Motorola MC54HC375AJ, MC74HC375ASD, MC74HC375ADW, MC74HC375ADT, MC74HC375AN Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Octal 3-State

Non-Inverting D Flip-Flop

High±Performance Silicon±Gate CMOS

The MC54/74HC374A is identical in pinout to the LS374. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

Data meeting the setup time is clocked to the outputs with the rising edge of the clock. The Output Enable input does not affect the states of the flip±flops, but when Output Enable is high, the outputs are forced to the high±impedance state; thus, data may be stored even when the outputs are not enabled.

The HC374A is identical in function to the HC574A which has the input pins on the opposite side of the package from the output. This device is similar in function to the HC534A which has inverting outputs.

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 266 FETs or 66.5 Equivalent Gates

LOGIC DIAGRAM

D0

3

2

Q0

5

4

Q1

D1

7

6

D2

Q2

8

9

DATA

D3

Q3

NONINVERTING

13

INPUTS

12

D4

Q4

OUTPUTS

14

D5

15

Q5

17

D6

16

18

Q6

D7

19

CLOCK

11

Q7

1

PIN 20 = VCC

OUTPUT ENABLE

PIN 10 = GND

FUNCTION TABLE

Inputs

Output

Output

Enable

Clock

D

Q

L

H

H

L

L

L

L

L,H,

X

No Change

H

X

X

Z

MC54/74HC374A

		J SUFFIX
	20	CERAMIC PACKAGE
		CASE 732±03
		1

		N SUFFIX
	20	PLASTIC PACKAGE
		CASE 738±03
		1

			DW SUFFIX
	20		SOIC PACKAGE
	1		CASE 751D±04
	20		SD SUFFIX
			SSOP PACKAGE
	1		CASE 940C±03
	20		DT SUFFIX
		TSSOP PACKAGE
	1
			CASE 948E±02
	ORDERING INFORMATION
	MC54HCXXXAJ		Ceramic
	MC74HCXXXAN		Plastic
	MC74HCXXXADW		SOIC
	MC74HCXXXASD		SSOP
	MC74HCXXXADT		TSSOP

PIN ASSIGNMENT

	OUTPUT		1	20	VCC
	ENABLE
	Q0		2	19	Q7
	D0		3	18	D7
	D1		4	17	D6
	Q1		5	16	Q6
	Q2		6	15	Q5
	D2		7	14	D5
	D3		8	13	D4
	Q3		9	12	Q4
	GND		10	11	CLOCK

X = don't care

Z = high impedance

8/96

Motorola, Inc. 1996

3±1

REV 7

MC54/74HC374A

MAXIMUM RATINGS*

	Symbol	Parameter	Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)	± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin	± 20	mA
	Iout	DC Output Current, per Pin	± 35	mA
	ICC	DC Supply Current, VCC and GND Pins	± 75	mA
	PD	Power Dissipation in Still Air, Plastic or Ceramic DIP²	750	mW
		SOIC Package²	500
		SSOP or TSSOP Package²	450
	Tstg	Storage Temperature	± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds		_C
		(Plastic DIP, SOIC, SSOP or TSSOP Package)	260
		(Ceramic DIP)	300

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

SSOP or TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.50	1.50	1.50	V
	Voltage	|Iout| v 20 μA	3.0	2.10	2.10	2.10
			4.5	3.15	3.15	3.15
			6.0	4.20	4.20	4.20
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.50	0.50	0.50	V
	Voltage	|Iout| v 20 μA	3.0	0.90	0.90	0.90
			4.5	1.35	1.35	1.35
			6.0	1.80	1.80	1.80
VOH	Minimum High±Level Output	Vin = VIH or VIL	2.0	1.90	1.90	1.90	V
	Voltage	|Iout| v 20 μA	4.5	4.40	4.40	4.40
			6.0	5.90	5.90	5.90
		Vin = VIH or VIL |Iout| v 2.4 mA	3.0	2.48	2.34	2.20
		|Iout| v 6.0 mA	4.5	2.98	3.84	3.70	V
		|Iout| v 7.8 mA	6.0	5.48	5.34	5.20

MOTOROLA	3±2	High±Speed CMOS Logic Data
		DL129 Ð Rev 6

MC54/74HC374A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VOL	Maximum Low±Level Output	Vin = VIH or VIL	2.0	0.10	0.10	0.10	V
	Voltage	|Iout| v 20 μA	4.5	0.10	0.10	0.10
			6.0	0.10	0.10	0.10
		Vin = VIH or VIL |Iout| v 2.4 mA	3.0	0.26	0.33	0.40
		|Iout| v 6.0 mA	4.5	0.26	0.33	0.40	V
		|Iout| v 7.8 mA	6.0	0.26	0.33	0.40
Iin	Maximum Input Leakage Current	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
IOZ	Maximum Three±State	Output in High±Impedance State	6.0	± 0.5	± 5.0	± 10	μA
	Leakage Current	Vin = VIL or VIH
		Vout = VCC or GND
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4	40	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
fmax	Maximum Clock Frequency (50% Duty Cycle)	2.0	6	5	4	MHz
		3.0	15	10	8
		4.5	30	24	20
		6.0	35	28	24
tPLH	Maximum Propagation Delay, Input Clock to Q	2.0	125	155	190	ns
tPHL	(Figures 1 and 5)	3.0	80	110	130
		4.5	25	31	38
		6.0	21	26	32
tPLZ	Maximum Propagation Delay, Output Enable to Q	2.0	150	190	225	ns
tPHZ	(Figures 3 and 6)	3.0	100	125	150
		4.5	30	38	45
		6.0	26	33	38
tPLZ	Maximum Propagation Delay, Output Enable to Q	2.0	150	190	225	ns
tPHZ	(Figures 3 and 6)	3.0	100	125	150
		4.5	30	38	45
		6.0	26	33	38
tTLH	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 5)	3.0	27	32	36
		4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance		10	10	10	pF
Cout	Maximum Three±State Output Capacitance		15	15	15	pF
	(Output in High±Impedance State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Enabled Output)*	34	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

High±Speed CMOS Logic Data	3±3	MOTOROLA
DL129 Ð Rev 6