Motorola MC54HC4353J, MC54HC4351J, MC74HC4353N, MC74HC4353DW, MC74HC4351DW Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Analog Multiplexers/ Demultiplexers with Address Latch

High±Performance Silicon±Gate CMOS

The MC54/74HC4351, and MC54/74HC4353 utilize silicon±gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range

(from VCC to VEE).

The Channel±Select inputs determine which one of the Analog Inputs/ Outputs is to be connected, by means of an analog switch, to the Common Output/Input. The data at the Channel±Select inputs may be latched by using the active±low Latch Enable pin. When Latch Enable is high, the latch is transparent. When either Enable 1 (active low) or Enable 2 (active high) is inactive, all analog switches are turned off.

The Channel±Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal±gate CMOS analog switches.

For multiplexers/demultiplexers without latches, see the HC4051, HC4052, and HC4053.

•Fast Switching and Propagation Speeds

•Low Crosstalk Between Switches

•Diode Protection on All Inputs/Outputs

•Analog Power Supply Range (VCC ± VEE) = 2.0 to 12.0 V

•Digital (Control) Power Supply Range (VCC ± GND) = 2.0 to 6.0 V

•Improved Linearity and Lower ON Resistance than Metal±Gate Types

•Low Noise

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: HC4351 Ð 222 FETs or 55.5 Equivalent Gates

HC4353 Ð 186 FETs or 46.5 Equivalent Gates

MC54/74HC4351

MC54/74HC4353

		J SUFFIX
	20	CERAMIC PACKAGE
		CASE 732±03
		1

		N SUFFIX
	20	PLASTIC PACKAGE
		CASE 738±03
		1

	DW SUFFIX
20	SOIC PACKAGE
1	CASE 751D±04
ORDERING INFORMATION
MC54HCXXXXJ	Ceramic
MC74HCXXXXN	Plastic

MC74HCXXXXDW SOIC

PIN ASSIGNMENT

MC54/74HC4351

X4		1	20	VCC
X6		2	19	X2
NC		3	18	X1
X		4	17	X0
X7		5	16	X3
X5		6	15	A
ENABLE 1		7	14	NC
ENABLE 2		8	13	B
VEE		9	12	C
GND		10	11	LATCH
				ENABLE
NC = NO CONNECTION

10/95

Motorola, Inc. 1995

REV 6

MC54/74HC4351 MC54/74HC4353

LOGIC DIAGRAM

MC54/74HC4351

Single±Pole, 8±Position Plus Common Off and Address Latch

				X0	17
				X1	18
				X2	19
		ANALOG		X3	16	MULTIPLEXER/	4	X	COMMON
INPUTS/OUTPUTS				X4	1	DEMULTIPLEXER			OUTPUT/INPUT
					6
				X5
					2
				X6
					5
				X7
		A	15	CHANNEL
CHANNEL±SELECT			13
		B		ADDRESS				PIN 20 = VCC
	INPUTS		12
		C			LATCH			PIN 9 = VEE
LATCH ENABLE			11					PIN 10 = GND
								PINS 3, 14 = NC
			7
SWITCH ENABLE 1
			8
ENABLES	ENABLE 2

FUNCTION TABLE

MC54/74HC4351

	Control Inputs				ON
Enable			Select		Channel
1	2	C	B	A	(LE = H)*
L	H	L	L	L	X0
L	H	L	L	H	X1
L	H	L	H	L	X2
L	H	L	H	H	X3
L	H	H	L	L	X4
L	H	H	L	H	X5
L	H	H	H	L	X6
L	H	H	H	H	X7
H	X	X	X	X	None
X	L	X	X	X	None

X = don't care

*When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states.

BLOCK DIAGRAM

MC54/74HC4353

Triple Single±Pole, Double±Position Plus Common Off and Address Latch

	X0	16
	X1	17	X SWITCH
	Y0	2
		1	Y SWITCH
	Y1

6

Z0 Z SWITCH

Z1

4

			A	15	CHANNEL
	CHANNEL±SELECT			13
			B		ADDRESS
		INPUTS		12
			C		LATCH
	LATCH ENABLE			11
				7
	SWITCH	ENABLE 1
				8
	ENABLES	ENABLE 2

18

X

	19	COMMON
		Y OUTPUT/INPUT

5

Z

PIN 20 = VCC

PIN 9 = VEE

PIN 10 = GND

PINS 3, 14 = NC

PIN ASSIGNMENT

	Y1	1	20	VCC
	Y0	2	19	Y
	NC	3	18	X
	Z1	4	17	X1
	Z	5	16	X0
	Z0	6	15	A
	ENABLE 1	7	14	NC
	ENABLE 2	8	13	B
	VEE	9	12	C
	GND	10	11	LATCH
				ENABLE
	NC = NO CONNECTION

FUNCTION TABLE

NOTE:

This device allows independent control of each switch. Channel±Select Input A controls the X Switch, Input B controls the Y Switch, and Input C controls the Z Switch.

	Control Inputs					On
Enable			Select			Channel
1	2	C	B	A		(LE = H)*
L	H	L	L	L	Z0	Y0	X0
L	H	L	L	H	Z0	Y0	X1
L	H	L	H	L	Z0	Y1	X0
L	H	L	H	H	Z0	Y1	X1
L	H	H	L	L	Z1	Y0	X0
L	H	H	L	H	Z1	Y0	X1
L	H	H	H	L	Z1	Y1	X0
L	H	H	H	H	Z1	Y1	X1
H	X	X	X	X		None
X	L	X	X	X		None

X = Don't Care

*When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states.

MOTOROLA

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MC54/74HC4351 MC54/74HC4353

MAXIMUM RATINGS*

	Symbol	Parameter			Value	Unit
	VCC	Positive DC Supply Voltage		(Ref. to GND)	± 0.5 to + 7.0	V
				(Ref. to VEE)	± 0.5 to 14.0
	VEE	Negative DC Supply Voltage (Ref. to GND)			± 7.0 to + 0.5	V
	VIS	Analog Input Voltage			VEE ± 0.5	V
					to VCC + 0.5
	Vin	DC Input Voltage (Ref. to GND)			± 1.5 to VCC + 1.5	V
	I	DC Current Into or Out of Any Pin			± 25	mA
	PD	Power Dissipation in Still Air, Plastic or Ceramic DIP²			750	mW
				SOIC Package²	500
	Tstg	Storage Temperature			± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for				_C
		10 Seconds	(Plastic DIP or SOIC Package)		260
				(Ceramic DIP)	300

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the ranges indicated in the Recommended Operating Conditions.

Unused digital input pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. See Applications Information.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	Positive DC Supply Voltage	(Ref. to GND)	2.0	6.0	V
		(Ref. to VEE)	2.0	12.0
VEE	Negative DC Supply Voltage	(Ref. to GND)	± 6.0	GND	V
VIS	Analog Input Voltage		VEE	VCC	V
Vin	Digital Input Voltage (Ref. to GND)		GND	VCC	V
VIO*	Static or Dynamic Voltage Across Switch		Ð	1.2	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time,	VCC = 2.0 V	0	1000	ns
	Channel Select or Enable	VCC = 4.5 V	0	500
	Inputs (Figure 9a)	VCC = 6.0 V	0	400

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted

					Guaranteed Limit
				VCC
					± 55 to	v _	v _
Symbol	Parameter	Test Conditions		V	_			Unit
					25 C	85 C	125 C
VIH	Minimum High±Level Input	Ron = Per Spec		2.0	1.5	1.5	1.5	V
	Voltage, Channel±Select or			4.5	3.15	3.15	3.15
	Enable Inputs			6.0	4.2	4.2	4.2
VIL	Maximum Low±Level Input	Ron = Per Spec		2.0	0.3	0.3	0.3	V
	Voltage, Channel±Select or			4.5	0.9	0.9	0.9
	Enable Inputs			6.0	1.2	1.2	1.2
Iin	Maximum Input Leakage	Vin = VCC or GND,		6.0	± 0.1	± 1.0	± 1.0	μA
	Current, Channel±Select or	VEE = ± 6.0 V
	Enable Inputs
ICC	Maximum Quiescent Supply	Channel Select = VCC or GND						μA
	Current (per Package)	Enables = VCC or GND		6.0	2	20	40
		VIS = VCC or GND	VEE = GND
		VIO = 0 V	VEE = ± 6.0	6.0	8	80	160

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

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MOTOROLA

MC54/74HC4351 MC54/74HC4353

DC ELECTRICAL CHARACTERISTICS Analog Section

					Guaranteed Limit
			VCC	VEE
					± 55 to	v _	v	_
Symbol	Parameter	Test Conditions	V	V	_				Unit
					25 C	85 C		125 C
Ron	Maximum ªONº Resistance	Vin = VIL or VIH	4.5	0.0	190	240		280	Ω
		VIS = VCC to VEE	4.5	± 4.5	120	150		170
		IS v 2.0 mA (Figures 1, 2)	6.0	± 6.0	100	125		140
		Vin = VIL or VIH	4.5	0.0	150	190		230
		VIS = VCC or VEE (Endpoints)	4.5	± 4.5	100	125		140
		IS v 2.0 mA (Figures 1, 2)	6.0	± 6.0	80	100		115
Ron	Maximum Difference in ªONº	Vin = VIL or VIH	4.5	0.0	30	35		40	Ω
	Resistance Between Any Two	VIS = 1/2 (VCC ± VEE)	4.5	± 4.5	12	15		18
	Channels in the Same Package	IS v 2.0 mA	6.0	± 6.0	10	12		14
Ioff	Maximum Off±Channel Leakage	Vin = VIL or VIH	6.0	± 6.0	0.1	0.5		1.0	μA
	Current, Any One Channel	VIO = VCC ± VEE
		Switch Off (Figure 3)
	Maximum Off±Channel Leakage	Vin = VIL or VIH
	Current, Common Channel	VIO = VCC ± VEE
	HC4351	Switch Off (Figure 4)	6.0	± 6.0	0.2	2.0		4.0
	HC4353		6.0	± 6.0	0.1	1.0		2.0
Ion	Maximum On±Channel Leakage	Vin = VIL or VIH							μA
	Current, Channel to Channel	Switch to Switch = VCC ± VEE
	HC4351	(Figure 5)	6.0	± 6.0	0.2	2.0		4.0
	HC4353		6.0	± 6.0	0.1	1.0		2.0

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

														Guaranteed Limit
									VCC					± 55 to		v _		v	_
Symbol		Parameter								V				_			C					Unit
														25 C		85			125 C
tPLH,		Maximum Propagation Delay, Channel±Select to Analog Output								2.0				370		465			550			ns
tPHL		(Figure 9)								4.5				74		93			110
										6.0				63		79			94
tPLH,		Maximum Propagation Delay, Analog Input to Analog Output								2.0				60		75			90			ns
tPHL		(Figure 10)								4.5				12		15			18
										6.0				10		13			15
tPLH,		Maximum Propagation Delay, Latch Enable to Analog Output								2.0				325		410			485			ns
tPHL		(Figure 12)								4.5				65		82			97
										6.0				55		70			82
tPLZ,		Maximum Propagation Delay, Enable 1 or 2 to Analog Output								2.0				290		365			435			ns
tPHZ		(Figure 11)								4.5				58		73			87
										6.0				49		62			74
tPZL,		Maximum Propagation Delay, Enable 1 or 2 to Analog Output								2.0				345		435			515			ns
tPZH		(Figure 11)								4.5				69		87			103
										6.0				59		74			87
Cin		Maximum Input Capacitance								Ð				10		10			10			pF
Cl/O		Maximum Capacitance Analog I/O	Enable 1 = VIH, Enable 2 = VIL							Ð				35		35			35			pF
		Common O/I: HC4351								Ð				130		130			130
		HC4353												50		50			50
		Feedthrough								Ð				1.0		1.0			1.0
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
														Typical @ 25°C, VCC = 5.0 V
CPD		Power Dissipation Capacitance (Per Package) (Figure 14)*													45 (HC4351)							pF
															45 (HC4353)
* Used to determine the no±load dynamic power consumption: P				= C	PD	V	CC	2f + I	CC	V	CC	. For load considerations, see Chapter 2 of the
			D

Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA

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