MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview |
MC54/74HC597A |
|
8-Bit Serial or Parallel-Input/ Serial-Output Shift Register with Input Latch
High±Performance Silicon±Gate CMOS
The MC54/74HC597A is identical in pinout to the LS597. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of an 8±bit input latch which feeds parallel data to an 8±bit shift register. Data can also be loaded serially (see Function Table).
The HC597A is similar in function to the HC589A, which is a 3±state device.
• Output Drive Capability: 10 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2 to 6 V
•Low Input Current: 1 μA
• High Noise Immunity Characteristic of CMOS Devices
•In Compliance with the Requirements Defined by JEDEC Standard No. 7A
•Chip Complexity: 516 FETs or 129 Equivalent Gates
LOGIC DIAGRAM
SERIAL
DATA 
SA 14
INPUT
|
|
A |
15 |
|
|
|
|
1 |
|
|
|
|
|
B |
|
|
|
|
|
2 |
|
|
|
|
|
C |
|
|
|
PARALLEL |
|
3 |
|
|
|
|
D |
|
|
||
|
|
|
|||
DATA |
|
4 |
INPUT |
SHIFT |
|
|
|
||||
INPUTS |
|
E |
|||
|
5 |
LATCH |
REGISTER |
||
|
|
F |
|||
|
|
|
|
|
6
G
7
H
12 LATCH CLOCK 
11
SHIFT CLOCK
SERIAL SHIFT/ 13
PARALLEL LOAD
10
RESET
SERIAL
9 QH
DATA OUTPUT
PIN 16 = VCC
PIN 8 = GND
|
|
J SUFFIX |
|
16 |
CERAMIC PACKAGE |
||
|
CASE 620±10 |
||
|
1 |
|
|
|
|
N SUFFIX |
|
16 |
PLASTIC PACKAGE |
||
|
CASE 648±08 |
||
|
|
||
|
1 |
|
|
|
|
D SUFFIX |
|
16 |
|
SOIC PACKAGE |
|
|
1 |
CASE 751B±05 |
|
16 |
|
DT SUFFIX |
|
TSSOP PACKAGE |
|||
|
|||
|
1 |
CASE 948F±01 |
|
|
ORDERING INFORMATION |
||
|
MC54HCXXXAJ |
Ceramic |
|
|
MC74HCXXXAN |
Plastic |
|
|
MC74HCXXXAD |
SOIC |
|
|
MC74HCXXXADT |
TSSOP |
|
PIN ASSIGNMENT
B |
1 |
16 |
|
VCC |
|
|
|||||
|
|||||
C |
2 |
15 |
|
A |
|
D |
3 |
14 |
|
SA |
|
|
|||||
|
|||||
E |
4 |
13 |
|
|
SERIAL SHIFT/ |
|
PARALLEL LOAD |
||||
F |
|
|
|
||
5 |
12 |
|
LATCH CLOCK |
||
|
|||||
G |
6 |
11 |
|
SHIFT CLOCK |
|
|
|||||
H |
7 |
10 |
|
RESET |
|
|
|||||
GND |
8 |
9 |
|
QH |
|
|
|||||
|
|||||
|
|
|
|
|
|
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/95
Motorola, Inc. 1995 |
REV 0 |
MC54/74HC597A
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
|
|
|
|
|
|
VCC |
DC Supply Voltage (Referenced to GND) |
± 0.5 to + 7.0 |
V |
|
Vin |
DC Input Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
|
Vout |
DC Output Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
|
Iin |
DC Input Current, per Pin |
± 20 |
mA |
|
Iout |
DC Output Current, per Pin |
± 25 |
mA |
|
ICC |
DC Supply Current, VCC and GND Pins |
± 50 |
mA |
|
PD |
Power Dissipation in Still Air, Plastic or Ceramic DIP² |
750 |
mW |
|
|
SOIC Package² |
500 |
|
|
|
TSSOP Package² |
450 |
|
|
|
|
|
|
|
Tstg |
Storage Temperature |
± 65 to + 150 |
_C |
|
TL |
Lead Temperature, 1 mm from Case for 10 Seconds |
|
_C |
|
|
||||
|
(Plastic DIP, SOIC or TSSOP Package) |
260 |
|
|
|
(Ceramic DIP) |
300 |
|
|
|
|
|
|
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C
ÐCeramic DIP: ± 10 mW/_C from 100_ to 125_C
ÐSOIC Package: ± 7 mW/_C from 65_ to 125_C
TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
|
Min |
Max |
Unit |
|
|
|
|
|
|
VCC |
DC Supply Voltage (Referenced to GND) |
|
2.0 |
6.0 |
V |
Vin, Vout |
DC Input Voltage, Output Voltage (Referenced to GND) |
0 |
VCC |
V |
|
TA |
Operating Temperature, All Package Types |
|
± 55 |
+ 125 |
_C |
tr, tf |
Input Rise and Fall Time |
VCC = 2.0 V |
0 |
1000 |
ns |
|
(Figure 1) |
VCC = 3.0 V |
0 |
600 |
|
|
|
VCC = 4.5 V |
0 |
500 |
|
|
|
VCC = 6.0 V |
0 |
400 |
|
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
|
|
|
|
Guaranteed Limit |
|
||
|
|
|
VCC |
|
|
|
|
|
|
|
± 55 to |
|
|
|
|
Symbol |
Parameter |
Test Conditions |
V |
25_C |
v 85_C |
v 125_C |
Unit |
|
|
|
|
|
|
|
|
VIH |
Minimum High±Level Input |
Vout = 0.1 V or VCC ± 0.1 V |
2.0 |
1.5 |
1.5 |
1.5 |
V |
|
Voltage |
|Iout| v 20 μA |
3.0 |
2.1 |
2.1 |
2.1 |
|
|
|
|
4.5 |
3.15 |
3.15 |
3.15 |
|
|
|
|
6.0 |
4.2 |
4.2 |
4.2 |
|
|
|
|
|
|
|
|
|
VIL |
Maximum Low±Level Input |
Vout = 0.1 V or VCC ± 0.1 V |
2.0 |
0.5 |
0.5 |
0.5 |
V |
|
Voltage |
|Iout| v 20 μA |
3.0 |
0.9 |
0.9 |
0.9 |
|
|
|
|
4.5 |
1.35 |
1.35 |
1.35 |
|
|
|
|
6.0 |
1.8 |
1.8 |
1.8 |
|
|
|
|
|
|
|
|
|
VOH |
Minimum High±Level Output |
Vin = VIH or VIL |
2.0 |
1.9 |
1.9 |
1.9 |
V |
|
Voltage |
|Iout| v 20 μA |
4.5 |
4.4 |
4 4 |
4 4 |
|
|
|
|
6.0 |
5.9 |
5.9 |
5.9 |
|
|
|
|
|
|
|
|
|
|
|
Vin = VIH or VIL |Iout| v 2.4 mA |
3.0 |
2.48 |
2.34 |
2.20 |
|
|
|
|Iout| v 4.0 mA |
4.5 |
3.98 |
3.84 |
3.70 |
|
|
|
|Iout| v 5.2 mA |
6.0 |
5.48 |
5.34 |
5.20 |
|
MOTOROLA |
2 |
MC54/74HC597A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
|
|
|
|
Guaranteed Limit |
|
||
|
|
|
|
|
|
|
|
|
|
|
VCC |
± 55 to |
|
|
|
Symbol |
Parameter |
Test Conditions |
V |
25_C |
v 85_C |
v 125_C |
Unit |
|
|
|
|
|
|
|
|
VOL |
Maximum Low±Level Output |
Vin = VIH or VIL |
2.0 |
0.1 |
0.1 |
0.1 |
V |
|
Voltage |
|Iout| v 20 μA |
4.5 |
0.1 |
0.1 |
0.1 |
|
|
|
|
6.0 |
0.1 |
0.1 |
0.1 |
|
|
|
|
|
|
|
|
|
|
|
Vin = VIH or VIL |Iout| v 2.4 mA |
3.0 |
0.26 |
0.33 |
0.40 |
|
|
|
|Iout| v 4.0 mA |
4.5 |
0.26 |
0.33 |
0.40 |
|
|
|
|Iout| v 5.2 mA |
6.0 |
0.26 |
0.33 |
0.40 |
|
Iin |
Maximum Input Leakage Current |
Vin = VCC or GND |
6.0 |
± 0.1 |
± 1.0 |
± 1.0 |
μA |
ICC |
Maximum Quiescent Supply |
Vin = VCC or GND |
6.0 |
4 |
40 |
160 |
μA |
|
Current (per Package) |
Iout = 0 μA |
|
|
|
|
|
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
|
|
|
Guaranteed Limit |
|
|
||
|
|
VCC |
|
|
|
|
|
|
|
± 55 to |
|
|
|
|
|
Symbol |
Parameter |
V |
25_C |
v 85_C |
v 125_C |
|
Unit |
|
|
|
|
|
|
|
|
fmax |
Maximum Clock Frequency (50% Duty Cycle) |
2.0 |
10 |
9 |
8 |
|
MHz |
|
(Figures 2 and 8) |
3.0 |
15 |
14 |
12 |
|
|
|
|
4.5 |
30 |
28 |
25 |
|
|
|
|
6.0 |
50 |
45 |
40 |
|
|
|
|
|
|
|
|
|
|
tPLH, |
Maximum Propagation Delay, Latch Clock to QH |
2.0 |
175 |
225 |
275 |
|
ns |
tPHL |
(Figures 1 and 8) |
3.0 |
100 |
110 |
125 |
|
|
|
|
4.5 |
40 |
50 |
60 |
|
|
|
|
6.0 |
30 |
40 |
50 |
|
|
|
|
|
|
|
|
|
|
tPLH, |
Maximum Propagation Delay, Shift Clock to QH |
2.0 |
160 |
200 |
240 |
|
ns |
tPHL |
(Figures 2 and 8) |
3.0 |
90 |
130 |
160 |
|
|
|
|
4.5 |
30 |
40 |
48 |
|
|
|
|
6.0 |
25 |
30 |
40 |
|
|
|
|
|
|
|
|
|
|
tPHL |
Maximum Propagation Delay, Reset to QH |
2.0 |
160 |
200 |
240 |
|
ns |
|
(Figures 3 and 8) |
3.0 |
90 |
130 |
160 |
|
|
|
|
4.5 |
30 |
40 |
48 |
|
|
|
|
6.0 |
25 |
30 |
40 |
|
|
|
|
|
|
|
|
|
|
tPLH, |
Maximum Propagation Delay, Serial Shift/Parallel Load to QH |
2.0 |
160 |
200 |
240 |
|
ns |
tPHL |
(Figures 4 and 8) |
3.0 |
90 |
130 |
160 |
|
|
|
|
4.5 |
30 |
40 |
48 |
|
|
|
|
6.0 |
25 |
30 |
40 |
|
|
|
|
|
|
|
|
|
|
tTLH, |
Maximum Output Transition Time, Any Output |
2.0 |
75 |
95 |
110 |
|
ns |
tTHL |
(Figures 1 and 8) |
3.0 |
27 |
32 |
36 |
|
|
|
|
4.5 |
15 |
19 |
22 |
|
|
|
|
6.0 |
13 |
16 |
19 |
|
|
|
|
|
|
|
|
|
|
Cin |
Maximum Input Capacitance |
Ð |
10 |
10 |
10 |
|
pF |
NOTES: |
|
|
|
|
|
|
|
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D). |
|
||||||
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D). |
|
||||||
|
|
|
|
|
|||
|
|
|
Typical @ 25°C, VCC = 5.0 V |
|
|
||
CPD |
Power Dissipation Capacitance (Per Package)* |
|
|
40 |
|
|
pF |
* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
3 |
MOTOROLA |
MC54/74HC597A
PIN DESCRIPTIONS
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs is stored in the input latch on the rising edge of the Latch Clock input.
SA (Pin 14)
Serial data input. Data on this input is shifted into the shift register on the rising edge of the Shift Clock input it Serial Shift/Parallel Load is high. Data on this input is ignored when Serial Shift/Parallel Load is low.
Reset (Pin 10)
Asynchronous, Active±low shift register reset. A low level applied to this input resets the shift register to a low level, but does not change the data in the input latch.
Shift Clock (Pin 11)
Serial shift register clock. A low±to±high transition on this input shifts data on the Serial Data Input into the shift register and data in stage H is shifted out QH, being replaced by the data previously stored in stage G.
Latch Clock (Pin 12)
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied to this pin, the shift register is allowed to serially shift data. When a low level is applied to this pin, the shift register accepts parallel data from the input latch, and serial shifting is inhibited.
Latch clock. A low±to±high transition on this input loads the parallel data on inputs A±H into the input latch.
OUTPUT
QH (Pin 9)
Serial data output. This pin is the output from the last stage of the shift register.
MOTOROLA |
4 |
Loading...