April 1999
LM2202
230 MHz Video Amplifier System
General Description
The LM2202 is a very high frequency video amplifier system intended for use in high resolution monochrome or RGB color monitor applications. In addition to the wideband video amplifier the LM2202 contains a gated differential input black level clamp comparator for brightness control, a DC controlled attenuator for contrast control and a DC controlled sub contrast attenuator for drive control. The DC control for the contrast attenuator is pinned out separately to provide a more accurate control system for RGB color monitor applications. All DC controls offer a high input impedance and operate over a 0V to 4V range for easy interface to bus controlled alignment systems. The LM2202 operates from a nominal 12V supply but can be operated with supply voltages down to 8V for applications that require reduced IC package power dissipation characteristics.
Features
nWideband video amplifier
(f−3dB = 230 MHz at VO = 4 VPP)
ntr, tf = 1.5 ns at VO = 4 VPP
nExternally gated comparator for brightness control
n0V to 4V high input impedance DC contrast control (>40 dB range)
n0V to 4V high input impedance DC drive control (±3 dB range)
nEasy to parallel three LM2202s for optimum color tracking in RGB systems
nOutput stage clamps to 0.65V and provides up to 9V output voltage swing
nOutput stage directly drives most hybrid or discrete CRT amplifier stages
nReplacement for the LM1202
Applications
nHigh resolution CRT monitors
nVideo switches
nVideo AGC amplifier
nWideband amplifier with gain and DC offset control
Block and Connection Diagram
DS012591-1
Order Number LM2202N or LM2202M
See NS Package Number N20A or M20B
System Amplifier Video MHz 230 LM2202
© 1999 National Semiconductor Corporation |
DS012591 |
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage VCC Pins 4, 7, 16 to |
13.5V |
Ground Pins 5, 13, 15 |
|
Voltage at Any Input Pin (VIN) |
VCC ³ VIN ³ GND |
Video Output Current (I17) |
28 mA |
Package Power Dissipation at |
|
TA = 25ÊC |
1.56W |
(Above 25ÊC Derate Based qJA and TJ) |
|
Package Thermal Resistance (qJA) |
|
N20A |
68ÊC/W |
M20B |
90ÊC/W |
Junction Temperature (TJ) |
150ÊC |
Storage Temperature Range (Tstg) |
−65ÊC to +150ÊC |
Lead Temperature |
|
N Package (Soldering, 10 sec.) |
265ÊC |
ESD Susceptibility |
|
Human Body Model: 100 pF |
|
Discharged through a 1.5k |
|
Resistor |
1.5 kV |
Operating Ratings (Note 2)
Temperature Range |
−20ÊC to +80ÊC |
Supply Voltage (VCC) |
8V £ VCC £ 13.2V |
DC Electrical Characteristics
See Test Circuit (Figure 1), TA = 25ÊC, V4 = V7 = V16 = 12V, S1 Open, V19 = 4V, V8 = 4V, V9 = 4V, V14 = 0V unless otherwise noted.
Symbol |
Parameter |
|
Conditions |
Typical |
Limit (Note |
Units |
|
(Note 3) |
4) |
||||
|
|
|
|
|
||
|
|
|
|
|
|
|
IS 4, 7, 16 |
Total Supply Current |
RLOAD = ∞ (Note 5) |
48 |
60 |
mA (max) |
|
V6 |
Video Input Bias Voltage |
|
|
2.4 |
2 |
V (min) |
V14L |
Clamp Gate Low Input Voltage |
Clamp Comparator On |
|
0.8 |
V (max) |
|
V14H |
Clamp Gate High Input Voltage |
Clamp Comparator Off |
|
2 |
V (min) |
|
I14L |
Clamp Gate Low Input Current |
V14 = 0V |
−0.5 |
|
µA |
|
I14H |
Clamp Gate High Input Current |
V14 = 12V |
0.005 |
|
µA |
|
I12+ |
Clamp Cap Charge Current |
V12 = 0V |
800 |
500 |
µA (min) |
|
I12− |
Clamp Cap Discharge Current |
V12 |
= 5V |
−800 |
−500 |
µA (min) |
V17L |
Video Output Low Voltage |
V12 |
= 0V |
0.2 |
0.65 |
V (max) |
V17H |
Video Output High Voltage |
V12 |
= 6V |
10 |
9 |
V (min) |
VOS |
Comparator Input Offset Voltage |
V18 − V 19 |
15 |
±50 |
mV (max) |
|
AC Electrical Characteristics
See Test Circuit (Figure 1), TA = 25ÊC, V4 = V7 = V16 = 12V, S1 Closed, V19 = 4V, V8 = 4V, V9 = 4V, V14 = 0V unless otherwise noted.
Symbol |
Parameter |
|
Conditions |
Typical |
Limit (Note |
Units |
|
(Note 3) |
4) |
||||
|
|
|
|
|
||
|
|
|
|
|
|
|
RIN |
Video Amplifier Input Resistance |
fIN = 12 kHz |
20 |
|
kW |
|
AV max |
Video Amplifier Gain |
V8 = 4V, V9 = 4V |
20 |
16 |
V/V (min) |
|
DAV 2V |
Attenuation at 2V |
Ref: AV max, V8 = 2V |
−6 |
|
dB |
|
DAV 0.5V |
Attentuation at 0.5V |
Ref: AV max, V8 = 0.5V |
−38 |
−23 |
dB (min) |
|
D Drive |
D Gain Range |
V9 = 0V to 4V |
6 |
5 |
dB (min) |
|
THD |
Video Amplifier Distortion |
VO = 4 |
VPP, fIN = 12 kHz |
0.5 |
1 |
% (max) |
f−3 dB |
Video Amplifier Bandwidth (Note 6) |
VO = 4 |
VPP |
230 |
|
MHz |
tr |
Output Rise Time (Note 6) |
VO = 4 |
VPP |
1.5 |
2 |
ns (max) |
tf |
Output Fall Time (Note 6) |
VO = 4 |
VPP |
1.5 |
2 |
ns (max) |
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. For guaranteed specifications and test conditions see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: Typical specifications are specified at +25ÊC and represent the most likely parametric norm.
Note 4: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 5: The supply current specified is the quiescent current for VCC1, VCC2 and VCC3 with RLoad = ∞, see Figure 1's test circuit. The total supply current also depends on the output load, RLoad. The increase in device power dissipation due to RLoad must be taken into account when operating the device at the maximum ambient temperature.
Note 6: When measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuit board is recommended. The measured rise and fall times are effective rise and fall times, taking into account the rise and fall times of the generator and the oscilloscope.
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Test Circuit
DS012591-2
FIGURE 1. LM2202 Test Circuit
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Typical Performance Characteristics (VCC = 12V, TA = 25ÊC unless otherwise specified)
Quiescent Supply Current |
Attenuation vs Drive Voltage |
vs Supply Voltage |
|
DS012591-4
|
DS012591-3 |
Contrast vs Frequency |
Drive vs Frequency |
DS012591-5 |
DS012591-6 |
Attenuation vs
Contrast Voltage
DS012591-7
Circuit Description
Figure 2 shows a block diagram of the LM2202 video amplifier along with contrast and brightness (black level) control. Contrast control is a DC-operated attenuator which varies the AC gain of the amplifier. Signal attenuation (contrast) is achieved by varying the base drive to a differential pair and thereby unbalancing the current through the differential pair. As shown in Figure 2, pin 20 provides a 5.3V bias voltage for
the positive input of the attenuator (pin 1). Pin 3 provides a control voltage for the negative input (pin 2) of the attenuator. The voltage at pin 3 varies as the voltage at the contrast control input (pin 8) varies thus providing signal attenuation. The gain is maximum (0 dB attenuation) if the voltage at pin 8 is 4V and is minimum (maximum attenuation) if the voltage at pin 8 is 0V. The 0V to 4V DC-operated drive control at pin 9
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Circuit Description (Continued)
provides a 6 dB gain adjustment range. This feature is necessary for RGB applications where independent gain adjustment of each channel is required.
The brightness or black level clamping requires a ªsample and holdº circuit which holds the DC bias of the video amplifier constant during the black level reference portion of the video waveform. Black level clamping, often referred to as DC restoration, is accomplished by applying a back porch clamp signal to the clamp gate input pin (pin 14). The clamp comparator is enabled when the clamp signal goes low during the black level reference period (see Figure 2). When the clamp comparator is enabled, the clamp capacitor connected to pin 12 is either charged or discharged until the voltage at the minus input of the comparator matches the voltage set at the plus input of the comparator. During the video portion of the signal, the clamp comparator is disabled and the clamp capacitor holds the proper DC bias. In a DC coupled cathode drive application, picture brightness function can be achieved by varying the voltage at the comparator's plus input. Note that the back porch clamp pulse width (tW in Figure 2) must be greater than 100 ns for proper operation.
VIDEO AMPLIFIER SECTION (Input Stage)
A simplified schematic of LM2202's video amplifier input stage is shown in Figure 3. The 5.4V zener diode, Q1, Q6 and R2 bias the base of Q7 at 2.6V. The AC coupled video
signal applied to pin 6 is referenced to the 2.6V bias voltage. Transistor Q7 buffers the video signal, VIN, and Q8 converts the voltage to current. The AC collector current through Q8 is IC8 = VIN/R9. Under maximum gain condition, transistors Q9 and Q11 are off and all of IC8 flows through the load resistors R10 and R11. The maximum signal gain at the base of Q13 is, AV1 = −(R10 + R11)/R9 = −2. Signal attenuation is achieved by varying the base drive to the differential pairs Q9, Q10 and Q11, Q12 thereby unbalancing the collector currents through the transistor pairs. Base of Q10 is biased at 5.3V by externally connecting pin 1 to pin 20 through a 100Ω resistor. Pin 2 is connected to pin 3 through a 100Ω resistor. Adjusting the contrast voltage at pin 8 produces a control voltage at pin 3 which drives the base of Q9. By varying the voltage at the base of Q9, Q8's collector current (IC8) is diverted away from the load resistors R10 and R11, thereby providing signal attenuation. Maximum attenuation is achieved when all of IC8 flows through Q9 and no current flows through the load resistors.
The differential pair Q11 and Q12 provide drive control. Q12's base is internally biased at 7.3V. Adjusting the voltage at the drive control input (pin 9) produces a control voltage at the base of Q11. With Q9 off and Q12 off, all of IC8 flows through R10, thus providing a gain of AV1 = −(R10/R9) x V IN = −1. Drive control thus provides a 6 dB attenuation range.
DS012591-8
FIGURE 2. Block Diagram of the LM2202 Video Amplifier with Contrast and Brightness (Black Level) Control
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Circuit Description (Continued)
DS012591-9
FIGURE 3. Simplified Schematic of the LM2202 Video Amplifier Input Stage
VIDEO AMPLIFIER SECTION (Output Stage)
A simplified schematic of LM2202's video amplifier output stage is shown in Figure 4. The output stage is the second gain stage. Ideally the gain of the second gain stage would be AV2 = −R21/R18 = −16. Because of the output stage's low open loop gain, the gain is approximately AV2 = −10. Thus the maximum gain of the video amplifier is AV = AV1 x AV2 = 20. Transistors Q23 and Q24 provide a push-pull drive to the load. The output voltage can swing from 0.2V to 10V.
CONTRAST CONTROL SECTION
A simplified schematic of LM2202's contrast control section is shown in Figure 5. A 0V to 4V DC voltage is applied at the contrast input (pin 8). Transistors Q29, Q30 and Q34 buffer and level shift the contrast voltage to the base of Q36. The voltage at the emitter of Q36 equals the contrast voltage (Vcont) and the current through Q36's collector is given by IC36 = Vcont/R28.
Transistor Q36's collector current is used to unbalance the current through the differential pair comprised of Q38 and Q40. Q40's base is internally biased at 5.3V and made avail-
able at pin 20. Pin 20 is externally connected to pin 1 through a 100Ω resistor (see Figure 2 and Figure 3). The base of Q38 (pin 3) is externally connected to pin 2 through a 100Ω
resistor (see Figure 2 and Figure 3). With Vcont = 2V, the differential pair (Q38, Q40) is balanced and the voltage at pins
1 and 2 is 5.3V. Under this condition, Q8's collector current is equally split between Q9 and Q10 (see Figure 3) and the amplifier's gain is half the maximum gain. If contrast voltage at pin 8 is greater than 2V then Q36's collector current increases, thus pulling Q38's collector node lower and consequently moving Q38's base below 5.3V. With pin 2 at a lower voltage than pin 1, current through Q10 (see Figure 3) in-
creases and the amplifier's gain increases. With Vcont = 4V, the amplifier's gain is maximum.
If the contrast voltage at pin 8 is less than 2V then Q36's collector current decreases and Q38's base is pulled above 5.3V. With pin 2 voltage greater than pin 1 voltage, less current flows through Q10 (see Figure 3), consequently the am-
plifier's gain decreases. With Vcont = 0V, the amplifier's gain is minimum (i.e., maximum attenuation).
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