Analog Devices SMP04EP, SMP04EQ, SMP04ES Datasheet

a		CMOS Quad
		Sample-and-Hold Amplifier
		SMP04*

FEATURES

Four Independent Sample-and-Holds Internal Hold Capacitors

High Accuracy: 12 Bit

Very Low Droop Rate: 2 mV/s typ Output Buffers Stable for CL ≤ 500 pF TTL/CMOS Compatible Logic Inputs Single or Dual Supply Applications Monolithic Low Power CMOS Design

APPLICATIONS

Signal Processing Systems

Multichannel Data Acquisition Systems

Automatic Test Equipment

Medical and Analytical Instrumentation

Event Analysis

DAC Deglitching

FUNCTIONAL BLOCK DIAGRAM

VDD

	SMP04
VIN1	VOUT1
S/H1
	VSS
VIN2	VOUT2
S/H2
	VSS
VIN3	VOUT3
S/H3
	VSS
VIN4	VOUT4
S/H4
	VSS

VSS

DGND

GENERAL DESCRIPTION

The SMP04 is a monolithic quad sample-and-hold; it has four internal precision buffer amplifiers and internal hold capacitors. It is manufactured in ADI’s advanced oxide isolated CMOS technology to obtain the high accuracy, low droop rate and fast acquisition time required by data acquisition and signal processing systems. The device can acquire an 8-bit input signal to

± 1/2 LSB in less than four microseconds. The SMP04 can operate from single or dual power supplies with TTL/CMOS logic compatibility. Its output swing includes the negative supply.

The SMP04 is ideally suited for a wide variety of sample-and- hold applications, including amplifier offset or VCA gain adjustments. One or more can be used with single or multiple DACs to provide multiple setpoints within a system.

The SMP04 offers significant cost and size reduction over equivalent module or discrete designs. It is available in a 16-lead hermetic or plastic DIP and surface mount SOIC packages. It is specified over the extended industrial temperature range of –40°C to +85°C.

*Protected by U.S. Patent No. 4,739,281.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Fax: [phone]	© Analog Devices, Inc., 1998

SMP04–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS (@ VDD = +12.0 V, VSS = DGND = 0 V, RL = No Load, TA = Operating Temperature Range specified in Absolute Maximum Ratings, unless otherwise noted.)

Parameter	Symbol	Conditions	Min	Typ	Max	Units
Linearity Error				0.01		%
Buffer Offset Voltage	VOS	VIN = 6 V	–10	±2.5	+10	mV
Hold Step	VHS	VIN = 6 V, TA = +25°C to +85°C		2.5	4	mV
		VIN = 6 V, TA = –40°C			5	mV
Droop Rate	V/ t	VIN = 6 V, TA = +25°C		2	25	mV/s
Output Source Current1	ISOURCE	VIN = 6 V	1.2			mA
Output Sink Current1	ISINK	VIN = 6 V	0.5			mA
Output Voltage Range	OVR	RL = 20 kΩ	0.06		10.0	V
		RL = 10 kΩ	0.06		9.5	V
LOGIC CHARACTERISTICS			2.4			V
Logic Input High Voltage	VINH
Logic Input Low Voltage	VINL				0.8	V
Logic Input Current	IIN			0.5	1	µA
DYNAMIC PERFORMANCE2		TA = +25°C, 0 V to 10 V Step to 0.1%				µs
Acquisition Time3	tAQ			3.5	4.25
		–40°C ≤ TA ≤ +85°C		3.75	5.25	µs
Acquisition Time3	tAQ	TA = +25°C, 0 V to 10 V Step to 0.01%		9		µs
Hold Mode Settling Time	tH	To 1 mV		1		µs
Slew Rate4	SR	RL = 20 kΩ	3	4		V/µs
Capacitive Load Stability	CL	<30% Overshoot		500		pF
Analog Crosstalk		0 V to 10 V Step		–80		dB
SUPPLY CHARACTERISTICS		10.8 V ≤ VDD ≤ 13.2 V	60	75		dB
Power Supply Rejection Ratio	PSRR
Supply Current	IDD			4	7	mA
Power Dissipation	PDIS				84	mW

ELECTRICAL CHARACTERISTICS (@ VDD = +5.0 V, VSS = –5.0 V, DGND = 0.0 V, RL = No Load, TA = Operating Temperature Range specified in Absolute Maximum Ratings, unless otherwise noted.)

Parameter	Symbol	Conditions	Min	Typ	Max	Units
Linearity Error				0.01		%
Buffer Offset Voltage	VOS	VIN = 0 V	–10	±2.5	+10	mV
Hold Step	VHS	VIN = 0 V, TA = +25°C to +85°C		2.5	4	mV
		VIN = 0 V, TA = –40°C			5	mV
Droop Rate	V/ t	VIN = 0 V, TA = +25°C		2	25	mV/s
Output Resistance	ROUT			1		Ω
Output Source Current1	ISOURCE	VIN = 0 V	1.2			mA
Output Sink Current1	ISINK	VIN = 0 V	0.5			mA
Output Voltage Range	OVR	RL = 20 kΩ	–3.0		+3.0	V
LOGIC CHARACTERISTICS			2.4			V
Logic Input High Voltage	VINH
Logic Input Low Voltage	VINL				0.8	V
Logic Input Current	IIN			0.5	1	µA
DYNAMIC PERFORMANCE2						µs
Acquisition Time3	tAQ	–3 V to +3 V Step to 0.1%		3.6	11
Acquisition Time3	tAQ	–3 V to +3 V Step to 0.01%		9		µs
Hold Mode Settling Time	tH	To 1 mV		1		µs
Slew Rate5	SR	RL = 20 kΩ		3		V/µs
Capacitive Load Stability	CL	<30% Overshoot	500			pF
SUPPLY CHARACTERISTICS		±5 V ≤ VDD ≤ ±6 V	60	75		dB
Power Supply Rejection Ratio	PSRR
Supply Current	IDD			3.5	5.5	mA
Power Dissipation	PDIS				55	mW

NOTES

1Outputs are capable of sinking and sourcing over 20 mA, but linearity and offset are guaranteed at specified load levels. 2All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 3This parameter is guaranteed without test.

4Slew rate is measured in the sample mode with a 0 V to 10 V step from 20% to 80%. 5Slew rate is measured in the sample mode with a –3 V to +3 V step from 20% to 80%.

Specifications are subject to change without notice.

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SMP04

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

VDD to DGND . . . . . . . . . . . . . . . . . . . . .	. . . . . . –0.3 V, 17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . –0.7 V, 17 V
VLOGIC to DGND . . . . . . . . . . . . . . . . . . .	. . . . . –0.3 V, VDD
VIN to DGND . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . VSS, VDD
VOUT to DGND . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . VSS, VDD
Analog Output Current . . . . . . . . . . . . . . .	. . . . . . . . ±20 mA
(Not Short-Circuit Protected)
Digital Input Voltage to DGND . . . . . . .	–0.3 V, VDD + 0.3 V
Operating Temperature Range	–40°C to +85°C
EQ, EP, ES . . . . . . . . . . . . . . . . . . . . . .
Junction Temperature . . . . . . . . . . . . . . . .	. . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . .	. –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . .	. . . . . . . . .+300°C

PIN CONNECTIONS

16-Lead Cerdip

16-Lead Plastic DIP

16-Lead SO

	VOUT2						VDD
		1				16
	VOUT1						VOUT3
		2				15
	VIN1						VOUT4
		3	SMP04			14
	NC						VSS
		4				13
			TOP VIEW
	VIN2						VIN4
		5	(Not to Scale)			12
	S/H1						VIN3
		6				11
	S/H2
		7				10	S/H4
	DGND
		8				9	S/H3

NC = NO CONNECT

Package Type	uJA*	uJC	Units
16-Lead Cerdip	94	12	°C/W
16-Lead Plastic DIP	76	33	°C/W
16-Lead SO	92	27	°C/W

*uJA is specified for worst case mounting conditions, i.e., uJA is specified for device in socket for cerdip and plastic DIP packages; uJA is specified for device soldered to printed circuit board for SO package.

CAUTION

1.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; function operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability.

2.Digital inputs and outputs are protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures.

3.Remove power before inserting or removing units from their sockets.

ORDERING GUIDE

	Temperature	Package	Package
Model	Range	Description	Options*
SMP04EQ	–40°C to +85°C	Cerdip-16	Q-16
SMP04EP	–40°C to +85°C	PDIP-16	N-16
SMP04ES	–40°C to +85°C	SO-16	R-16A

*Q = Cerdip; N = Plastic DIP; R = Small Outline.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP04 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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SMP04

VOUT1

VOUT2 VDD VOUT3

VOUT4

VIN1

VSS

VIN4

VIN2

VIN3

S/H1

S/H2 DGND

S/H3 S/H4

Dice Characteristics

Die Size: 0.80 x 0.120 mil = 9,600 sq. mil (2.032 x 3.048mm = 6.193 sq. mm)

WAFER TEST LIMITS (@ VDD = +12 V, VSS = DGND = 0 V, RL = No Load, TA = +258C, unless otherwise noted.)

			SMP04G
Parameter	Symbol	Conditions	Limits	Units
Buffer Offset Voltage	VOS	VIN = +6 V	± 10	mV max
Hold Step	VHS	VIN = +6 V	± 4	mV max
Droop Rate	V/ t	VIN = +6 V	25	mV/s max
Output Source Current	ISOURCE	VIN = +6 V	1.2	mA min
Output Sink Current	ISINK	VIN = +6 V	0.5	mA min
Output Voltage Range	OVR	RL = 20 kΩ	0.06/10.0	V min/max
		RL = 10 kΩ	0.06/9.5	V min/max
LOGIC CHARACTERISTICS
Logic Input High Voltage	VINH		2.4	V min
Logic Input Low Voltage	VINL		0.8	V max
Logic Input Current	IIN		1	µA max
SUPPLY CHARACTERISTICS		10.8 V ≤ VDD ≤ 13.2 V
Power Supply Rejection Ratio	PSRR		60	dB min
Supply Current	IDD		7	mA max
Power Dissipation	PDIS		84	mW max

NOTE

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

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Typical Performance Characteristics–SMP04

	10000	VDD = +12V
		VSS = 0V
– mV/s	1000	VIN = +5V
		RL = 10kV
DROOP RATE	100
	10
	0
	–55 –35–15		5	25	45	65	85	105	125
		TEMPERATURE –8C

Figure 1. Droop Rate vs. Temperature

	3
								TA = +258C
	2							VDD = +12V
								VSS = 0V
mV	1
–
HOLD STEP	0
	–1
	–2
	–3
	0	1	2	3	4	5	6	7	8	9	10

INPUT VOLTAGE – Volts

Figure 4. Hold Step vs. Input Voltage

	2								VDD = +12V
	1								VSS = 0V
– mV
	0				RL =
VOLTAGE
	–1							RL = 20kV
OFFSET	–2
							RL = 10kV
	–3
	–4
	0	1	2	3	4	5	6	7	8	9	10

INPUT VOLTAGE – Volts

Figure 7. Offset Voltage vs. Input Voltage (TA = +25°C)

	5
								VDD = +12V
								VSS = 0V
– mV/s	3
	1
RATE
	0
DROOP	–1
	–3
	–5
	0	1	2	3	4	5	6	7	8	9	10
				INPUT VOLTAGE – Volts

Figure 2. Droop Rate vs. Input Voltage (TA = +25°C)

	3				VDD = +12V
	2				VSS = 0V
					VIN = +5V
mV	1
–
HOLD STEP	0
	–1
	–2
	–3
	–55 –35–15	5	25	45	65	85	105	125
	TEMPERATURE –8C

Figure 5. Hold Step vs. Temperature

	20
								VDD = +12V
	15							VSS = 0V
mV	10
–
VOLTAGE	5				RL =				RL = 20kV
	0
OFFSET	–5
	–10
	–15						RL = 10kV
	–20
	0	1	2	3	4	5	6	7	8	9	10
				INPUT VOLTAGE – Volts

Figure 8. Offset Voltage vs. Input Voltage (TA = +125°C)

	1800								VDD = +12V
	1600								VSS = 0V
mV/s	1400
–
RATE	1200
DROOP	1000
	800
	600
	0	1	2	3	4	5	6	7	8	9	10
				INPUT VOLTAGE – Volts

Figure 3. Droop Rate vs. Input Voltage (TA = +125°C)

	7
		TA = +258C
		VSS = 0V
V/ms	6
–			–SR
RATE	5
SLEW				+SR
	4
	3
	10	11	12	13	14	15	16	17	18
				VDD – Volts

Figure 6. Slew Rate vs. VDD

	4
								VDD = +12V
	2				RL =			VSS = 0V
mV
	0
–							RL = 20kV
VOLTAGE
	–2
	–4
OFFSET
	–6				RL = 10kV
	–8
	–10
	0	1	2	3	4	5	6	7	8	9	10
				INPUT VOLTAGE – Volts

Figure 9. Offset Voltage vs. Input Voltage (TA = –55°C)

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