October 1986
Revised March 2000
DM74AS280
9-Bit Parity Generator/Checker
General Description
These universal, 9-bit parity generators/checkers utilize advanced Schottky high performance circuitry and feature odd/even outputs to facilitate operation of either odd or even parity applications. The word length capability is easily expanded by cascading.
The DM74AS280 can be used to upgrade the performance of most systems utilizing the ’180 parity generator/checker. Although the DM74AS280 is implemented without expander inputs, the corresponding function is provided by the availability of an input at pin 4 and no internal connection at pin 3. This permits the DM74AS280 to be substituted for the ’180 in existing designs to produce identical function even if DM74AS280s are mixed with existing ’180s.
Features
■Generates either odd or even parity for nine data lines
■Inputs are buffered to lower the drive requirements
■Can be used to upgrade existing systems using MSI parity circuits
■Cascadable for N-bits
■Advanced oxide-isolated, ion-implanted Schottky TTL process
■Switching specifications at 50 pF
■Switching specifications guaranteed over full temperature and VCC range
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74AS280M |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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DM74AS280N |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Function Table |
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Number of Inputs (A thru I) |
Outputs |
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that are HIGH |
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åEven |
åOdd |
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0, 2, 4, 6, 8 |
H |
L |
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1, 3, 5, 7, 9 |
L |
H |
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L = LOW State |
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H = HIGH State |
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Generator/Checker Parity Bit-9 DM74AS280
© 2000 Fairchild Semiconductor Corporation |
DS006303 |
www.fairchildsemi.com |
DM74AS280
Logic Diagram
www.fairchildsemi.com |
2 |
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