October 1986
Revised March 2000
DM74AS874
Dual 4-Bit D-Type Edge-Triggered Flip-Flop
General Description
These dual 4-bit inverting registers feature totem-pole 3- STATE outputs designed specifically for driving highlycapacitive or relatively low-impedance loads. The highimpedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the DM74AS874 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.
A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-imped- ance state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.
The pinout is arranged to ease printed circuit board layout. All data inputs are on one side of the package, while all outputs are on the other side.
Features
■Switching specifications at 50 pF
■Switching specifications guaranteed over full temperature and VCC range
■Advanced oxide-isolated, ion-implanted Schottky TTL process
■3-STATE buffer-type outputs drive bus lines directly
■Space saving 300 mil wide package
■Bus structured pinout
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74AS874WM |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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DM74AS874NT |
N24C |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Flop-Flip Triggered-Edge Type-D Bit-4 Dual DM74AS874
© 2000 Fairchild Semiconductor Corporation |
DS006331 |
www.fairchildsemi.com |
DM74AS874
Function Table |
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Logic Diagram |
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Inputs |
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Output |
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CLR |
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D |
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CLK |
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OC |
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Q |
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X |
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X |
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X |
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H |
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Z |
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L |
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X |
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X |
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L |
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L |
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H |
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H |
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− |
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L |
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H |
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H |
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L |
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− |
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L |
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L |
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H |
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X |
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L |
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L |
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Q0 |
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L = LOW State |
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H = HIGH State |
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X = Don’t Care |
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− = Positive Edge Transition
Z = High Impedance State
Q0 = Previous Condition of Q
www.fairchildsemi.com |
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