Texas Instruments PCI1420GHK, PCI1420PDV Datasheet

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PCI1420

PC Card Controllers

Data Manual

Literature Number: SCPS047

April 1999

Printed on Recycled Paper

IMPORTANT NOTICE

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Contents

Section	Title	Page
1 Introduction . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	1±1

1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1±1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1±1 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1±2 1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1±2

2 Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±1 3 Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±1

3.1 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±1 3.2 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±2 3.3 Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±2 3.4 Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . 3±2 3.4.1 PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±2 3.4.2 Loading Subsystem Identification . . . . . . . . . . . . . . . . . . . . . 3±3

3.5 PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±3 3.5.1 PC Card Insertion/Removal and Recognition . . . . . . . . . . . 3±3 3.5.2 P2C Power-Switch Interface (TPS2206/2216) . . . . . . . . . . 3±4 3.5.3 Zoomed Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±5 3.5.4 Ultra Zoomed Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±6 3.5.5 Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±7 3.5.6 Integrated Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 3±7 3.5.7 SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . . 3±7 3.5.8 LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3±8 3.5.9 PC Card-16 Distributed DMA Support . . . . . . . . . . . . . . . . . 3±8 3.5.10 PC Card-16 PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±10 3.5.11 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±10

3.6 Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±11 3.6.1 Serial Bus Interface Implementation . . . . . . . . . . . . . . . . . . . 3±11 3.6.2 Serial Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 3±11 3.6.3 Serial Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . 3±13 3.6.4 Serial Bus Power Switch Application . . . . . . . . . . . . . . . . . . 3±14 3.6.5 Accessing Serial Bus Devices Through Software . . . . . . . . 3±15

3.7 Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±15

3.7.1PC Card Functional and Card Status Change Interrupts . 3±15

3.7.2 Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±17 3.7.3 Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3±18 3.7.4 Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3±18

iii

3.7.5 Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . . 3±19 3.7.6 SMI Support in the PCI1420 . . . . . . . . . . . . . . . . . . . . . . . . . . 3±19 3.8 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±19 3.8.1 Clock Run Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±20 3.8.2 CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3±20 3.8.3 16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . . 3±20 3.8.4 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±20 3.8.5 Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . . 3±21 3.8.6 Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±22 3.8.7 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±22 3.8.8 CardBus Device Class Power Management . . . . . . . . . . . . 3±23 3.8.9 ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±24

3.8.10Master List of PME Context Bits and

Global Reset Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±24

4 PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±1

4.1 PCI Configuration Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . 4±1 4.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±2 4.3 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±2 4.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±3 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±4 4.6 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±5 4.7 PCI Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±5 4.8 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±5 4.9 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±6 4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±6 4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±6 4.12 CardBus Socket Registers/ExCA Base-Address Register . . . . . . . . . 4±7 4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±7 4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±8 4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±9 4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±9 4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±9 4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±10 4.19 Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±10 4.20 Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±11 4.21 I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±11 4.22 I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±12 4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±12 4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±13 4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±14 4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±15 4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±15 4.28 PC Card 16-bit I/F Legacy-Mode Base Address Register . . . . . . . . . 4±15 4.29 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±16

4.30	Multifunction Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±19
4.31	Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±21
4.32	Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±22
4.33	Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±23
4.34	Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±24
4.35	Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±25
4.36	Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±26
4.37	Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±27
4.38	Next-Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±27
4.39	Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . .	4±28
4.40	Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . .	4±29
4.41	Power Management Control/Status Register Bridge
	Support Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±30
4.42	Power Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±30
4.43	General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . .	4±31
4.44	General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . .	4±32
4.45	General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±33
4.46	General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±34
4.47	Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±34
4.48	Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±35
4.49	Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±35
4.50	Serial Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . .	4±36
5 ExCA Compatibility Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . .		5±1
5.1	ExCA Identification and Revision Register (Index 00h) . . . . . . . . . . .	5±5
5.2	ExCA Interface Status Register (Index 01h) . . . . . . . . . . . . . . . . . . . . .	5±6
5.3	ExCA Power Control Register (Index 02h) . . . . . . . . . . . . . . . . . . . . . .	5±7
5.4	ExCA Interrupt and General-Control Register (Index 03h) . . . . . . . . .	5±8
5.5	ExCA Card Status-Change Register (Index 04h) . . . . . . . . . . . . . . . . .	5±9
5.6	ExCA Card Status-Change-Interrupt Configuration
	Register (Index 05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±10
5.7	ExCA Address Window Enable Register (Index 06h) . . . . . . . . . . . . .	5±11
5.8	ExCA I/O Window Control Register (Index 07h) . . . . . . . . . . . . . . . . .	5±12
5.9	ExCA I/O Windows 0 and 1 Start-Address Low-Byte
	Registers (Index 08h, 0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±13
5.10	ExCA I/O Windows 0 and 1 Start-Address High-Byte
	Registers (Index 09h, 0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±13
5.11	ExCA I/O Windows 0 and 1 End-Address Low-Byte
	Registers (Index 0Ah, 0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±14
5.12	ExCA I/O Windows 0 and 1 End-Address High-Byte
	Registers (Index 0Bh, 0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±14
5.13	ExCA Memory Windows 0±4 Start-Address Low-Byte
	Registers (Index 10h, 18h, 20h, 28h, 30h) . . . . . . . . . . . . . . . . . . . . . .	5±15
5.14	ExCA Memory Windows 0±4 Start-Address High-Byte
	Registers (Index 11h, 19h, 21h, 29h, 31h) . . . . . . . . . . . . . . . . . . . . . .	5±16
5.15	ExCA Memory Windows 0±4 End-Address Low-Byte
	Registers (Index 12h, 1Ah, 22h, 2Ah, 32h) . . . . . . . . . . . . . . . . . . . . . .	5±17

5.16ExCA Memory Windows 0±4 End-Address High-Byte

Registers (Index 13h, 1Bh, 23h, 2Bh, 33h) . . . . . . . . . . . . . . . . . . . . . 5±18

5.17ExCA Memory Windows 0±4 Offset-Address Low-Byte

Registers (Index 14h, 1Ch, 24h, 2Ch, 34h) . . . . . . . . . . . . . . . . . . . . . 5±19

5.18ExCA Memory Windows 0±4 Offset-Address High-Byte

Registers (Index 15h, 1Dh, 25h, 2Dh, 35h) . . . . . . . . . . . . . . . . . . . . . 5±20

5.19ExCA I/O Windows 0 and 1 Offset-Address Low-Byte

Registers (Index 36h, 38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±21

5.20ExCA I/O Windows 0 and 1 Offset-Address High-Byte

Registers (Index 37h, 39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±21 5.21 ExCA Card Detect and General Control Register (Index 16h) . . . . . . 5±22 5.22 ExCA Global Control Register (Index 1Eh) . . . . . . . . . . . . . . . . . . . . . . 5±23 5.23 ExCA Memory Windows 0±4 Page Register . . . . . . . . . . . . . . . . . . . . 5±24

6 CardBus Socket Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . . . . . 6±1

6.1 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±2 6.2 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±3 6.3 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±4 6.4 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±6 6.5 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±7 6.6 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±8

7 Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±1

7.1 DMA Current Address/Base Address Register . . . . . . . . . . . . . . . . . . . 7±1 7.2 DMA Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±2 7.3 DMA Current Count/Base Count Register . . . . . . . . . . . . . . . . . . . . . . . 7±2 7.4 DMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±3 7.5 DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±3 7.6 DMA Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±4 7.7 DMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±4 7.8 DMA Master Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±5 7.9 DMA Multichannel/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±5

8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8±1

8.1Absolute Maximum Ratings Over Operating

Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8±1

8.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 8±2

8.3Electrical Characteristics Over Recommended

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8±3

8.4PCI Clock/Reset Timing Requirements Over Recommended

Ranges Of Supply Voltage And Operating Free-air Temperature . . . 8±3

8.5PCI Timing Requirements Over Recommended Ranges

of Supply Voltage and Operating Free-air Temperature . . . . . . . . . . . 8±4

9 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9±1

List of Illustrations

Figure			Title	Page
2±1 PCI-to-CardBus Pin Diagram . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2±1
2±2 PCI-to-PC Card (16-Bit) Diagram . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2±2
3±1 PCI1420 Simplified Block Diagram .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±1
3±2 3-State Bidirectional Buffer . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±2
3±3 TPS2206 Terminal Assignments . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±4
3±4 TPS2206 Typical Application . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±5
3±5 Zoomed Video Implementation Using PCI1420 . . . . . . . . . . . . . . . . . . . . . . .				3±5
3±6 Zoomed Video Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				3±6
3±7 Sample Application of SPKROUT and CAUDPWM . . . . . . . . . . . . . . . . . . . .				3±8
3±8 Two Sample LED Circuits . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±8
3±9 Serial EEPROM Application . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±11
3±10 Serial Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . .				3±12
3±11 Serial Bus Protocol Acknowledge .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±12
3±12 Serial Bus Protocol ± Byte Write . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±13
3±13 Serial Bus Protocol ± Byte Read . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±13
3±14 EEPROM Interface Doubleword Data Collection . . . . . . . . . . . . . . . . . . . . .				3±13
3±15 EEPROM Data Format . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±14
3±16 Send Byte Protocol . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±15
3±17 IRQ Implementation . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±18
3±18 Suspend Functional Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				3±21
3±19 Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				3±21
3±20		Functional Diagram		3±22
	RI_OUT		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3±21 Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				3±24
5±1 ExCA Register Access Through I/O			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±1
5±2 ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				5±2
6±1 Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . . .				6±1

vii

List of Tables

Table

Title

Page

2±1 CardBus PC Card Signal Names by GHK/PDV Pin Number . . . . . . . . . . . . 2±3 2±2 CardBus PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . 2±4 2±3 16-Bit PC Card Signal Names by GHK/PDV Pin Number . . . . . . . . . . . . . . . 2±5 2±4 16-Bit PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . . . 2±7 2±5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±8 2±6 PC Card Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±8 2±7 PCI System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±9 2±8 PCI Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±10 2±9 PCI Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±11 2±10 Multifunction and Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±12 2±11 16-Bit PC Card Address and Data (Slots A and B) . . . . . . . . . . . . . . . . . . . . 2±13 2±12 16-Bit PC Card Interface Control (Slots A and B) . . . . . . . . . . . . . . . . . . . . . 2±14 2±13 CardBus PC Card Interface System (Slots A and B) . . . . . . . . . . . . . . . . . . 2±16 2±14 CardBus PC Card Address and Data (Slots A and B) . . . . . . . . . . . . . . . . . 2±17 2±15 CardBus PC Card Interface Control (Slots A and B) . . . . . . . . . . . . . . . . . . 2±18 3±1 PC Card Card-Detect and Voltage-Sense Connections . . . . . . . . . . . . . . . . 3±4 3±2 PC Card Card-Detect and Voltage-Sense Connections . . . . . . . . . . . . . . . . 3±6 3±3 Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±9 3±4 PC/PCI Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±10 3±5 I/O Addresses Used for PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±10 3±6 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±11 3±7 Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . . . . . . . 3±13 3±8 PCI1420 Registers Used to Program Serial Bus Devices . . . . . . . . . . . . . . . 3±15 3±9 Interrupt Mask and Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±16 3±10 PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±17 3±11 Interrupt Pin Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±19 3±12 SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±19 3±13 Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±23 4±1 PCI Configuration Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . . . . . 4±1 4±2 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±3 4±3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±4 4±4 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±8 4±5 Interrupt Pin Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±13 4±6 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±14 4±7 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±17 4±8 Multifunction Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±19 4±9 Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±21

viii

4±10 Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±22
4±11 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±23
4±12 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±24
4±13 Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±25
4±14 Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±26
4±15 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±28
4±16 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . .	4±29
4±17 Power Management Control/Status Register Bridge
Support Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±30
4±18 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±31
4±19 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±32
4±20 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±33
4±21 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±34
4±22 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±34
4±23 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±35
4±24 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±35
4±25 Serial Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±36
5±1 ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±3
5±2 ExCA Identification and Revision Register (Index 00h) . . . . . . . . . . . . . . . . .	5±5
5±3 ExCA Interface Status Register (Index 01h) . . . . . . . . . . . . . . . . . . . . . . . . . .	5±6
5±4 ExCA Power Control Register 82365SL Support (Index 02h) . . . . . . . . . . .	5±7
5±5 ExCA Power Control Register 82365SL-DF Support (Index 02h) . . . . . . . .	5±7
5±6 ExCA Interrupt and General-Control Register (Index 03h) . . . . . . . . . . . . . .	5±8
5±7 ExCA Card Status-Change Register (Index 04h) . . . . . . . . . . . . . . . . . . . . . .	5±9
5±8 ExCA Card Status-Change-Interrupt Configuration Register
(Index 05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±10
5±9 ExCA Address Window Enable Register (Index 06h) . . . . . . . . . . . . . . . . . .	5±11
5±10 ExCA I/O Window Control Register (Index 07h) . . . . . . . . . . . . . . . . . . . . . .	5±12
5±11 ExCA Memory Windows 0±4 Start-Address High-Byte Registers
(Index 11h, 19h, 21h, 29h, 31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±16
5±12 ExCA Memory Windows 0±4 End-Address High-Byte Registers
(Index 13h, 1Bh, 23h, 2Bh, 33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±18
5±13 ExCA Memory Windows 0±4 Offset-Address High-Byte Registers
(Index 15h, 1Dh, 25h, 2Dh, 35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±20
5±14 ExCA Card Detect and General Control Register (Index 16h) . . . . . . . . . .	5±22
5±15 ExCA Global Control Register (Index 1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . .	5±23
6±1 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±1
6±2 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±2
6±3 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±3
6±4 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±4
6±5 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±6
6±6 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±7
6±7 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±8

7±1 Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±1 7±2 DMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±3 7±3 DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±3 7±4 DMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±4 7±5 DMA Multichannel/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±5

1 Introduction

1.1 Description

The TI PCI1420, the industry's first 208-pin controller to meet the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges, is a high-performance PCI-to-CardBus controller that supports two independent card sockets compliant with the 1997 PC Card Standard. The PCI1420 provides features that make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1420 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.

The PCI1420 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bridging transactions. The PCI1420 is also compliant with the latest PCI Bus Power Management Interface Specification.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1420 is register compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The PCI1420 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1420 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1420, such as socket activity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.

1.2 Features

The PCI1420 supports the following features:

•Fully compatible with the Intel 430TX (Mobile Triton II) chipset

•A 208-Pin Low-Profile QFP (PDV) or MicroStar Ball Grid Array (GHK) package

•3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

•Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards

•Two PC Card or CardBus slots with hot insertion and removal

•Uses serial interface to TI TPS2206/2216 dual-slot PC Card power switch

•Burst transfers to maximize data throughput with CardBus Cards

•Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI interrupts, and serial ISA IRQ and PCI interrupts

•Serial EEPROM interface for loading subsystem ID and subsystem vendor ID

•Pipelined architecture allows greater than 130M bps throughput from CardBus-to-PCI and from PCI-to-CardBus

1±1

•Up to five general-purpose I/Os

•Programmable output select for CLKRUN

•Multifunction PCI device with separate configuration space for each socket

•Five PCI memory windows and two I/O windows available for each R2 socket

•Two I/O windows and two memory windows available to each CardBus socket

•Exchangeable Card Architecture (ExCA) compatible registers are mapped in memory and I/O space

•Intel 82365SL-DF and 82365SL register compatible

•Distributed DMA (DDMA) and PC/PCI DMA

•16-Bit DMA on both PC Card sockets

•Ring indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN

•Socket activity LED pins

•PCI Bus Lock (LOCK)

•Advanced Submicron, Low-Power CMOS Technology

•Internal Ring Oscillator

1.3Related Documents

•Advanced Configuration and Power Interface (ACPI) Specification (Revision 1.0)

•PCI Bus Power Management Interface Specification (Revision 1.1)

•PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (Revision 0.6)

•PCI to PCMCIA CardBus Bridge Register Description (Yenta) (Revision 2.1)

•PCI Local Bus Specification (Revision 2.2)

•PCI Mobile Design Guide (Revision 1.0)

•PCI14xx Implemenation Guide for D3 Wake-Up

•1997 PC Card Standard

•PC 99

•Serialized IRQ Support for PCI Systems (Revision 6)

1.4Ordering Information

ORDERING NUMBER	NAME	VOLTAGE	PACKAGE

PCI1420	PC Card Controller	3.3 V, 5-V Tolerant I/Os	208-pin LQFP
			209-ball PBGA

1±2

2 Terminal Descriptions

PDV LOW-PROFILE QUAD FLAT PACKAGE

TOP VIEW

						SUSPEND	MFUNC1	MFUNC0	GND	DATA	CLOCK	LATCH	SPKROUT	V	CAD31A	RSVDA	CAD30A	CAD29A	V	CAD28A	CAD27A	CCD2A		CCLKRUNA	CSTSCHGA	CAUDIOA	CSERRA	CINTA	CVS1A	CAD26A	CAD25A	CAD24A		CC/BE3A	GND	CAD23A	CREQA	CAD22A CAD21A		CRSTA	CAD20A	CVS2A	CAD19A	V	CAD18A	CAD17A		CC/BE2A		CFRAMEA	CIRDYA	CTRDYA	V	CCLKA		CDEVSELA	CGNTA	CSTOPA	CPERRA		CBLOCKA	CPARA


														CCI					CC																									CCA									CC
														CCI					CC																									CCA									CC		111
																																													119	118	117		116		115	114	113	112			110


	MFUNC2			156			155	154	153	152	151	150	149	148	147	146	145	144	143	142	141	140	139		138	137	136	135	134	133	132	131	130		129	128	127	126	125	124	123	122	121	120														109	108	107		106
	MFUNC2			157
	MFUNC3			158
	MFUNC4			159
	MFUNC5				160


	MFUNC6			161																																	Card A
				162
		C/BE3		162
				163
RI_OUT/PME				163
			VCC	164
			AD25	165
			PRST	166
			PRST	166
			GND	167
			GNT	168
			REQ	169
			AD31	170
			AD30	171
			AD11	172
			AD29		173


			AD28	174
			GRST	175
			AD27	176
			AD26	177
		V CCP		178
			AD24	179								PCI																		PCI1420 Core
			PCLK	180								PCI																		PCI1420 Core
			GND	181
		IDSEL		182
			AD23	183
			AD22	184
			AD21	185
			AD20		186


			VCC	187
			AD19	188
			AD18	189
			AD17	190
			AD16		191


				192
		C/BE2		192
		FRAME		193
			GND	194
			IRDY	195
			TRDY	196
				197
	DEVSEL			197
				198
			STOP	198
			PERR	199
			SERR	200
			VCC	201
			PAR	202
		C/BE1		203																																						Card B
			AD15	204																																						Card B
			AD14	205
			AD13	206
			GND	207
			AD12	208
				1			2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18		19	20	21	22	23	24	25	26	27		28	29	30	31	32	33	34	35	36	37	38	39	40		41		42	43	44	45	46		47	48	49	50		51
															AD4			GND										GND											CAD11B											CPARB			GND	CSTOPB

					V		AD10	AD9	AD8	C/BE0	AD7 V		AD6	AD5		AD3	AD2		AD1	AD0	CCD1B	CAD0B		CAD2B	CAD1B	CAD4B	CAD3B		CAD6B	CAD5B	RSVDB	CAD7B		CAD8B	CC/BE0B	CAD9B	CAD10B	V		CAD13B	CAD12B	CAD15B	CAD14B	CAD16B	V	CC/BE1B		RSVDB			CBLOCKB	CPERRB				CGNTB	CDEVSELB	CCLKB	CTRDYB		CIRDYB	CFRAMEB
						CCP						CC																										CC							CCB
						CCP																																							CCB

	A RSVD
105
104		A_CC/BE1
103		A_CAD16
102		A_CAD14
101		A_CAD15
100		A_CAD12
99		A_CAD13
98		A_CAD11
97		A_CAD10
96		GND
95		A_CAD9
94
		A_CC/BE0
93		A_CAD8
92		A_CAD7
91		A_RSVD
90		A_CAD5
89		A_CAD6
88		A_CAD3
87		A_CAD4
86		VCC
85		A_CAD1
84		A_CAD2
83		A_CAD0
82		A_CCD1
81		B_CAD31
80		B_RSVD
79		B_CAD30
78		B_CAD29
77		B_CAD28
76		B_CAD27
75		GND
74		B_	CCD2
73		B_	CCLKRUN
72		B_CSTSCHG
71		B_CAUDIO
70		B_	CSERR
69		B_	CINT
68		B_CVS1
67		B_CAD26
66		B_CAD25
65		B_CAD24
64		VCC
63		B_CC/BE3
62		B_CAD23
61		B_	CREQ
60		B_CAD22
59		B_CAD21
58		B_CRST
57		B_CAD20
56		B_CVS2
55		B_CAD19
54		B_CAD18
53		B_CAD17
52
	B CC/BE2

Figure 2±1. PCI-to-CardBus Pin Diagram

2±1

									SUSPEND
MFUNC2							156
							157
MFUNC3							158
MFUNC4							159
MFUNC5								160


MFUNC6							161
							162
		C/BE3
							163
RI_OUT/PME
					VCC		164
				AD25			165
				PRST			166
					GND		167
						GNT	168
						REQ	169
				AD31			170
				AD30			171
				AD11			172
				AD29			173
				AD28			174
			GRST				175
				AD27			176
				AD26			177
		VCCP					178
				AD24			179
				PCLK			180
					GND		181
		IDSEL					182
				AD23			183
				AD22			184
				AD21			185
				AD20			186
					VCC		187
				AD19			188
				AD18			189
				AD17			190
				AD16			191
		C/BE2					192
		FRAME					193
					GND		194
					IRDY		195
			TRDY				196
	DEVSEL						197
				STOP			198
			PERR				199
			SERR				200
					VCC		201
						PAR	202
		C/BE1					203
				AD15			204
				AD14			205
				AD13			206
					GND		207
				AD12			208
							1
									CCP
								V

MFUNC1	MFUNC0	GND	DATA	CLOCK	LATCH


155	154	153	152	151	150

PCI

2 3	4 5	6 7
AD10 AD9	AD8 C/BE0	AD7 V
		CC

PDV LOW-PROFILE QUAD FLAT PACKAGE

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														BVD1(STSCHG/RI)A		BVD2(SPKR)A				READY(IREQ)A

SPKROUT	V	D10A	D2A	D9A	D1A	V	D8A	D0A		CD2A		WP(IOIS16)A						WAITA				VS1A	A0A	A1A	A2A		REGA	GND	A3A		INPACKA	A4A	A5A	RESETA	A6A		VS2A	A25A	V	A7A	A24A	A12A	A23A








	CCI					CC																																	CCA	119	118	117	116
149	148	147	146	145	144	143	142	141	140		139		138		137		136		135		134		133	132	131	130		129	128	127		126	125	124	123	122		121	120	119	118	117	116

Card A

PCI1420 Core


																										Card B
8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32	33	34	35	36	37	38	39	40	41
AD6	AD5	AD4	AD3	AD2	GND	AD1	AD0	CD1B	D3B	D11B	D4B	D12B	D5B	GND	D13B	D6B	D14B	D7B	D15B	CE1B	A10B	CE2B V		OEB	IORDB	A11B	IOWRB A9B		A17B	V	A8B	A18B	A13B
																							CC							CCB
																							CC							CCB


A15	A22	CC A16		A21		WE A20		A14

A A V A				A A A A
115	114	113	112	111	110

							109	108

42	43	44	45	46		47	48	49
B A19	B A14	GND	B A20		B WE	B A21	B A16	B A22

A A19	A A13
107	106

50	51
B A15	B A23

A A18
105	A_A8
104	A_A8
103	A_A17
102	A_A9
101	A_	IOWR
100	A_A11
99	A_	IORD
98	A_OE
97	A_	CE2
96	GND
95	A_A10
94	A_	CE1
93	A_D15
92	A_D7
91	A_D14
90	A_D6
89	A_D13
88	A_D5
87	A_D12
86	VCC
85	A_D4
84	A_D11
83	A_D3
82	A_	CD1
81	B_D10
80	B_D2
79	B_D9
78	B_D1
77	B_D8
76	B_D0
75	GND
74	B_	CD2
73	B_WP(IOIS16)
72	B_BVD1(		STSCHG/RI)
71	B_BVD2(SPKR)
70	B_	WAIT
69	B_READY(IREQ)
68	B_	VS1
67	B_A0
66	B_A1
65	B_A2
64	VCC
63	B_	REG
62	B_A3
61
61	B_INPACK
60	B_A4
59	B_A5
58	B_RESET
57	B_A6
56	B_	VS2
55	B_A25
54	B_A7
53	B_A24
52
B A12

Figure 2±2. PCI-to-PC Card (16-Bit) Diagram

2±2

Table 2±1 and Table 2±2 show the terminal assignments for the CardBus PC Card; Table 2±3 and Table 2±4 show the terminal assignments for the 16-bit PC Card. Table 2±1 and Table 2±3 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the associated GHK package terminal number. Table 2±2 and Table 2±4 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the signal name and its associated terminal numbers. Pin E5 is a no connection identification ball.

Table 2±1. CardBus PC Card Signal Names by GHK/PDV Pin Number

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

GHK

PDV

GHK

PDV

GHK

PDV

GHK

PDV

208

AD12

AD10

G19

143

VCC

L18

124

CRST

203

206

AD13

B_CAD2

L19

123

A_CAD20

C/BE1

199

201

VCC

B_CAD0

B_CAD12

PERR

195

194

GND

B_CAD15

IRDY

CCD1

190

AD17

189

AD18

AD0

B_CAD14

185

AD21

E10

183

AD23

AD3

VCCB

A10

180

PCLK

E11

178

VCCP

H14

141

A_CAD27

B_CAD16

A11

175

GRST

E12

171

AD30

H15

142

A_CAD28

M14

115

CIRDY

A12

174

AD28

E13

165

AD25

H17

140

CCD2

M15

119

A_CAD18

A13

170

AD31

E14

159

MFUNC4

H18

139

CCLKRUN

M17

120

VCCA

A14

166

E17

155

MFUNC1

H19

138

A_CSTSCHG

M18

121

A_CAD19

PRST

A15

162

E18

153

GND

B_CAD1

M19

122

A_CVS2

C/BE3

A16

157

MFUNC2

E19

151

CLOCK

B_CAD4

B_CC/BE1

205

AD14

AD4

B_CAD3

B_RSVD

200

AD6

GND

B_CPAR

SERR

196

TRDY

VCC

B_CAD6

CSTOP

191

AD16

AD9

J14

136

CSERR

CBLOCK

186

AD20

204

AD15

J15

137

A_CAUDIO

N14

108

CPERR

B10

181

GND

198

STOP

J17

135

CINT

N15

113

VCC

B11

176

AD27

193

FRAME

J18

134

A_CVS1

N17

116

CFRAME

B12

173

AD29

188

AD19

J19

133

A_CAD26

N18

117

A_CC/BE2

B13

169

F10

184

AD22

B_CAD5

N19

118

A_CAD17

REQ

B14

164

VCC

F11

179

AD24

B_RSVD

CPERR

B15

161

F12

167

GND

B_CAD7

GND

MFUNC6/CLKRUN

207

GND

F13

160

MFUNC5

B_CAD8

CGNT

202

PAR

F14

152

DATA

B_CC/BE0

CIRDY

197

F15

154

MFUNC0

K14

132

A_CAD25

B_CCLK

DEVSEL

192

F17

150

LATCH

K15

131

A_CAD24

B_CVS2

C/BE2

187

VCC

F18

148

VCCI

K17

130

A_CC/BE3

B_CC/BE3

C10

182

IDSEL

F19

147

A_CAD31

K18

129

GND

C11

177

AD26

AD1

K19

128

A_CAD23

P10

B_RSVD

C12

172

AD11

GND

B_CAD9

P11

A_CAD2

C13

168

AD2

B_CAD10

P12

A_CAD6

GNT

C14

163

AD5

VCC

P13

RI_OUT/PME

A_CC/BE0

C15

158

MFUNC3

AD8

B_CAD13

P14

100

A_CAD12

VCCP

G14

146

A_RSVD

B_CAD11

P15

107

CBLOCK

D19

156

SUSPEND

G15

149

SPKROUT

L14

127

CREQ

P17

111

CDEVSEL

AD7

G17

145

A_CAD30

L15

126

A_CAD22

P18

112

A_CCLK

C/BE0

G18

144

A_CAD29

L17

125

A_CAD21

P19

114

CTRDY

2±3

Table 2±1. CardBus PC Card Signal Names by GHK/PDV Pin Number (Continued)

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

GHK

PDV

GHK

PDV

GHK

PDV

GHK

PDV

R18

109

U14

A_CAD11

B_CAD17

CDEVSEL

CSTOP

CTRDY

R19

110

CGNT

U15

103

A_CAD16

CRST

CFRAME

B_CC/BE2

B_CAD20

B_CAD23

B_CAD19

T19

105

A_RSVD

B_CAD22

B_CAD25

CREQ

B_CAD18

B_CAD24

CSERR

B_CAD26

B_CAD21

CINT

B_CAUDIO

CCD2

VCC

B_CSTSCHG

W10

B_CAD27

R10

B_CAD30

B_CVS1

V10

B_CAD28

W11

B_CAD31

R11

A_CAD1

CCLKRUN

V11

CCD1

W12

VCC

R12

A_CAD5

U10

B_CAD29

V12

A_CAD4

W13

A_RSVD

R13

A_CAD10

U11

A_CAD0

V13

A_CAD7

W14

A_CAD9

R14

102

A_CAD14

U12

A_CAD3

V14

GND

W15

A_CAD13

R17

106

A_CPAR

U13

A_CAD8

V15

101

A_CAD15

W16

104

A_CC/BE1

Table 2±2. CardBus PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

GHK

PDV

GHK

PDV

GHK

PDV

GHK

PDV

A_CAD0

U11

A_CAD27

H14

141

CTRDY

P19

114

AD21

185

A_CAD1

R11

A_CAD28

H15

142

A_CVS1

J18

134

AD22

F10

184

A_CAD2

P11

A_CAD29

G18

144

A_CVS2

M19

122

AD23

E10

183

A_CAD3

U12

A_CAD30

G17

145

A_RSVD

G14

146

AD24

F11

179

A_CAD4

V12

A_CAD31

F19

147

A_RSVD

T19

105

AD25

E13

165

A_CAD5

R12

A_CAUDIO

J15

137

A_RSVD

W13

AD26

C11

177

A_CAD6

P12

CBLOCK

P15

107

AD0

AD27

B11

176

A_CAD7

V13

P13

AD1

AD28

A12

174

A_CC/BE0

A_CAD8

U13

W16

104

AD2

AD29

B12

173

A_CC/BE1

A_CAD9

W14

N18

117

AD3

AD30

E12

171

A_CC/BE2

A_CAD10

R13

K17

130

AD4

AD31

A13

170

A_CC/BE3

A_CAD11

U14

CCD1

V11

AD5

B_CAD0

A_CAD12

P14

100

CCD2

H17

140

AD6

B_CAD1

A_CAD13

W15

A_CCLK

P18

112

AD7

B_CAD2

A_CAD14

R14

102

CCLKRUN

H18

139

AD8

B_CAD3

A_CAD15

V15

101

CDEVSEL

P17

111

AD9

B_CAD4

A_CAD16

U15

103

CFRAME

N17

116

AD10

B_CAD5

A_CAD17

N19

118

CGNT

R19

110

AD11

C12

172

B_CAD6

A_CAD18

M15

119

CINT

J17

135

AD12

208

B_CAD7

A_CAD19

M18

121

CIRDY

M14

115

AD13

206

B_CAD8

A_CAD20

L19

123

A_CPAR

R17

106

AD14

205

B_CAD9

A_CAD21

L17

125

CPERR

N14

108

AD15

204

B_CAD10

A_CAD22

L15

126

CREQ

L14

127

AD16

191

B_CAD11

A_CAD23

K19

128

CRST

L18

124

AD17

190

B_CAD12

A_CAD24

K15

131

CSERR

J14

136

AD18

189

B_CAD13

A_CAD25

K14

132

CSTOP

R18

109

AD19

188

B_CAD14

A_CAD26

J19

133

A_CSTSCHG

H19

138

AD20

186

B_CAD15

2±4

Texas Instruments PCI1420GHK, PCI1420PDV Datasheet

Table 2±2. CardBus PC Card Signal Names Sorted Alphabetically (Continued)

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

GHK

PDV

GHK

PDV

GHK

PDV

GHK

PDV

B_CAD16

CCLKRUN

DEVSEL

197

PAR

202

B_CAD17

CDEVSEL

FRAME

193

PCLK

A10

180

B_CAD18

CFRAME

GND

B10

181

PERR

199

B_CAD19

CGNT

GND

207

PRST

A14

166

B_CAD20

CINT

GND

194

REQ

B13

169

B_CAD21

CIRDY

GND

E18

153

RI_OUT/PME

C14

163

B_CAD22

B_CPAR

GND

F12

167

200

SERR

B_CAD23

CPERR

GND

SPKROUT

G15

149

B_CAD24

CREQ

GND

STOP

198

B_CAD25

CRST

GND

K18

129

SUSPEND

D19

156

B_CAD26

CSERR

GND

TRDY

196

B_CAD27

W10

CSTOP

GND

VCC

B14

164

B_CAD28

V10

B_CSTSCHG

GND

V14

VCC

187

B_CAD29

U10

CTRDY

GNT

C13

168

VCC

201

B_CAD30

R10

B_CVS1

A11

175

VCC

GRST

B_CAD31

W11

B_CVS2

IDSEL

C10

182

VCC

G19

143

B_CAUDIO

B_RSVD

IRDY

195

VCC

CBLOCK

B_RSVD

LATCH

F17

150

VCC

N15

113

B_CC/BE0

B_RSVD

P10

MFUNC0

F15

154

VCC

B_CC/BE1

C/BE0

MFUNC1

E17

155

VCC

W12

B_CC/BE2

C/BE1

203

MFUNC2

A16

157

VCCA

M17

120

B_CC/BE3

C/BE2

192

MFUNC3

C15

158

VCCB

A15

162

MFUNC4

E14

159

VCCI

F18

148

CCD1

C/BE3

CCD2

CLOCK

E19

151

MFUNC5

F13

160

VCCP

B_CCLK

DATA

F14

152

MFUNC6/CLKRUN

B15

161

VCCP

E11

178

Table 2±3. 16-Bit PC Card Signal Names by GHK/PDV Pin Number

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

GHK

PDV

GHK

PDV

GHK

PDV

GHK

PDV

208

AD12

196

C11

177

AD26

E11

178

VCCP

TRDY

203

C/BE1

191

AD16

C12

172

AD11

E12

171

AD30

199

PERR

186

AD20

C13

168

GNT

E13

165

AD25

195

IRDY

B10

181

GND

C14

163

RI_OUT/PME

E14

159

MFUNC4

190

AD17

B11

176

AD27

C15

158

MFUNC3

E17

155

MFUNC1

185

AD21

B12

173

AD29

VCCP

E18

153

GND

A10

180

PCLK

B13

169

REQ

D19

156

SUSPEND

E19

151

CLOCK

A11

175

GRST

B14

164

VCC

AD7

AD4

A12

174

AD28

B15

161

MFUNC6

AD6

C/BE0

A13

170

AD31

207

GND

AD10

VCC

A14

166

PRST

202

PAR

206

AD13

AD9

A15

162

C/BE3

197

DEVSEL

201

VCC

204

AD15

A16

157

MFUNC2

192

194

GND

198

C/BE2

STOP

205

AD14

187

VCC

189

AD18

193

FRAME

200

SERR

C10

182

IDSEL

E10

183

AD23

188

AD19

2±5

Table 2±3. 16-Bit PC Card Signal Names by GHK/PDV Pin Number (Continued)

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL

PIN NO.

SIGNAL

PIN NO.

SIGNAL NAME

GHK

PDV

GHK

PDV

NAME

GHK

PDV

NAME

GHK

PDV

F10

184

AD22

J18

134

VS1

N14

108

A_A14

B_A12

F11

179

AD24

J19

133

A_A0

N15

113

VCC

T19

105

A_A18

F12

167

GND

B_D6

N17

116

A_A23

B_A7

F13

160

MFUNC5

B_D14

N18

117

A_A12

B_A5

F14

152

DATA

B_D7

N19

118

A_A24

VCC

F15

154

MFUNC0

B_D15

B_A14

VS1

F17

150

LATCH

CE1

GND

B_WP(IOIS16)

F18

148

VCCI

K14

132

A_A1

U10

B_D1

F19

147

A_D10

K15

131

A_A2

B_A15

U11

A_D3

AD1

K17

130

REG

B_A16

U12

A_D5

GND

K18

129

GND

VS2

U13

A_D15

AD2

K19

128

A_A3

REG

U14

AD5

B_A10

GND

U15

103

A_A17

AD8

CE2

P10

B_D2

B_A6

G14

146

A_D2

VCC

P11

A_D11

B_A4

G15

149

SPKROUT

IORD

P12

A_D13

B_A2

G17

145

A_D9

P13

CE1

B_READY(IREQ)

G18

144

A_D1

L14

127

INPACK

P14

100

A_A11

B_BVD1(STSCHG/R1)

G19

143

VCC

L15

126

A_A4

P15

107

A_A19

V10

B_D8

B_D11

L17

125

A_A5

P17

111

A_A21

V11

CD1

B_D3

L18

124

A_RESET

P18

112

A_A16

V12

A_D12

CD1

L19

123

A_A6

P19

114

A_A22

V13

A_D7

AD0

B_A11

B_A21

V14

GND

AD3

IOWR

B_A22

V15

101

IOWR

H14

141

A_D0

B_A9

B_A23

B_A24

H15

142

A_D8

VCCB

B_A25

B_RESET

H17

140

CD2

B_A17

INPACK

B_A3

H18

139

A_WP(IOIS16)

M14

115

A_A15

B_A0

B_A1

H19

138

A_BVD1(STSCHG/R1)

M15

119

A_A7

CD2

WAIT

B_D4

M17

120

VCCA

R10

B_D9

B_BVD2(SPKR)

B_D12

M18

121

A_A25

R11

A_D4

W10

B_D0

B_D5

M19

122

VS2

R12

A_D6

W11

B_D10

GND

B_A8

R13

CE2

W12

VCC

B_D13

B_A18

R14

102

A_A9

W13

A_D14

J14

136

WAIT

B_A13

R17

106

A_A13

W14

A_A10

J15

137

A_BVD2(SPKR)

B_A20

R18

109

A_A20

W15

IORD

J17

135

A_READY(IREQ)

B_A19

R19

110

W16

104

A_A8

2±6

Table 2±4. 16-Bit PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

GHK

PDV

GHK

PDV

GHK

PDV

GHK

PDV

A_A0

J19

133

A_D11

P11

AD26

C11

177

B_D5

A_A1

K14

132

A_D12

V12

AD27

B11

176

B_D6

A_A2

K15

131

A_D13

P12

AD28

A12

174

B_D7

A_A3

K19

128

A_D14

W13

AD29

B12

173

B_D8

V10

A_A4

L15

126

A_D15

U13

AD30

E12

171

B_D9

R10

A_A5

L17

125

INPACK

L14

127

AD31

A13

170

B_D10

W11

A_A6

L19

123

IORD

W15

B_A0

B_D11

A_A7

M15

119

IOWR

V15

101

B_A1

B_D12

A_A8

W16

104

U14

B_A2

B_D13

A_A9

R14

102

J17

135

B_A3

B_D14

A_READY(IREQ)

A_A10

W14

REG

K17

130

B_A4

B_D15

A_A11

P14

100

A_RESET

L18

124

B_A5

INPACK

A_A12

N18

117

VS1

J18

134

B_A6

IORD

A_A13

R17

106

VS2

M19

122

B_A7

IOWR

A_A14

N14

108

WAIT

J14

136

B_A8

A_A15

M14

115

R19

110

B_A9

B_READY(IREQ)

A_A16

P18

112

A_WP(IOIS16)

H18

139

B_A10

REG

A_A17

U15

103

AD0

B_A11

B_RESET

A_A18

T19

105

AD1

B_A12

VS1

A_A19

P15

107

AD2

B_A13

VS2

A_A20

R18

109

AD3

B_A14

WAIT

A_A21

P17

111

AD4

B_A15

A_A22

P19

114

AD5

B_A16

B_WP(IOIS16)

A_A23

N17

116

AD6

B_A17

C/BE0

A_A24

N19

118

AD7

B_A18

203

C/BE1

A_A25

M18

121

AD8

B_A19

192

C/BE2

H19

138

AD9

B_A20

A15

162

A_BVD1(STSCHG/R1)

C/BE3

J15

137

AD10

B_A21

CLOCK

E19

151

A_BVD2(SPKR)

CD1

V11

AD11

C12

172

B_A22

DATA

F14

152

CD2

H17

140

AD12

208

B_A23

DEVSEL

197

CE1

P13

AD13

206

B_A24

FRAME

193

CE2

R13

AD14

205

B_A25

GND

B10

181

A_D0

H14

141

AD15

204

GND

207

B_BVD1(STSCHG/R1)

A_D1

G18

144

AD16

191

GND

194

B_BVD2(SPKR)

A_D2

G14

146

AD17

190

CD1

GND

E18

153

A_D3

U11

AD18

189

CD2

GND

F12

167

A_D4

R11

AD19

188

CE1

GND

A_D5

U12

AD20

186

CE2

GND

A_D6

R12

AD21

185

B_D0

W10

GND

K18

129

A_D7

V13

AD22

F10

184

B_D1

U10

GND

A_D8

H15

142

AD23

E10

183

B_D2

P10

GND

A_D9

G17

145

AD24

F11

179

B_D3

GND

V14

A_D10

F19

147

AD25

E13

165

B_D4

C13

168

GNT

2±7

Table 2±4. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

SIGNAL NAME

PIN NO.

GHK

PDV

GHK

PDV

GHK

PDV

GHK

PDV

A11

175

MFUNC5

F13

160

SPKROUT

G15

149

VCC

GRST

IDSEL

C10

182

MFUNC6

B15

161

198

VCC

N15

113

STOP

195

PAR

202

D19

156

VCC

IRDY

SUSPEND

LATCH

F17

150

PCLK

A10

180

196

VCC

W12

TRDY

MFUNC0

F15

154

199

VCC

B14

164

VCCA

M17

120

PERR

MFUNC1

E17

155

A14

166

VCC

187

VCCB

PRST

MFUNC2

A16

157

B13

169

VCC

201

VCCI

F18

148

REQ

MFUNC3

C15

158

C14

163

VCC

VCCP

RI_OUT/PME

MFUNC4

E14

159

200

VCC

G19

143

VCCP

E11

178

SERR

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference.

			Table 2±5. Power Supply
	TERMINAL
			DESCRIPTION
NAME	NO.		DESCRIPTION

	PDV	GHK
	PDV	GHK

	13, 22, 44, 75,	B10, C5, E8,
GND	96, 129, 153,	E18, F12, G2,	Device ground terminals
GND	167, 181, 194,	J5, K18, P2,	Device ground terminals
	167, 181, 194,	J5, K18, P2,
	207	P9, V14

	7, 31, 64, 86,	B14, C9, E7,
VCC	113, 143, 164,	F3, G19, L3,	Power supply terminal for core logic (3.3 V)
	187, 201	N15, U7, W12
VCCA	120	M17	Clamp voltage for PC Card A interface. Matches Card A signaling environment, 5 V or 3.3 V.
VCCB	38	M5	Clamp voltage for PC Card B interface. Matches Card B signaling environment, 5 V or 3.3 V.
VCCI	148	F18	Clamp voltage for interrupt subsystem interface and miscellaneous I/O, 5 V or 3.3 V
VCCP	1, 178	D1, E11	Clamp voltage for PCI signaling, 5 V or 3.3 V

				Table 2±6. PC Card Power Switch
TERMINAL
			I/O	DESCRIPTION
NAME	NO.		I/O	DESCRIPTION

	PDV	GHK
	PDV	GHK

				Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults
				to an input, but can be changed to a PCI1420 output by using bit 27 (P2CCLK) in the system control register
CLOCK	151	E19	I/O	(see Section 4.29). The TPS2206 defines the maximum frequency of this signal to be 2 MHz.
				If a system design defines this terminal as an output, then this terminal requires an external pulldown
				resistor. The frequency of the PCI1420 output CLOCK is derived from dividing the PCI CLK by 36.

DATA	152	F14	O	Power switch data. DATA is used to serially communicate socket power control information to the power
DATA	152	F14	O	switch.
				switch.

				Power switch latch. LATCH is asserted by the PCI1420 to indicate to the power switch that the data on the
LATCH	150	F17	O	DATA line is valid. When a pulldown resistor is implemented on this terminal, the MFUNC1 and MFUNC4
				terminals provide the serial EEPROM SDA and SCL interface.

2±8

Table 2±7. PCI System

TERMINAL

NAME

NO.

I/O

DESCRIPTION

PDV

GHK

Global reset. When the global reset is asserted, the

signal causes the PCI1420 to place all output

GRST

buffers in a high-impedance state and reset all internal registers. When

GRST

is asserted, the device is

completely in its default state. For systems that require wake-up from D3, GRST will normally be asserted

175

A11

only during initial boot. PRST should be asserted following initial boot so that PME context is retained when

GRST

transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST should be tied to

PRST.

mode is enabled, the device is protected from the

and the internal registers are

When the

SUSPEND

GRST,

preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

PCLK

180

A10

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the

rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted,

causes the PCI1420 to place all output buffers in a

PRST

high-impedance state and reset internal registers. When PRST is asserted, the device is completely

166

A14

nonfunctional. After PRST is deasserted, the PCI1420 is in a default state.

PRST

When the

SUSPEND

mode is enabled, the device is protected from the

PRST,

and the internal registers are

preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

2±9

						Table 2±8. PCI Address and Data
	TERMINAL
					I/O			DESCRIPTION
NAME		NO.			I/O			DESCRIPTION

		PDV	GHK
		PDV	GHK

AD31		170		A13
AD30		171		E12
AD29		173		B12
AD28		174		A12
AD27		176		B11
AD26		177		C11
AD25		165		E13
AD24		179		F11
AD23		183		E10
AD22		184		F10
AD21		185		A9
AD20		186		B9
AD19		188		F9
AD18		189		E9
AD17		190		A8		PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
AD16		191		B8
AD16		191		B8	I/O	interface. During the address phase of a primary bus PCI cycle, AD31±AD0 contain a 32-bit address or other
AD15		204		F6	I/O
AD15		204		F6		destination information. During the data phase, AD31±AD0 contain data.
AD14		205		B5
AD14		205		B5
AD13		206		E6
AD12		208		A4
AD11		172		C12
AD10		2		E3
AD9		3		F5
AD8		4		G6
AD7		6		E1
AD6		8		F2
AD5		9		G5
AD4		10		F1
AD3		11		H6
AD2		12		G3
AD1		14		G1
AD0		15		H5

		162		A15		PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
C/BE3
C/BE3						the address phase of a primary bus PCI cycle, C/BE3±C/BE0 define the bus command. During the data
C/BE2		192		C8
C/BE2		192		C8	I/O	phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit
C/BE1		203		A5	I/O
C/BE1		203		A5		data bus carry meaningful data. C/BE0 applies to byte 0 (AD7±AD0), C/BE1 applies to byte 1 (AD15±AD8),
C/BE0		5		E2
C/BE0		5		E2		C/BE2 applies to byte 2 (AD23±AD16), and C/BE3 applies to byte 3 (AD31±AD24).


						PCI bus parity. In all PCI bus read and write cycles, the PCI1420 calculates even parity across the
						AD31±AD0 and
PAR		202		C6	I/O	AD31±AD0 and	C/BE3±C/BE0 buses. As an initiator during PCI cycles, the PCI1420 outputs this parity
PAR		202		C6	I/O	indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the

						initiator's parity indicator. A compare error results in the assertion of a parity error (PERR).

2±10

Table 2±9. PCI Interface Control

TERMINAL

I/O

DESCRIPTION

NAME

NO.

PDV

GHK

PCI device select. The PCI1420 asserts

DEVSEL

to claim a PCI cycle as the target device. As a PCI initiator

DEVSEL

197

I/O

on the bus, the PCI1420 monitors DEVSEL until a target responds. If no target responds before timeout

occurs, then the PCI1420 terminates the cycle with an initiator abort.

PCI cycle frame.

FRAME

is driven by the initiator of a bus cycle.

FRAME

is asserted to indicate that a bus

FRAME

193

I/O

transaction is beginning, and data transfers continue while this signal is asserted. When

FRAME

deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant.

is driven by the PCI bus arbiter to grant the PCI1420 access to the PCI bus after the

GNT

168

C13

current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI

bus parking algorithm.

IDSEL

182

C10

Initialization device select. IDSEL selects the PCI1420 during configuration space accesses. IDSEL can be

connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready.

indicates the PCI bus initiator's ability to complete the current data phase of the

IRDY

195

I/O

transaction. A data phase is completed on a rising edge of PCLK where both

IRDY

and TRDY are asserted.

Until IRDY and TRDY are both sampled asserted, wait states are inserted.

199

I/O

PCI parity error indicator.

PERR

is driven by a PCI device to indicate that calculated parity does not match

PERR

PAR when PERR is enabled through bit 6 of the command register (see Section 4.4).

169

B13

PCI bus request.

is asserted by the PCI1420 to request access to the PCI bus as an initiator.

REQ

PCI system error.

is an output that is pulsed from the PCI1420 when enabled through bit 8 of the

SERR

200

command register (see Section 4.4) indicating a system error has occurred. The PCI1420 need not be the

SERR

target of the PCI cycle to assert this signal. When SERR is enabled in the command register, this signal also

pulses, indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal.

STOP

is driven by a PCI target to request the initiator to stop the current PCI bus

STOP

198

I/O

transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not

support burst data transfers.

PCI target ready.

TRDY

indicates the primary bus target's ability to complete the current data phase of the

TRDY

196

I/O

transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted.

Until both IRDY and TRDY are asserted, wait states are inserted.

2±11

Table 2±10. Multifunction and Miscellaneous Pins

TERMINAL

I/O

DESCRIPTION

NAME

NO.

PDV

GHK

Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt

INTA,

GPI0, GPO0, socket

MFUNC0

154

F15

I/O

activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See

Section 4.30, Multifunction Routing Register, for configuration details.

Multifunction terminal 1. MFUNC1 can be configured as parallel PCI interrupt

INTB,

GPI1, GPO1, socket

activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See

Section 4.30, Multifunction Routing Register, for configuration details.

MFUNC1

155

E17

I/O

Serial data (SDA). When LATCH is detected low after a PCI reset, the MFUNC1 terminal provides the

SDA signaling for the serial bus interface. The two-pin serial interface loads the subsystem identification

and other register defaults from an EEPROM after a PCI reset. See Section 3.6.1, Serial Bus Interface

Implementation, for details on other serial bus applications.

Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2, socket

MFUNC2

157

A16

I/O

activity LED output, ZV switching outputs, CardBus audio PWM, GPE, RI_OUT, or a parallel IRQ. See

Section 4.30, Multifunction Routing Register, for configuration details.

MFUNC3

158

C15

I/O

Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal

IRQSER. See Section 4.30, Multifunction Routing Register, for configuration details.

Multifunction terminal 4. MFUNC4 can be configured as PCI

LOCK, GPI3, GPO3, socket activity LED

output, ZV switching outputs, CardBus audio PWM, GPE, RI_OUT, or a parallel IRQ. See Section 4.30,

Multifunction Routing Register, for configuration details.

MFUNC4

159

E14

I/O

Serial clock (SCL). When LATCH is detected low after a PCI reset, the MFUNC4 terminal provides the

SCL signaling for the serial bus interface. The two-pin serial interface loads the subsystem identification

and other register defaults from an EEPROM after a PCI reset. See Section 3.6.1, Serial Bus Interface

Implementation, for details on other serial bus applications.

Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant, GPI4, GPO4, socket activity

MFUNC5

160

F13

I/O

LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See Section 4.30,

Multifunction Routing Register, for configuration details.

MFUNC6

161

B15

I/O

Multifunction terminal 6. MFUNC6 can be configured as a PCI

CLKRUN

or a parallel IRQ. See

Section 4.30, Multifunction Routing Register, for configuration details.

Ring indicate out and power management event output. Terminal provides an output for ring-indicate or

RI_OUT/PME

163

C14

PME signals.

Speaker output. SPKROUT is the output to the host system that can carry

or CAUDIO through

SPKR

SPKROUT

149

G15

the PCI1420 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card

SPKR//CAUDIO inputs.

Suspend.

SUSPEND

protects the internal registers from clearing when the

GRST

PRST

signal is

SUSPEND

156

D19

asserted. See Section 3.8.4, Suspend Mode, for details.

2±12

Table 2±11. 16-Bit PC Card Address and Data (Slots A and B)

	TERMINAL

		NUMBER			I/O	DESCRIPTION

NAME	SLOT A²		SLOT B³
NAME	SLOT A²		SLOT B³
	PDV	GHK	PDV	GHK

A25	121	M18	55	R6
A24	118	N19	53	W4
A23	116	N17	51	R3
A22	114	P19	49	R2
A21	111	P17	47	R1
A20	109	R18	45	N5
A19	107	P15	42	N6
A18	105	T19	40	N2
A17	103	U15	37	M6
A16	112	P18	48	P6
A15	115	M14	50	P5
A14	108	N14	43	P1
A13	106	R17	41	N3	O	PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.
A12	117	N18	52	T1	O
A12	117	N18	52	T1
A11	100	P14	34	M1
A10	95	W14	29	L1
A9	102	R14	36	M3
A8	104	W16	39	N1
A7	119	M15	54	U5
A6	123	L19	57	V5
A5	125	L17	59	U6
A4	126	L15	60	V6
A3	128	K19	62	W6
A2	131	K15	65	V7
A1	132	K14	66	W7
A0	133	J19	67	R8

D15	93	U13	27	K5
D14	91	W13	25	K2
D13	89	P12	23	J6
D12	87	V12	20	J2
D11	84	P11	18	H1
D10	147	F19	81	W11
D9	145	G17	79	R10
D8	142	H15	77	V10	I/O	PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.
D7	92	V13	26	K3	I/O
D7	92	V13	26	K3
D6	90	R12	24	K1
D5	88	U12	21	J3
D4	85	R11	19	J1
D3	83	U11	17	H2
D2	146	G14	80	P10
D1	144	G18	78	U10
D0	141	H14	76	W10

² Terminal name for slot A is preceded with A_. For example, the full name for terminals 121 and M18 are A_A25. ³ Terminal name for slot B is preceded with B_. For example, the full name for terminals 55 and R6 are B_A25.

2±13

Table 2±12. 16-Bit PC Card Interface Control (Slots A and B)

TERMINAL

NUMBER

I/O

DESCRIPTION

NAME

SLOT A²

SLOT B³

PDV

GHK

PDV

GHK

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that

include batteries. BVD1 is used with BVD2 as an indication of the condition of the

batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery

is good. When BVD2 is low and BVD1 is high, the battery is weak and should be

replaced. When BVD1 is low, the battery is no longer serviceable and the data in

BVD1

138

H19

the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change-Interrupt

Configuration Register, for enable bits. See Section 5.5, ExCA

Card

(STSCHG/RI)

Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the

status bits for this signal.

Status change.

STSCHG

is used to alert the system to a change in the READY,

write protect, or battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate.

is used by 16-bit modem cards to indicate a ring detection.

Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that

include batteries. BVD2 is used with BVD1 as an indication of the condition of the

batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery

is good. When BVD2 is low and BVD1 is high, the battery is weak and should be

replaced. When BVD1 is low, the battery is no longer serviceable and the data in

the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change-Interrupt

BVD2

Configuration Register, for enable bits. See Section 5.5, ExCA

Card

137

J15

Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the

(SPKR)

status bits for this signal.

Speaker.

SPKR

is an optional binary audio signal available only when the card and

socket have been configured for the 16-bit I/O interface. The audio signals from

cards A and B are combined by the PCI1420 and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA

operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to

indicate a request for a DMA operation.

V11

Card detect 1 and Card detect 2.

CD1

and

CD2

are internally connected to ground

CD1

on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled

CD2

140

H17

low. For signal status, see Section 5.2, ExCA Interface Status Register.

P13

Card enable 1 and card enable 2.

CE1

and

CE2

enable evenand odd-numbered

CE1

address bytes. CE1 enables even-numbered address bytes, and CE2 enables

CE2

R13

odd-numbered address bytes.

Input acknowledge.

INPACK

is asserted by the PC Card when it can respond to an

I/O read cycle at the current address.

127

L14

INPACK

DMA request.

INPACK

can be used as the DMA request signal during DMA

operations from a 16-bit PC Card that supports DMA. If it is used as a strobe, then

the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read.

IORD

is asserted by the PCI1420 to enable 16-bit I/O PC Card data output

during host I/O read cycles.

W15

IORD

DMA write.

IORD

is used as the DMA write strobe during DMA operations from a

16-bit PC Card that supports DMA. The PCI1420 asserts IORD during DMA

transfers from the PC Card to host memory.

I/O write.

IOWR

is driven low by the PCI1420 to strobe write data into 16-bit I/O PC

Cards during host I/O write cycles.

101

V15

IOWR

DMA read.

IOWR

is used as the DMA write strobe during DMA operations from a

16-bit PC Card that supports DMA. The PCI1420 asserts IOWR during transfers

from host memory to the PC Card.

² Terminal name for slot A is preceded with A_. For example, the full name for terminals 127 and L14 are A_INPACK. ³ Terminal name for slot B is preceded with B_. For example, the full name for terminals 61 and R7 are B_INPACK.

2±14

Table 2±12. 16-Bit PC Card Interface Control (Slots A and B) (Continued)

TERMINAL

NUMBER

I/O

DESCRIPTION

NAME

SLOT A²

SLOT B³

PDV

GHK

PDV

GHK

Output enable.

is driven low by the PCI1420 to enable 16-bit memory PC Card data

output during host memory read cycles.

U14

DMA terminal count.

is used as terminal count (TC) during DMA operations to a 16-bit

PC Card that supports DMA. The PCI1420 asserts OE to indicate TC for a DMA write

operation.

Ready. The ready function is provided by READY when the 16-bit PC Card and the host

socket are configured for the memory-only interface. READY is driven low by the 16-bit

memory PC Cards to indicate that the memory card circuits are busy processing a previous

READY

135

J17

write command. READY is driven high when the 16-bit memory PC Card is ready to accept

(IREQ)

a new data transfer command.

Interrupt request.

IREQ

is asserted by a 16-bit I/O PC Card to indicate to the host that a

device on the 16-bit I /O PC Card requires service by the host software. IREQ is high

(deasserted) when no interrupt is requested.

Attribute memory select.

REG

remains high for all common memory accesses. When

REG

is asserted, access is limited to attribute memory

(OE

or WE active) and to the I/O space

(IORD or IOWR active). Attribute memory is a separately accessed section of card memory

and is generally used to record card capacity and other configuration and attribute

130

K17

information.

REG

DMA acknowledge.

REG

is used as a DMA acknowledge

(DACK

) during DMA operations

to a 16-bit PC Card that supports DMA. The PCI1420 asserts REG to indicate a DMA

operation.

REG

is used in conjunction with the DMA read (IOWR) or DMA write

(IORD)

strobes to transfer data.

RESET

124

L18

PC Card reset. RESET forces a hard reset to a 16-bit PC Card.

Bus cycle wait.

is driven by a 16-bit PC Card to extend the completion of the memory

136

J14

WAIT

or I/O cycle in progress.

Write enable.

is used to strobe memory write data into 16-bit memory PC Cards.

is also used for memory PC Cards that employ programmable memory technologies.

110

R19

DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that

supports DMA. The PCI1420 asserts WE to indicate TC for a DMA read operation.

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the

write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the

16-bit port (IOIS16) function.

is asserted by the 16-bit PC Card

I/O is 16 bits.

IOIS16

applies to 16-bit I/O PC Cards.

IOIS16

139

H18

when the address on the bus corresponds to an address to which the 16-bit PC Card

(IOIS16)

responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit

PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a request for

a DMA operation.

134

J18

Voltage sense 1 and voltage sense 2.

and

when used in conjunction with each

VS1

I/O

VS1

VS2,

VS2

122

M19

other, determine the operating voltage of the PC Card.

² Terminal name for slot A is preceded with A_. For example, the full name for terminals 110 and R19 are A_WE. ³ Terminal name for slot B is preceded with B_. For example, the full name for terminals 46 and P3 are B_WE.

2±15

Table 2±13. CardBus PC Card Interface System (Slots A and B)

TERMINAL

NUMBER

I/O

DESCRIPTION

NAME

SLOT A²

SLOT B³

PDV

GHK

PDV

GHK

CardBus clock. CCLK provides synchronous timing for all transactions on the

CardBus interface. All signals except

CRST,

CCLKRUN, CINT, CSTSCHG, CAUDIO,

CCLK

112

P18

CCD2,

CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all

timing parameters are defined with the rising edge of this signal. CCLK operates at

the PCI bus clock frequency, but it can be stopped in the low state or slowed down

for power savings.

CardBus clock run.

CCLKRUN

is used by a CardBus PC Card to request an increase

CCLKRUN

139

H18

in the CCLK frequency, and by the PCI1420 to indicate that the CCLK frequency is

going to be decreased.

CardBus reset.

CRST

brings CardBus PC Card-specific registers, sequencers, and

signals to a known state. When CRST is asserted, all CardBus PC Card signals are

CRST

124

L18

I/O

placed in a high-impedance state, and the PCI1420 drives these signals to a valid

logic level. Assertion can be asynchronous to CCLK, but deassertion must be

synchronous to CCLK.

² Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18 are A_CCLK. ³ Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P6 are B_CCLK.

2±16

Table 2±14. CardBus PC Card Address and Data (Slots A and B)

TERMINAL

NUMBER

I/O

DESCRIPTION

NAME

SLOT A²

SLOT B³

PDV

GHK

PDV

GHK

CAD31

147

F19

W11

CAD30

145

G17

R10

CAD29

144

G18

U10

CAD28

142

H15

V10

CAD27

141

H14

W10

CAD26

133

J19

CAD25

132

K14

CAD24

131

K15

CAD23

128

K19

CAD22

126

L15

CAD21

125

L17

CAD20

123

L19

CAD19

121

M18

CAD18

119

M15

CAD17

118

N19

CardBus address and data. These signals make up the multiplexed CardBus address

CAD16

103

U15

I/O

and data bus on the CardBus interface. During the address phase of a CardBus cycle,

CAD15

101

V15

CAD31±CAD0 contain a 32-bit address. During the data phase of a CardBus cycle,

CAD14

102

R14

CAD31±CAD0 contain data. CAD31 is the most significant bit.

CAD13

W15

CAD12

100

P14

CAD11

U14

CAD10

R13

CAD9

W14

CAD8

U13

CAD7

V13

CAD6

P12

CAD5

R12

CAD4

V12

CAD3

U12

CAD2

P11

CAD1

R11

CAD0

U11

CardBus bus commands and byte enables.

CC/BE3±CC/BE0 are multiplexed on the

130

K17

same CardBus terminals. During the address phase of a CardBus cycle,

CC/BE3

CC/BE3±CC/BE0 define the bus command. During the data phase, this 4-bit bus is used

CC/BE2

117

N18

I/O

as byte enables. The byte enables determine which byte paths of the full 32-bit data bus

CC/BE1

104

W16

carry meaningful data. CC/BE0 applies to byte 0 (CAD7±CAD0), CC/BE1 applies to

CC/BE0

P13

byte 1 (CAD15±CAD8), CC/BE2 applies to byte 2 (CAD23±CAD8), and CC/BE3 applies

to byte 3 (CAD31±CAD24).

CardBus parity. In all CardBus read and write cycles, the PCI1420 calculates even parity

across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1420

CPAR

106

R17

I/O

outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated

parity is compared to the initiator's parity indicator; a compare error results in a parity

error assertion.

² Terminal name for slot A is preceded with A_. For example, the full name for terminals 106 and R17 are A_CPAR. ³ Terminal name for slot B is preceded with B_. For example, the full name for terminals 41 and N3 are B_CPAR.

2±17

Table 2±15. CardBus PC Card Interface Control (Slots A and B)

TERMINAL

NUMBER

I/O

DESCRIPTION

NAME

SLOT A²

SLOT B³

PDV

GHK

PDV

GHK

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system

CAUDIO

137

J15

speaker. The PCI1420 supports the binary audio mode and outputs a binary signal

from the card to SPKROUT.

107

P15

I/O

CardBus lock.

is used to gain exclusive access to a target.

CBLOCK

V11

CardBus detect 1 and CardBus detect 2.

CCD1

and

CCD2

are used in conjunction

CCD1

with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the

CCD2

140

H17

operating voltage and card type.

CardBus device select. The PCI1420 asserts

to claim a CardBus cycle as

CDEVSEL

111

P17

I/O

the target device. As a CardBus initiator on the bus, the PCI1420 monitors CDEVSEL

CDEVSEL

until a target responds. If no target responds before timeout occurs, then the PCI1420

terminates the cycle with an initiator abort.

CardBus cycle frame.

CFRAME

is driven by the initiator of a CardBus bus cycle.

116

N17

I/O

CFRAME is asserted to indicate that a bus transaction is beginning, and data

CFRAME

transfers continue while this signal is asserted. When CFRAME is deasserted, the

CardBus bus transaction is in the final data phase.

110

R19

CardBus bus grant.

CGNT

is driven by the PCI1420 to grant a CardBus PC Card

CGNT

access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt.

is asserted low by a CardBus PC Card to request interrupt

135

J17

CINT

servicing from the host.

CardBus initiator ready.

CIRDY

indicates the CardBus initiator's ability to complete

115

M14

I/O

the current data phase of the transaction. A data phase is completed on a rising edge

CIRDY

of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are

both sampled asserted, wait states are inserted.

CardBus parity error.

CPERR

reports parity errors during CardBus transactions,

CPERR

108

N14

I/O

except during special cycles. It is driven low by a target two clocks following that data

when a parity error is detected.

127

L14

CardBus request.

CREQ

indicates to the arbiter that the CardBus PC Card desires

CREQ

use of the CardBus bus as an initiator.

CardBus system error.

CSERR

reports address parity errors and other system errors

136

J14

that could lead to catastrophic results. CSERR is driven by the card synchronous to

CSERR

CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The

PCI1420 can report CSERR to the system by assertion of SERR on the PCI interface.

CardBus stop.

CSTOP

is driven by a CardBus target to request the initiator to stop

CSTOP

109

R18

I/O

the current CardBus transaction.

CSTOP

is used for target disconnects, and is

commonly asserted by target devices that do not support burst data transfers.

CSTSCHG

138

H19

CardBus status change. CSTSCHG alerts the system to a change in the card's

status, and is used as a wake-up mechanism.

CardBus target ready.

indicates the CardBus target's ability to complete the

CTRDY

114

P19

I/O

current data phase of the transaction. A data phase is completed on a rising edge of

CTRDY

CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are

inserted.

CVS1

134

J18

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used

I/O

in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards

CVS2

122

M19

to determine the operating voltage and card type.

² Terminal name for slot A is preceded with A_. For example, the full name for terminals 137 and J15 are A_CAUDIO. ³ Terminal name for slot B is preceded with B_. For example, the full name for terminals 71 and W9 are B_CAUDIO.

2±18

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