TEXAS INSTRUMENTS PCI1620 Technical data

PCI1620

PCI1620 PDV/GHK

Dual Socket PC Card and UltraMedia Controller

Data Manual

August 2003

PCIBus Solutions

SCPS064C

IMPORTANT NOTICE

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Products		Applications
Amplifiers	amplifier.ti.com	Audio	www.ti.com/audio
Data Converters	dataconverter.ti.com	Automotive	www.ti.com/automotive
DSP	dsp.ti.com	Broadband	www.ti.com/broadband
Interface	interface.ti.com	Digital Control	www.ti.com/digitalcontrol
Logic	logic.ti.com	Military	www.ti.com/military
Power Mgmt	power.ti.com	Optical Networking	www.ti.com/opticalnetwork
Microcontrollers	microcontroller.ti.com	Security	www.ti.com/security
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		Wireless	www.ti.com/wireless
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Copyright 2003, Texas Instruments Incorporated

			Contents
1	Introduction . .		. . . . . . . . . . . . . .	. . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	1−1
	1.1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				1−1
	1.2	Features	. . . . . . . . . . . . .	. . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	1−1
	1.3	Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				1−2
	1.4	Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				1−2
	1.5	Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				1−3
	1.6	Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				1−3
2	Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2−1
	2.1	Terminal Assignments for PCI1620 . . . . . . . . . . . . . . . . . . . . . . . . . . . .				2−1
3	Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−1
	3.1	Summary of UltraMedia Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				3−1
		3.1.1	SmartMedia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3−1
		3.1.2	MultiMediaCard (MMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3−1
		3.1.3	Secure Digital (SD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3−2
		3.1.4	Memory Stick . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3−2
		3.1.5	Smart Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3−2
	3.2	I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				3−3
	3.3	Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				3−3
	3.4	Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . .				3−3
		3.4.1	PCI Bus Lock			3−3
				(LOCK)
		3.4.2	Serial EEPROM I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3−4
		3.4.3	PCI1620 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3−4

3.4.4Loading the Subsystem Identification (EEPROM Interface) 3−6

3.5 PC Card Applications Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6 3.5.1 Card Detection in an UltraMedia System . . . . . . . . . . . . . . . 3−6 3.5.2 Query Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8 3.5.3 P2C Power Switch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8 3.5.4 Zoomed-Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9 3.5.5 Standardized Zoomed-Video Register Model . . . . . . . . . . . 3−11 3.5.6 Integrated Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11 3.5.7 SPKROUT Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−12 3.5.8 LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3−13 3.5.9 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−13 3.5.10 PCI Firmware Loading Function Programming Model . . . . 3−14

3.6 Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−16

3.6.1PC Card Functional and Card Status-Change Interrupts . 3−17

3.6.2 Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18 3.6.3 Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3−19 3.6.4 Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3−19

iii

3.6.5 Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . . 3−20 3.6.6 SMI Support in the PCI1620 . . . . . . . . . . . . . . . . . . . . . . . . . . 3−20 3.7 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−19 3.7.1 Integrated Low-Dropout Voltage Regulator (LDO-VR) . . . . 3−20 3.7.2 Clock Run Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−21 3.7.3 CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3−21 3.7.4 16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . . 3−21 3.7.5 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−21 3.7.6 Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . . 3−22 3.7.7 Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−22 3.7.8 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−23 3.7.9 CardBus Bridge Power Management . . . . . . . . . . . . . . . . . . 3−24 3.7.10 ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−25

3.7.11Master List of PME Context Bits and

Global Reset-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−26

4 PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1

4.1 PCI Configuration Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . 4−1 4.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2 4.3 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2 4.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4 4.6 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5 4.7 Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5 4.8 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5 4.9 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6 4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6 4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6 4.12 CardBus Socket Registers/ExCA Base Address Register . . . . . . . . . 4−7 4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7 4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8 4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9 4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9 4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9 4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10 4.19 CardBus Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10 4.20 CardBus Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11 4.21 CardBus I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11 4.22 CardBus I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12 4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12 4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13 4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14 4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−15 4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−15 4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register . . . . . . . . . 4−16

iv

4.29	Subsystem Vendor ID Register (Firmware Loader Function) . . . . . . .	4−16
4.30	Subsystem ID Register (Firmware Loader Function) . . . . . . . . . . . . .	4−17
4.31	System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−18
4.32	MC_CD_Debounce Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−20
4.33	General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−21
4.34	General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . .	4−22
4.35	General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . .	4−23
4.36	General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−23
4.37	General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−24
4.38	Multifunction Routing Status Register . . . . . . . . . . . . . . . . . . . . . . . . . .	4−25
4.39	Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−27
4.40	Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−28
4.41	Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−29
4.42	Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−30
4.43	Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−31
4.44	Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−31
4.45	Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . .	4−32
4.46	Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . .	4−33
4.47	Power Management Control/Status Bridge Support
	Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−34
4.48	Power-Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−34
4.49	Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−35
4.50	Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−35
4.51	Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−36
4.52	Serial Bus Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−37

5 ExCA Compatibility Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . 5−1

5.1 ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . 5−5 5.2 ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−6 5.3 ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−7 5.4 ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . 5−9 5.5 ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−10 5.6 ExCA Card Status-Change Interrupt Configuration Register . . . . . . . 5−11 5.7 ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 5−12 5.8 ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−13

5.9ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . . 5−14

5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . . 5−14

5.11ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . . 5−15

5.12ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . . 5−15

5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers . . . 5−16

5.14ExCA Memory Windows 0−4 Start-Address High-Byte Registers . . . 5−17

5.15ExCA Memory Windows 0−4 End-Address Low-Byte Registers . . . . 5−18

5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers . . . 5−19

5.17ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers . . 5−20

5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers . 5−21

v

5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . 5−22 5.20 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−23

5.21ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . . 5−24

5.22	ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . .	5−24
5.23	ExCA Memory Windows 0−4 Page Registers . . . . . . . . . . . . . . . . . . .	5−25
6 CardBus Socket Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . . . . .		6−1

6.1 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2 6.2 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3 6.3 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−4 6.4 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−5 6.5 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7 6.6 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−8

7 PCI Firmware Loading Function Programming Model (Function 2) . . . 7−1

7.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−1 7.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−1 7.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−2 7.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−3 7.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 7−4 7.6 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−4 7.7 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−4 7.8 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−5 7.9 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−5 7.10 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−5 7.11 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−6 7.12 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−6 7.13 Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−6 7.14 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−7 7.15 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−7 7.16 Min Grant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−7 7.17 Max Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−7 7.18 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−8 7.19 Next-Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−8 7.20 Power-Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 7−9 7.21 Power-Management Control/Status Register . . . . . . . . . . . . . . . . . . . . 7−10 7.22 Power-Management Bridge Support Extension Register . . . . . . . . . . 7−10 7.23 Power-Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−11

8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−1

8.1Absolute Maximum Ratings Over Operating Temperature Ranges . 8−1

8.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 8−2

8.3Electrical Characteristics Over Recommended

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−3

8.4PCI Clock/Reset Timing Requirements Over Recommended Ranges

of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . 8−3

8.5PCI Timing Requirements Over Recommended Ranges of Supply

Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . 8−4

vi

8.6	Switching Characteristics for PHY-Link Interface . . . . . . . . . . . . . . . . .	8−4
8.7	Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . .	8−5
8.8	PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . .	8−6
8.9	PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8−6

8.10Timing Requirements Over Recommended Ranges of Supply

Voltage and Operating Free-Air Temperature, Memory Cycles . . . . 8−8

8.11Timing Requirements Over Recommended Ranges of Supply

Voltage and Operating Free-Air Temperature, I/O Cycles . . . . . . . . . 8−8

8.12Switching Characteristics Over Recommended Ranges of Supply

Voltage and Operating Free-Air Temperature, Miscellaneous . . . . . . 8−9 8.13 PC Card Parameter Measurement Information . . . . . . . . . . . . . . . . . . 8−9

9 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−1

vii

List of Illustrations

Figure				Title	Page
2−1 PCI1620 GHK Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2−1
2−2 PCI1620 PDV Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2−2
3−1 PCI1620 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−1
3−2 3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−3
3−3 Serial EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−4
3−4 Example SmartMedia Query Terminal Configuration . . . . . . . . . . . . . . . . . . .					3−8
3−5 TPS222X Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−9
3−6 Zoomed-Video Implementation Using PCI1620 . . . . . . . . . . . . . . . . . . . . . . .					3−10
3−7 Zoomed-Video Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−10
3−8 SPKROUT Connection to Speaker Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−13
3−9 Two Sample LED Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−13
3−10 IRQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−19
3−11 Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−22
				Functional Diagram	3−23
3−12 RI_OUT
3−13 Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					3−25
5−1 ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					5−2
5−2 ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					5−2
6−1 Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . . .					6−1
8−1 Load Circuit and Voltage Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					8−5
8−2 PCLK Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					8−6
8−3			Timing Waveforms		8−6
	RSTIN
8−4 Shared Signals Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					8−6
8−5 PC Card Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					8−9
8−6 PC Card I/O Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					8−10
8−7 Miscellaneous PC Card Delay Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					8−10

viii

List of Tables

Table	Title	Page
1−1 Terms and Definitions . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	1−3
2−1 Signal Names by PDV Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		2−3
2−2 Signal Names by GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		2−5
2−3 CardBus PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . .		2−8
2−4 16-Bit PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . . .		2−10
2−5 Power Supply Terminals . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2−12
2−6 PC Card Power Switch Terminals .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2−12
2−7 PCI System Terminals . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2−13
2−8 PCI Address and Data Terminals . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2−14
2−9 PCI Interface Control Terminals . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2−15
2−10 Multifunction and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . .		2−16
2−11 CardBus PC Card Interface System Terminals (Slots A and B) . . . . . . . . .		2−17
2−12 CardBus PC Card Address and Data Terminals (Slots A and B) . . . . . . . .		2−18
2−13 CardBus PC Card Terminals (Slots A and B) . . . . . . . . . . . . . . . . . . . . . . . .		2−19
2−14 16-Bit PC Card Address and Data Terminals (Slots A and B) . . . . . . . . . .		2−20
2−15 16-Bit PC Card Interface Control Terminals (Slots A and B) . . . . . . . . . . . .		2−21
2−16 UltraMedia Mapping to the PCMCIA 68-Terminal Connector . . . . . . . . . . .		2−23
2−17 UltraMedia Terminals (Slots A & B)	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2−25
3−1 Serial EEPROM Map . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3−5
3−2 PC Card—Card Detect and Voltage Sense Connections . . . . . . . . . . . . . . .		3−7
3−3 Query Terminal Definition . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3−7
3−4 Query Terminals − Voltage . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3−7
3−5 Query Terminals − Media Interface Implementation . . . . . . . . . . . . . . . . . . . .		3−8
3−6 Functionality of the ZV Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3−11
3−7 Terminals With Integrated Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . .		3−12
3−8 CardBus Socket Registers . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3−14
3−9 Firmware Loader I/O Register Map .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3−14
3−10 Firmware Loader Control Register Description . . . . . . . . . . . . . . . . . . . . . . .		3−16
3−11 Interrupt Mask and Flag Registers .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3−17
3−12 PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . .		3−18
3−13 Interrupt Pin Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3−20
3−14 SMI Control . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3−20
3−15 Requirements for Internal/External 2.5-V Core Power Supply . . . . . . . . . .		3−20
3−16 Power Management Registers . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3−24
4−1 Functions 0 and 1 PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . .		4−1
4−2 Command Register Description . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−3
4−3 Status Register Description . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−4

ix

4−4 Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−8
4−5 Interrupt Pin Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−13
4−6 Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−14
4−7 System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−18
4−8 General Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−21
4−9 General-Purpose Event Status Register Description . . . . . . . . . . . . . . . . . . .	4−22
4−10 General-Purpose Event Enable Register Description . . . . . . . . . . . . . . . . .	4−23
4−11 General-Purpose Input Register Description . . . . . . . . . . . . . . . . . . . . . . . . .	4−23
4−12 General-Purpose Output Register Description . . . . . . . . . . . . . . . . . . . . . . .	4−24
4−13 Multifunction Routing Status Register Description . . . . . . . . . . . . . . . . . . . .	4−25
4−14 Retry Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−27
4−15 Card Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−28
4−16 Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−29
4−17 Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−30
4−18 Power Management Capabilities Register Description . . . . . . . . . . . . . . . .	4−32
4−19 Power Management Control/Status Register Description . . . . . . . . . . . . . .	4−33
4−20 Power Management Control/Status Bridge Support Extensions
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−34
4−21 Serial Bus Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−35
4−22 Serial Bus Index Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4−35
4−23 Serial Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . . .	4−36
4−24 Serial Bus Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . .	4−37
5−1 ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5−3
5−2 ExCA Identification and Revision Register Description . . . . . . . . . . . . . . . . .	5−5
5−3 ExCA Interface Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .	5−6
5−4 ExCA Power Control Register Description—82365SL Support . . . . . . . . . .	5−7
5−5 ExCA Power Control Register Description—82365SL-DF Support . . . . . . .	5−8
5−6 ExCA Interrupt and General Control Register Description . . . . . . . . . . . . . .	5−9
5−7 ExCA Card Status-Change Register Description . . . . . . . . . . . . . . . . . . . . . .	5−10
5−8 ExCA Card Status-Change Interrupt Configuration
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5−11
5−9 ExCA Address Window Enable Register Description . . . . . . . . . . . . . . . . . . .	5−12
5−10 ExCA I/O Window Control Register Description . . . . . . . . . . . . . . . . . . . . . .	5−13
5−11 ExCA Memory Windows 0−4 Start-Address High-Byte
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5−17
5−12 ExCA Memory Windows 0−4 End-Address High-Byte
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5−19
5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5−21
5−14 ExCA Card Detect and General Control Register Description . . . . . . . . . .	5−22
5−15 ExCA Global Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .	5−23
6−1 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6−1
6−2 Socket Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6−2
6−3 Socket Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6−3
6−4 Socket Present State Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . .	6−4

x

6−5 Socket Force Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6−6
6−6 Socket Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6−7
6−7 Socket Power Management Register Description . . . . . . . . . . . . . . . . . . . . .	6−8
7−1 Function 2 Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7−1
7−2 Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7−2
7−3 Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7−3
7−4 Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . . .	7−4
7−5 Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7−5
7−6 Power-Management Capabilities Register Description . . . . . . . . . . . . . . . . .	7−9
7−7 Power-Management Control/Status Register Description . . . . . . . . . . . . . . .	7−10
8−1 PC Card Address Setup Time, t su(A), 8-Bit and 16-Bit PCI Cycles . . . . . . .	8−7
8−2 PC Card Command Active Time, t c(A), 8-Bit PCI Cycles . . . . . . . . . . . . . . . .	8−7
8−3 PC Card Command Active Time, t c(A), 16-Bit PCI Cycles . . . . . . . . . . . . . .	8−7
8−4 PC Card Address Hold Time, t h(A), 8-Bit and 16-Bit PCI Cycles . . . . . . . . .	8−7

xi

xii

1 Introduction

1.1 Description

The Texas Instruments PCI1620 is an integrated dual-socket PC Card controller, FlashMedia controller (SmartMedia Card, MultiMediaCard, SD Card, Memory Stick card) and Smart Card controller.

The PCI1620 UltraMedia controller is a three-function PCI device compliant with PCI Local Bus Specification 2.2. Functions 0 and 1 provide two independent PC Card socket controllers compliant with PC Card Standard 8.0. Function 2 is the interface to load the PCI1620 program RAM with firmware. The PCI1620 provides features that make it ideal for bridging between the PCI bus and PC Cards, and supports any combination of 16-bit, CardBus, and UltraMedia PC Cards in the two sockets, powered at 5 V, 3.3 V, or 1.8 V as required.

UltraMedia cards that comply with the latest PCMCIA standard provide for very low-cost flash media and Smart Card adapters, because the control logic is integrated into the PCI1620. The PCI1620 supports a passive 4-in-1 adapter, as well as active PC Card-style Flash media and Smart Card adapters.

No PCMCIA card or socket service software changes are required to move systems from an existing CardBus socket controller to the PCI1620. The FlashMedia UltraMedia applications use existing host ATA drivers, and Texas Instruments provides a qualified Smart Card driver for UltraMedia-based Smart Card adapters. The PCI1620 is register compatible with the Intel 82365SL–DF ExCA controller and implements the host interface defined in the PC Card Standard. The PCI1620 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and the pipeline architecture provide a high performance level with sustained bursting. The PCI1620 can be programmed to accept posted writes to improve bus utilization.

Various implementation-specific functions and general-purpose inputs and outputs are provided through seven multifunction terminals. These terminals present a system with options for PCI LOCK, serial and parallel interrupts, PC Card activity indicator LEDs, and other platform-specific signals. ACPI-compliant general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs.

The PCI1620 is compliant with PCI Bus Power Management Interface Specification 1.1, and provides several low-power modes, which enable the host power system to further reduce power consumption. The PCI1620 also has a three-terminal serial interface compatible with both the TI TPS2226 and TPS2228 power switches.

1.2 Features

The PCI1620 supports the following features:

•PC Card Standard 8.0 compliant

•PCI Bus Power Management Interface Specification 1.1 compliant

•Advanced Configuration and Power Interface Specification 1.0 compliant

•PCI Local Bus Specification Revision 2.2 compliant

•PC 98/99 compliant

•Has integrated voltage regulator to use 1.8-V core voltage

•Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges

•Advanced filtering on card detect lines provides 90 microseconds of noise immunity.

•Programmable D3 status terminal

•1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core VCC

•Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

•Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus cards

•Supports two PC Card or CardBus slots with hot insertion and removal

1−1

•Uses serial interface to TI TPS2226 and TI TPS2228 dual power switch

•Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus bus

•Supports serialized IRQ with PCI interrupts

•13 programmable multifunction terminals

•Interrupt modes supported: serial ISA/serial PCI, serial ISA/parallel PCI, parallel PCI only

•Serial EEPROM interface for loading subsystem ID and subsystem vendor ID

•Supports external zoomed video

•Dedicated terminal for PCI CLKRUN

•Four general-purpose event registers

•Multifunction PCI device with separate configuration space for each socket

•Five PCI memory windows and two I/O windows available to each 16-bit PC Card socket

•Two I/O windows and two memory windows available to each CardBus socket

•ExCA-compatible registers are mapped in memory or I/O space

•Intel 82365SL–DF register compatible

•Supports ring indicate, suspend, and PCI clock run

•Advanced submicron, low-power CMOS technology

•Provides VGA/palette memory and I/O, and subtractive decoding options

•LED activity terminals

•Supports PCI bus lock (LOCK)

1.3Related Documents

•PC Card Controller Device Class Power Management Reference Specification

•PC Card Standard release 7

•PCI Local Bus Specification revision 2.2

•PCI to PCMCIA CardBus Bridge Register Description (Yenta), revision 2.1

•Texas Instruments TPS2226 and TPS2228 product data sheets

•SmartMedia Specifications, Issued 5/19/99

•MultiMediaCard Specification Version 2.2

•Multimedia Host Specification Version 3.7, Sandisk

•SD Memory Card Specifications, SD Group, 2000.

•Memory Stick Format Specification, Sony

•Memory Stick I/F Specification − Helen/Helious, TI Wireless Japan, Feb. 2000.

•ISO Standards for Identification Cards ISO/IEC 7816

•3Soft M8052 MegaMacro Design Specification

•ANSI AT Attachment (ATA) Specification for Disk Drives x3.221−1994

1.4Trademarks

Intel is a trademark of Intel Corporation.

MegaMacro is a trademark of MEJ Electronics Ltd., UK.

Memory Stick is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.

MicroStar BGA and UltraMedia are trademarks of Texas Instruments.

SmartMedia is a trademark of Kabushiki Kaisha Toshiba DBA Toshiba Corporation, Japan. SmartSocket is a trademark of ControlNet, Incorporated.

Other trademarks are the property of their respective owners.

1−2

1.5 Terms and Definitions

Terms and definitions used in this document are given in Table 1−1.

	Table 1−1. Terms and Definitions
TERM	DEFINITIONS
ATA	AT (advanced technology, as in PC AT) attachment interface
ATA driver	An existing host software component that loads when a SmartMedia adapter and card is inserted into a PC Card
	socket. This driver is logically attached to a predefined CIS provided by the PCI1620 when the adapter and media
	are both inserted.
CIS	Card information structure. Tuple list defined by the PC Card standard to communicate card information to the host
	computer
CSR	Control and status register
Flash Media	SmartMedia, Memory Stick, or SD Flash operating in an ATA compatible mode
Function 2 firmware loader	A hardware element of the PCI1620 that provides a software interface to the TI firmware loader driver to load the
	program RAM with firmware
ISO/IEC 7816	The Smart Card standard
Magic Gate	A security technology for Memory Stick promoted and licensed by Sony
Memory Stick	A small-form-factor flash interface that is defined, promoted, and licensed by Sony
MMC	MultiMediaCard. Specified by the MMC Association, and scope is encompassed by the SD Flash specification.
OHCI	Open host controller interface
PCMCIA	Personal Computer Memory Card International Association. Standards body that governs the PC Card standards
RSVD	Reserved for future use
SD Flash	Secure Digital Flash. Standard governed by the SD Association
Smart Card	The name applied to ID cards containing integrated circuits, as defined by ISO/IEC 7816-1
SmartMedia	Also known as SSFDC, defined by Toshiba and governed by SSFDC Forum
SPI	Serial peripheral interface, a general-purpose synchronous serial interface. For more information, see the
	Multimedia Card System Specification, version 2.2.
SSFDC	Solid State Floppy Disk Card. The SSFDC Forum specifies SmartMedia
TI firmware loader driver	A qualified software component provided by Texas Instruments that loads the firmware into the PCI1620 on power
	up and initialization.
TI Smart Card driver	A qualified software component provided by Texas Instruments that loads when an UltraMedia-based Smart Card
	adapter is inserted into a PC Card slot. This driver is logically attached to a CIS provided by the PCI1620 when the
	adapter is inserted.
TI SmartSocket driver	A qualified software component provided by Texas Instruments that loads when an unsupported UltraMedia-based
	card is inserted into a PC Card slot. This driver serves to give the user a message that the inserted card is not
	supported.
UART	Universal asynchronous receiver and transmitter
UltraMedia	De facto industry standard promoted by Texas Instruments that integrates CardBus, Smart Card, Memory Stick,
	MultiMediaCard/Secure Digital and SmartMedia functionality into one controller.

1.6 Ordering Information

ORDERING NUMBER	NAME	VOLTAGE	PACKAGE
PCI1620	PC Card, Cardbus card, Flash Media and	3.3-V, 5-V tolerant I/Os	209-terminal GHK, 208-terminal PDV
	Smart Card controller		packages

1−3

1−4

2 Terminal Descriptions

The PCI1620 is available in a 209-terminal MicroStar BGA package (GHK), and in a 208-terminal plastic quad flatpack package (PDV).

2.1 Terminal Assignments for PCI1620

Figure 2−1 shows the terminal layout for the 209-terminal MicroStar BGA package (GHK). Figure 2−2 shows the terminal assignments for the 208-terminal quad flatpack (PDV) package.

BOTTOM VIEW

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1	3	5	7	9		11	13	15	17	19
2		4	6	8	10	12	14		16	18

Figure 2−1. PCI1620 GHK Terminal Diagram

2−1

PDV LOW-PROFILE QUAD FLAT PACKAGE (LQFP)

TOP VIEW

																					MFUNC0		DATA		CLOCK			LATCH	SPKROUT		CAD31//AA D10		RSVD//AA D2		CAD30//AA D9		CAD29//AA D1		GND		CAD28//AA D8		CAD27//AA D0			CCD2//AA CD2	V				CCLKRUN//AA WP(IOIS16)		CSTSCHG//AA BVD1(STSCHG/RI)		CAUDIO//AA BVD2(SPKR)		CSERR//AA WAIT		CINT//AA READY(IREQ)		CVS1//AA VS1	CAD26//AA A0		CAD25//AA A1		CAD24//AA A2		V			CC/BE3//AA REG	CAD23//AA A3			CREQ//AA INPACK	CAD22//AA A4			OUTVR		CAD21//AA A5		CRST//AA RESET	CAD20//AA A6			CVS2//AA VS2		CAD19//AA A25	CAD18//AA A7		CAD17//AA A24			CC/BE2//AA A12		CFRAME//AA A23	V				CIRDY//AA A15		CTRDY//AA A22		CCLK//AA A16	V				CDEVSEL//AA A21		CGNT//AA WE		CSTOP//AA A20	GND				CPERR//AA A14		CBLOCK//AA A19		CPAR//AA A13		RSVD//AA A18		CC/BE1//AA A8
																																																CC																					CC																														CC									CCA
																				156			155		154		153		152		151		150		149		148		147		146		145		144		143				142	141		140		139		138		137		136		135		134		133		132		131		130		129		128		127		126		125		124		123		122		121		120		119		118			117		116		115		114			113		112		111		110			109		108		107		106		105
		MFUNC1																		157																																																																																																											104						A_CAD16//A_A17
																				158																																																																																																											103						A_CAD14//A_A9
		SUSPEND
		MFUNC2																		159																																																																																																											102						A_CAD15//A_
																																																																																																																																																	IOWR
		MFUNC3																		160																																																																																																											101						A_CAD13//A_
																																																																																																																																																	IORD
		MFUNC4																		161																																																																																																											100						A_CAD12//A_A11
		MFUNC5																		162																																																																																																											99						A_CAD11//A_
																																																																																																																																																OE
MFUNC6/CLKRUN																				163																																																																																																											98						A_CAD10//A_												CE2
																				164																																																																																																											97						A_CAD9//A_A10
					C/BE3
																				165																																																																																																											96
	RI_OUT/PME																																																																																																																																				A_CC/BE0//A_CE1
								GND												166																																																																																																											95						GND
							AD25													167																																																																																																											94						A_CAD8//A_D15
																				168																																																																																																											93						A_CAD7//A_D7
							PRST
																				169																																																																																																											92						A_RSVD//A_D14
										GNT
																				170																																																																																																											91						VCC
									REQ
							AD31													171																																																																																																											90						A_CAD5//A_D6
							AD30													172																																																																																																											89						A_CAD6//A_D13
							AD11													173																																																																																																											88						A_CAD3//A_D5
												VCC								174																																																																																																											87						A_CAD4//A_D12
							AD29													175																																																																																																											86						A_CAD1//A_D4
							AD28													176																																																																																																											85						A_CAD2//A_D11
																				177																																																																																																											84						A_CAD0//A_D3
							GRST
							AD27													178																																																																																																											83						A_
																																																																																																																																						CCD1//A_CD1
							AD26													179																																																																																																											82						B_CAD31//B_D10
							VCCP													180																																																																																																											81						CLK48
							AD24													181																																																																																																											80						B_RSVD//B_D2
							PCLK													182																																																		PCI1620																																																									79						B_CAD30//B_D9
					IDSEL															183																																																																																																											78						B_CAD29//B_D1
							AD23													184																																																																																																											77						B_CAD28//B_D8
								GND												185																																																																																																											76						B_CAD27//B_D0
							AD22													186																																																																																																											75						B_
																																																																																																																																						CCD2//B_CD2
							AD21													187																																																																																																											74						B_
																																																																																																																																						CCLKRUN//B												_WP(IOIS16)
							AD20													188																																																																																																											73
																																																																																																																																					B_CSTSCHG//B_BVD1(STSCHG/RI)
							AD19													189																																																																																																											72
																																																																																																																																					B_CAUDIO//B_BVD2(SPKR)
							AD18													190																																																																																																											71						B_
																																																																																																																																						CSERR//B_WAIT
							AD17													191																																																																																																											70						VCC
							AD16													192																																																																																																											69						B_
																																																																																																																																						CINT//B_READY(IREQ)
																				193																																																																																																											68						B_CVS1//B_
					C/BE2																																																																																																																																								VS1
																				194																																																																																																											67						B_CAD26//B_A0
					FRAME
												VCC								195																																																																																																											66						B_CAD25//B_A1
								IRDY												196																																																																																																											65						B_CAD24//B_A2
																				197																																																																																																											64
							TRDY																																																																																																																														B_CC/BE3//B_REG
																				198																																																																																																											63						B_CAD23//B_A3
				DEVSEL
								GND												199																																																																																																											62						GND
																				200																																																																																																											61						B_
							STOP																																																																																																																															CREQ//B_INPACK
																				201																																																																																																											60						B_CAD22//B_A4
							PERR
																				202																																																																																																											59						B_CAD21//B_A5
						SERR
										PAR										203																																																																																																											58						B_
																																																																																																																																						CRST//B_RESET
																				204																																																																																																											57						B_CAD20//B_A6
					C/BE1
							AD15													205																																																																																																											56						B_CVS2//B_
																																																																																																																																													VS2
							AD14													206																																																																																																											55						B_CAD19//B_A25
							AD13													207																																																																																																											54						B_CAD18//B_A7
							AD12													208																			10				12		13		14				15	16		17		18		19		20		21		22		23		24		25		26		27		28		29		30		31		32		33		34		35		36		37		38		39							42		43			44		45		46		47			48		49				51		53						B_CAD17//B_A24
																				1			2		3		4		5		6		7		8		9				11																																																												40		41																				50				52
																					AD10		AD9		AD8			C/BE0	AD7		GND		AD6		AD5		AD4		AD3		AD2		AD1			AD0	V				CCD1//BB_ _CD1		CAD0//BB_ _D3		CAD2//BB_ _D11		CAD1//BB_ _D4		CAD4//BB_ _D12		CAD3//BB_ _D5	CAD6//BB_ _D13		CAD5//BB_ _D6		RSVD//BB_ _D14		GND			CAD7//BB_ _D7	CAD8//BB_ _D15			CC/BE0//BB_ _CE1	CAD9//BB_ _A10			VR_EN		CAD10//BB_ _CE2		CAD11//BB_ _OE	CAD12//BB_ _A11			CAD13//BB_ _IORD		CAD15//BB_ _IOWR	CAD14//BB_ _A9		CAD16//BB_ _A17			CC/BE1//BB_ _A8		RSVD//BB_ _A18	V				CPAR//BB_ _A13		CBLOCK//BB_ _A19		CPERR//BB_ _A14	GND				CSTOP//BB_ _A20		BCGNT//B_ _WE		_CDEVSEL//BB _A21	V				_CCLK//BB _A16		_CTRDY//BB _A22		_CIRDY//BB _A15		_CFRAME//BB _A23		_CC/BE2//BB _A12
																																																CC																																																			CC																		CCB

Figure 2−2. PCI1620 PDV Terminal Diagram

The following tables show the correspondence between signal names and their respective terminal assignments. In Table 2−1, PDV -package entries are listed in order by terminal number, with signal names for CardBus PC Cards and 16-bit PC Cards. In Table 2−2, GHK-package entries are listed in alphanumeric order by terminal number, with signal

2−2

names for CardBus PC Cards and 16-bit PC Cards. In Table 2−3, entries are listed in alphanumeric order by CardBus PC Card signal names, with corresponding terminal numbers. In Table 2−4, entries are listed in alphanumeric order by 16-bit PC Card signal names, with corresponding terminal numbers.

Table 2−1. Signal Names by PDV Terminal Number

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

NO.

CardBus PC Card

16-Bit PC Card

NO.

CardBus PC Card

16-Bit PC Card

1

AD10

AD10

41

B_

CBLOCK

B_A19

2

AD9

AD9

42

B_

CPERR

B_A14

3

AD8

AD8

43

GND

GND

4

44

B_A20

C/BE0

C/BE0

B_CSTOP

5

AD7

AD7

45

B_

CGNT

B_

WE

6

GND

GND

46

B_

CDEVSEL

B_A21

7

AD6

AD6

47

VCCB

VCCB

8

AD5

AD5

48

B_CCLK

B_A16

9

AD4

AD4

49

B_

CTRDY

B_A22

10

AD3

AD3

50

B_

CIRDY

B_A15

11

AD2

AD2

51

B_

CFRAME

B_A23

12

AD1

AD1

52

B_A12

B_CC/BE2

13

AD0

AD0

53

B_CAD17

B_A24

14

VCC

VCC

54

B_CAD18

B_A7

15

B_

B_

55

B_CAD19

B_A25

CCD1

CD1

16

B_CAD0

B_D3

56

B_CVS2

B_

VS2

17

B_CAD2

B_D11

57

B_CAD20

B_A6

18

B_CAD1

B_D4

58

B_

CRST

B_RESET

19

B_CAD4

B_D12

59

B_CAD21

B_A5

20

B_CAD3

B_D5

60

B_CAD22

B_A4

21

B_CAD6

B_D13

61

B_

CREQ

B_

INPACK

22

B_CAD5

B_D6

62

GND

GND

23

B_RSVD

B_D14

63

B_CAD23

B_A3

24

GND

GND

64

B_

B_CC/BE3

REG

25

B_CAD7

B_D7

65

B_CAD24

B_A2

26

B_CAD8

B_D15

66

B_CAD25

B_A1

27

B_

67

B_CAD26

B_A0

B_CC/BE0

CE1

28

B_CAD9

B_A10

68

B_CVS1

B_

VS1

29

69

B_

VR_EN

VR_EN

CINT

B_READY(IREQ)

30

B_CAD10

B_

70

VCC

VCC

CE2

31

B_CAD11

B_

71

B_

B_

OE

CSERR

WAIT

32

B_CAD12

B_A11

72

B_CAUDIO

B_BVD2(SPKR)

33

B_CAD13

B_

73

B_CSTSCHG

IORD

B_BVD1(STSCHG/RI)

34

B_CAD15

B_

74

B_

IOWR

CCLKRUN

B_WP(IOIS16)

35

B_CAD14

B_A9

75

B_

CCD2

B_

CD2

36

B_CAD16

B_A17

76

B_CAD27

B_D0

37

B_A8

77

B_CAD28

B_D8

B_CC/BE1

38

B_RSVD

B_A18

78

B_CAD29

B_D1

39

VCC

VCC

79

B_CAD30

B_D9

40

B_CPAR

B_A13

80

B_RSVD

B_D2

2−3

Table 2−1. Signal Names by PDV Terminal Number (Continued)

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

NO.

CardBus PC Card

16-Bit PC Card

NO.

CardBus PC Card

16-Bit PC Card

81

CLK48

CLK48

123

A_CAD19

A_A25

82

B_CAD31

B_D10

124

A_CVS2

A_

VS2

83

A_

A_

125

A_CAD20

A_A6

CCD1

CD1

84

A_CAD0

A_D3

126

A_

CRST

A_RESET

85

A_CAD2

A_D11

127

A_CAD21

A_A5

86

A_CAD1

A_D4

128

VR_OUT

VR_OUT

87

A_CAD4

A_D12

129

A_CAD22

A_A4

88

A_CAD3

A_D5

130

A_

CREQ

A_

INPACK

89

A_CAD6

A_D13

131

A_CAD23

A_A3

90

A_CAD5

A_D6

132

A_

A_CC/BE3

REG

91

VCC

VCC

133

VCC

VCC

92

A_RSVD

A_D14

134

A_CAD24

A_A2

93

A_CAD7

A_D7

135

A_CAD25

A_A1

94

A_CAD8

A_D15

136

A_CAD26

A_A0

95

GND

GND

137

A_CVS1

A_

VS1

96

A_

138

A_

A_CC/BE0

CE1

CINT

A_READY(IREQ)

97

A_CAD9

A_A10

139

A_

CSERR

A_

WAIT

98

A_CAD10

A_

140

A_CAUDIO

CE2

A_BVD2(SPKR)

99

A_CAD11

A_

141

A_CSTSCHG

OE

A_BVD1(STSCHG/RI)

100

A_CAD12

A_A11

142

A_

CCLKRUN

A_WP(IOIS16)

101

A_CAD13

A_

143

VCC

VCC

IORD

102

A_CAD15

A_

144

A_

A_

IOWR

CCD2

CD2

103

A_CAD14

A_A9

145

A_CAD27

A_D0

104

A_CAD16

A_A17

146

A_CAD28

A_D8

105

A_A8

147

GND

GND

A_CC/BE1

106

A_RSVD

A_A18

148

A_CAD29

A_D1

107

A_CPAR

A_A13

149

A_CAD30

A_D9

108

A_

A_A19

150

A_RSVD

A_D2

CBLOCK

109

A_

A_A14

151

A_CAD31

A_D10

CPERR

110

GND

GND

152

SPKROUT

SPKROUT

111

A_

A_A20

153

LATCH

LATCH

CSTOP

112

A_

A_

154

CLOCK

CLOCK

CGNT

WE

113

A_

A_A21

155

DATA

DATA

CDEVSEL

114

VCCA

VCCA

156

MFUNC0

MFUNC0

115

A_CCLK

A_A16

157

MFUNC1

MFUNC1

116

A_

A_A22

158

CTRDY

SUSPEND

SUSPEND

117

A_

A_A15

159

MFUNC2

MFUNC2

CIRDY

118

VCC

VCC

160

MFUNC3

MFUNC3

119

A_

A_A23

161

MFUNC4

MFUNC4

CFRAME

120

A_A12

162

MFUNC5

MFUNC5

A_CC/BE2

121

A_CAD17

A_A24

163

MFUNC6/CLKRUN

MFUNC6/CLKRUN

122

A_CAD18

A_A7

164

C/BE3

C/BE3

2−4

Table 2−1. Signal Names by PDV Terminal Number (Continued)

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

NO.

CardBus PC Card

16-Bit PC Card

NO.

CardBus PC Card

16-Bit PC Card

165

187

AD21

AD21

RI_OUT/PME

RI_OUT/PME

166

GND

GND

188

AD20

AD20

167

AD25

AD25

189

AD19

AD19

168

190

AD18

AD18

PRST

PRST

169

191

AD17

AD17

GNT

GNT

170

192

AD16

AD16

REQ

REQ

171

AD31

AD31

193

C/BE2

C/BE2

172

AD30

AD30

194

FRAME

FRAME

173

AD11

AD11

195

VCC

VCC

174

VCC

VCC

196

IRDY

IRDY

175

AD29

AD29

197

TRDY

TRDY

176

AD28

AD28

198

DEVSEL

DEVSEL

177

199

GND

GND

GRST

GRST

178

AD27

AD27

200

STOP

STOP

179

AD26

AD26

201

PERR

PERR

180

VCCP

VCCP

202

SERR

SERR

181

AD24

AD24

203

PAR

PAR

182

PCLK

PCLK

204

C/BE1

C/BE1

183

IDSEL

IDSEL

205

AD15

AD15

184

AD23

AD23

206

AD14

AD14

185

GND

GND

207

AD13

AD13

186

AD22

AD22

208

AD12

AD12

Table 2−2. Signal Names by GHK Terminal Number

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

NO.

NO.

CardBus PC Card

16-Bit PC Card

CardBus PC Card

16-Bit PC Card

A04

AD12

AD12

B12

AD11

AD11

A05

PAR

PAR

B13

GNT

GNT

A06

GND

GND

B14

C/BE3

C/BE3

A07

VCC

VCC

B15

MFUNC4

MFUNC4

A08

AD18

AD18

C05

AD13

AD13

A09

GND

GND

C06

SERR

SERR

A10

VCCP

VCCP

C07

TRDY

TRDY

A11

AD29

AD29

C08

AD16

AD16

A12

VCC

VCC

C09

AD21

AD21

A13

C10

PCLK

PCLK

REQ

REQ

A14

GND

GND

C11

GRST

GRST

A15

MFUNC5

MFUNC5

C12

AD30

AD30

A16

MFUNC1

MFUNC1

C13

PRST

PRST

B05

AD15

AD15

C14

MFUNC6/CLKRUN

MFUNC6/CLKRUN

B06

C15

STOP

STOP

SUSPEND

SUSPEND

B07

D01

AD10

AD10

IRDY

IRDY

B08

AD17

AD17

D19

MFUNC0

MFUNC0

B09

AD22

AD22

E01

GND

GND

B10

AD24

AD24

E02

AD7

AD7

B11

AD28

AD28

E03

AD9

AD9

2−5

Table 2−2. Signal Names by GHK Terminal Number (Continued)

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

NO.

NO.

CardBus PC Card

16-Bit PC Card

CardBus PC Card

16-Bit PC Card

E05

NC

NC

H05

B_

B_

CCD1

CD1

E06

AD14

AD14

H06

AD2

AD2

E07

H14

A_CSTSCHG

PERR

PERR

A_BVD1(STSCHG/RI)

E08

H15

A_

FRAME

FRAME

CCLKRUN

A_WP(IOIS16)

E09

AD19

AD19

H17

A_CAUDIO

A_BVD2(SPKR)

E10

IDSEL

IDSEL

H18

A_

A_

CSERR

WAIT

E11

AD27

AD27

H19

A_

CINT

A_READY(IREQ)

E12

AD31

AD31

J01

B_CAD4

B_D12

E13

J02

B_CAD3

B_D5

RI_OUT/PME

RI_OUT/PME

E14

MFUNC2

MFUNC2

J03

B_CAD6

B_D13

E17

DATA

DATA

J05

B_CAD5

B_D6

E18

LATCH

LATCH

J06

B_RSVD

B_D14

E19

A_CAD31

A_D10

J14

A_CAD26

A_A0

F01

AD3

AD3

J15

A_CVS1

A_

VS1

F02

AD5

AD5

J17

A_CAD25

A_A1

F03

AD6

AD6

J18

A_CAD24

A_A2

F05

AD8

AD8

J19

VCC

VCC

F06

K01

GND

GND

C/BE1

C/BE1

F07

K02

B_CAD7

B_D7

DEVSEL

DEVSEL

F08

K03

B_CAD8

B_D15

C/BE2

C/BE2

F09

AD20

AD20

K05

B_

B_CC/BE0

CE1

F10

AD23

AD23

K06

B_CAD9

B_A10

F11

AD26

AD26

K14

A_

A_CC/BE3

REG

F12

AD25

AD25

K15

A_CAD23

A_A3

F13

MFUNC3

MFUNC3

K17

A_

A_

CREQ

INPACK

F14

SPKROUT

SPKROUT

K18

A_CAD22

A_A4

F15

CLOCK

CLOCK

K19

VR_OUT

VR_OUT

F17

A_RSVD

A_D2

L01

VR_EN

VR_EN

F18

A_CAD29

A_D1

L02

B_CAD10

B_

CE2

F19

GND

GND

L03

B_CAD11

B_

OE

G01

VCC

VCC

L05

B_CAD13

B_

IORD

G02

AD0

AD0

L06

B_CAD12

B_A11

G03

AD1

AD1

L14

A_CAD21

A_A5

G05

AD4

AD4

L15

A_

A_RESET

CRST

G06

L17

A_CAD20

A_A6

C/BE0

C/BE0

G14

A_CAD28

A_D8

L18

A_CVS2

A_

VS2

G15

A_CAD30

A_D9

L19

A_CAD19

A_A25

G17

A_CAD27

A_D0

M01

B_CAD15

B_

IOWR

G18

A_

A_

M02

B_CAD14

B_A9

CCD2

CD2

G19

VCC

VCC

M03

B_CAD16

B_A17

H01

B_CAD1

B_D4

M05

B_RSVD

B_A18

H02

B_CAD2

B_D11

M06

B_A8

B_CC/BE1

H03

B_CAD0

B_D3

M14

A_CCLK

A_A16

2−6

Table 2−2. Signal Names by GHK Terminal Number (Continued)

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

NO.

NO.

CardBus PC Card

16-Bit PC Card

CardBus PC Card

16-Bit PC Card

M15

A_

A_A23

R14

A_CAD15

A_

CFRAME

IOWR

M17

A_A12

R17

A_RSVD

A_A18

A_CC/BE2

M18

A_CAD17

A_A24

R18

A_

A_A14

CPERR

M19

A_CAD18

A_A7

R19

GND

GND

N01

VCC

VCC

T01

B_A12

B_CC/BE2

N02

B_CPAR

B_A13

T19

A_A8

A_CC/BE1

N03

B_

B_A19

U05

B_CAD18

B_A7

CBLOCK

N05

B_

B_

U06

B_CAD21

B_A5

CGNT

WE

N06

B_

B_A14

U07

B_

CPERR

B_CC/BE3

REG

N14

A_

A_A19

U08

B_CVS1

B_

CBLOCK

VS1

N15

A_

A_A21

U09

B_CSTSCHG

CDEVSEL

B_BVD1(STSCHG/RI)

N17

A_

A_A22

U10

B_CAD29

B_D1

CTRDY

N18

A_

A_A15

U11

A_

A_

CIRDY

CCD1

CD1

N19

VCC

VCC

U12

A_CAD3

A_D5

P01

GND

GND

U13

A_CAD7

A_D7

P02

B_

B_A20

U14

A_CAD10

A_

CSTOP

CE2

P03

B_

B_A21

U15

A_CAD14

A_A9

CDEVSEL

P05

B_

B_A15

V05

B_CAD20

B_A6

CIRDY

P06

B_CCLK

B_A16

V06

B_CAD22

B_A4

P07

B_CVS2

B_

V07

B_CAD24

B_A2

VS2

P08

B_CAD23

B_A3

V08

B_

CINT

B_READY(IREQ)

P09

B_

B_

V09

B_CAUDIO

CCD2

CD2

B_BVD2(SPKR)

P10

B_RSVD

B_D2

V10

B_CAD28

B_D8

P11

A_CAD0

A_D3

V11

B_CAD31

B_D10

P12

A_CAD6

A_D13

V12

A_CAD4

A_D12

P13

A_CAD8

A_D15

V13

A_RSVD

A_D14

P14

A_CAD12

A_A11

V14

A_

A_CC/BE0

CE1

P15

A_CPAR

A_A13

V15

A_CAD13

A_

IORD

P17

A_

A_A20

W04

B_CAD17

B_A24

CSTOP

P18

A_

A_

W05

B_

B_RESET

CGNT

WE

CRST

P19

VCCA

VCCA

W06

GND

GND

R01

VCCB

VCCB

W07

B_CAD25

B_A1

R02

B_

B_A22

W08

VCC

VCC

CTRDY

R03

B_

B_A23

W09

B_

B_

CFRAME

CSERR

WAIT

R06

B_CAD19

B_A25

W10

B_CAD27

B_D0

R07

B_

B_

W11

CLK48

CLK48

CREQ

INPACK

R08

B_CAD26

B_A0

W12

A_CAD1

A_D4

R09

B_

W13

VCC

VCC

CCLKRUN

B_WP(IOIS16)

R10

B_CAD30

B_D9

W14

GND

GND

R11

A_CAD2

A_D11

W15

A_CAD11

A_

OE

R12

A_CAD5

A_D6

W16

A_CAD16

A_A17

R13

A_CAD9

A_A10

2−7

Table 2−3. CardBus PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

TERM NO.

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM NO.

PDV

GHK

PDV

GHK

PDV

GHK

PDV

GHK

A_CAD0

84

P11

105

T19

AD10

1

D01

B_CAD13

33

L05

A_CC/BE1

A_CAD1

86

W12

120

M17

AD11

173

B12

B_CAD14

35

M02

A_CC/BE2

A_CAD2

85

R11

132

K14

AD12

208

A04

B_CAD15

34

M01

A_CC/BE3

A_CAD3

88

U12

A_

83

U11

AD13

207

C05

B_CAD16

36

M03

CCD1

A_CAD4

87

V12

A_

144

G18

AD14

206

E06

B_CAD17

53

W04

CCD2

A_CAD5

90

R12

A_CCLK

115

M14

AD15

205

B05

B_CAD18

54

U05

A_CAD6

89

P12

A_

142

H15

AD16

192

C08

B_CAD19

55

R06

CCLKRUN

A_CAD7

93

U13

A_

113

N15

AD17

191

B08

B_CAD20

57

V05

CDEVSEL

A_CAD8

94

P13

A_

119

M15

AD18

190

A08

B_CAD21

59

U06

CFRAME

A_CAD9

97

R13

A_

112

P18

AD19

189

E09

B_CAD22

60

V06

CGNT

A_CAD10

98

U14

A_

138

H19

AD20

188

F09

B_CAD23

63

P08

CINT

A_CAD11

99

W15

A_

117

N18

AD21

187

C09

B_CAD24

65

V07

CIRDY

A_CAD12

100

P14

A_CPAR

107

P15

AD22

186

B09

B_CAD25

66

W07

A_CAD13

101

V15

A_

109

R18

AD23

184

F10

B_CAD26

67

R08

CPERR

A_CAD14

103

U15

A_

130

K17

AD24

181

B10

B_CAD27

76

W10

CREQ

A_CAD15

102

R14

A_

126

L15

AD25

167

F12

B_CAD28

77

V10

CRST

A_CAD16

104

W16

A_

139

H18

AD26

179

F11

B_CAD29

78

U10

CSERR

A_CAD17

121

M18

A_

111

P17

AD27

178

E11

B_CAD30

79

R10

CSTOP

A_CAD18

122

M19

A_CSTSCHG

141

H14

AD28

176

B11

B_CAD31

82

V11

A_CAD19

123

L19

A_

116

N17

AD29

175

A11

B_CAUDIO

72

V09

CTRDY

A_CAD20

125

L17

A_CVS1

137

J15

AD30

172

C12

B_

CBLOCK

41

N03

A_CAD21

127

L14

A_CVS2

124

L18

AD31

171

E12

27

K05

B_CC/BE0

A_CAD22

129

K18

A_RSVD

106

R17

B_CAD0

16

H03

37

M06

B_CC/BE1

A_CAD23

131

K15

A_RSVD

92

V13

B_CAD1

18

H01

52

T01

B_CC/BE2

A_CAD24

134

J18

A_RSVD

150

F17

B_CAD2

17

H02

64

U07

B_CC/BE3

A_CAD25

135

J17

AD0

13

G02

B_CAD3

20

J02

B_

CCD1

15

H05

A_CAD26

136

J14

AD1

12

G03

B_CAD4

19

J01

B_

CCD2

75

P09

A_CAD27

145

G17

AD2

11

H06

B_CAD5

22

J05

B_CCLK

48

P06

A_CAD28

146

G14

AD3

10

F01

B_CAD6

21

J03

B_

CCLKRUN

74

R09

A_CAD29

148

F18

AD4

9

G05

B_CAD7

25

K02

B_

CDEVSEL

46

P03

A_CAD30

149

G15

AD5

8

F02

B_CAD8

26

K03

B_

CFRAME

51

R03

A_CAD31

151

E19

AD6

7

F03

B_CAD9

28

K06

B_

CGNT

45

N05

A_CAUDIO

140

H17

AD7

5

E02

B_CAD10

30

L02

B_

CINT

69

V08

A_

108

N14

AD8

3

F05

B_CAD11

31

L03

B_

50

P05

CBLOCK

CIRDY

96

V14

AD9

2

E03

B_CAD12

32

L06

B_CPAR

40

N02

A_CC/BE0

2−8

Table 2−3. CardBus PC Card Signal Names Sorted Alphabetically (Continued)

SIGNAL NAME

TERM NO.

SIGNAL NAME

TERM NO.

PDV

GHK

PDV

GHK

B_

42

N06

LATCH

153

E18

CPERR

B_

61

R07

MFUNC0

156

D19

CREQ

B_

58

W05

MFUNC1

157

A16

CRST

B_

71

W09

MFUNC2

159

E14

CSERR

B_

44

P02

MFUNC3

160

F13

CSTOP

B_CSTSCHG

73

U09

MFUNC4

161

B15

B_

49

R02

MFUNC5

162

A15

CTRDY

B_CVS1

68

U08

163

C14

MFUNC6/CLKRUN

B_CVS2

56

P07

NC

—

E05

B_RSVD

23

J06

PAR

203

A05

B_RSVD

38

M05

PCLK

182

C10

B_RSVD

80

P10

201

E07

PERR

4

G06

168

C13

C/BE0

PRST

204

F06

170

A13

C/BE1

REQ

193

F08

165

E13

C/BE2

RI_OUT/PME

164

B14

202

C06

C/BE3

SERR

CLK48

81

W11

SPKROUT

152

F14

CLOCK

154

F15

200

B06

STOP

DATA

155

E17

158

C15

SUSPEND

198

F07

197

C07

DEVSEL

TRDY

194

E08

VCC

14

A07

FRAME

GND

6

A06

VCC

39

A12

GND

24

A09

VCC

70

G01

GND

43

A14

VCC

91

G19

GND

62

E01

VCC

118

J19

GND

95

K01

VCC

133

N01

GND

110

P01

VCC

143

N19

GND

147

R19

VCC

174

W08

GND

166

W06

VCC

195

W13

GND

185

F19

VCCA

114

P19

GND

199

W14

VCCB

47

R01

169

B13

VCCP

180

A10

GNT

177

C11

29

L01

GRST

VR_EN

IDSEL

183

E10

VR_OUT

128

K19

196

B07

IRDY

2−9

Table 2−4. 16-Bit PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM NO.

PDV

GHK

PDV

GHK

PDV

GHK

A_A0

136

J14

A_D10

151

E19

AD24

181

B10

A_A1

135

J17

A_D11

85

R11

AD25

167

F12

A_A2

134

J18

A_D12

87

V12

AD26

179

F11

A_A3

131

K15

A_D13

89

P12

AD27

178

E11

A_A4

129

K18

A_D14

92

V13

AD28

176

B11

A_A5

127

L14

A_D15

94

P13

AD29

175

A11

A_A6

125

L17

A_

INPACK

130

K17

AD30

172

C12

A_A7

122

M19

A_

IORD

101

V15

AD31

171

E12

A_A8

105

T19

A_

IOWR

102

R14

B_A0

67

R08

A_A9

103

U15

A_

OE

99

W15

B_A1

66

W07

A_A10

97

R13

138

H19

B_A2

65

V07

A_READY(IREQ)

A_A11

100

P14

A_

REG

132

K14

B_A3

63

P08

A_A12

120

M17

A_RESET

126

L15

B_A4

60

V06

A_A13

107

P15

A_

VS1

137

J15

B_A5

59

U06

A_A14

109

R18

A_

VS2

124

L18

B_A6

57

V05

A_A15

117

N18

A_

WAIT

139

H18

B_A7

54

U05

A_A16

115

M14

A_

WE

112

P18

B_A8

37

M06

A_A17

104

W16

142

H15

B_A9

35

M02

A_WP(IOIS16)

A_A18

106

R17

AD0

13

G02

B_A10

28

K06

A_A19

108

N14

AD1

12

G03

B_A11

32

L06

A_A20

111

P17

AD2

11

H06

B_A12

52

T01

A_A21

113

N15

AD3

10

F01

B_A13

40

N02

A_A22

116

N17

AD4

9

G05

B_A14

42

N06

A_A23

119

M15

AD5

8

F02

B_A15

50

P05

A_A24

121

M18

AD6

7

F03

B_A16

48

P06

A_A25

123

L19

AD7

5

E02

B_A17

36

M03

141

H14

AD8

3

F05

B_A18

38

M05

A_BVD1(STSCHG/RI)

140

H17

AD9

2

E03

B_A19

41

N03

A_BVD2(SPKR)

A_

83

U11

AD10

1

D01

B_A20

44

P02

CD1

A_

144

G18

AD11

173

B12

B_A21

46

P03

CD2

A_

96

V14

AD12

208

A04

B_A22

49

R02

CE1

A_

98

U14

AD13

207

C05

B_A23

51

R03

CE2

A_D0

145

G17

AD14

206

E06

B_A24

53

W04

A_D1

148

F18

AD15

205

B05

B_A25

55

R06

A_D2

150

F17

AD16

192

C08

73

U09

B_BVD1(STSCHG/RI)

A_D3

84

P11

AD17

191

B08

72

V09

B_BVD2(SPKR)

A_D4

86

W12

AD18

190

A08

B_

CD1

15

H05

A_D5

88

U12

AD19

189

E09

B_

CD2

75

P09

A_D6

90

R12

AD20

188

F09

B_

CE1

27

K05

A_D7

93

U13

AD21

187

C09

B_

CE2

30

L02

A_D8

146

G14

AD22

186

B09

B_D0

76

W10

A_D9

149

G15

AD23

184

F10

B_D1

78

U10

2−10

Table 2−4. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)

SIGNAL NAME

TERM NO.

SIGNAL NAME

TERM NO.

PDV

GHK

PDV

GHK

B_D2

80

P10

GND

147

R19

B_D3

16

H03

GND

166

W06

B_D4

18

H01

GND

199

W14

B_D5

20

J02

169

B13

GNT

B_D6

22

J05

177

C11

GRST

B_D7

25

K02

IDSEL

183

E10

B_D8

77

V10

196

B07

IRDY

B_D9

79

R10

LATCH

153

E18

B_D10

82

V11

MFUNC0

156

D19

B_D11

17

H02

MFUNC1

157

A16

B_D12

19

J01

MFUNC2

159

E14

B_D13

21

J03

MFUNC3/IRQSER

160

F13

B_D14

23

J06

MFUNC4

161

B15

B_D15

26

K03

MFUNC5

162

A15

B_

61

R07

163

C14

INPACK

MFUNC6/CLKRUN

B_

33

L05

NC

—

E05

IORD

B_

34

M01

PAR

203

A05

IOWR

B_

31

L03

PCLK

182

C10

OE

69

V08

201

E07

B_READY(IREQ)

PERR

B_

64

U07

168

C13

REG

PRST

B_RESET

58

W05

170

A13

REQ

B_

68

U08

165

E13

VS1

RI_OUT/PME

B_

56

P07

202

C06

VS2

SERR

B_

71

W09

SPKROUT

152

F14

WAIT

B_

45

N05

200

B06

WE

STOP

74

R09

158

C15

B_WP(IOIS16)

SUSPEND

4

G06

197

C07

C/BE0

TRDY

204

F06

VCC

14

A07

C/BE1

193

F08

VCC

39

A12

C/BE2

164

B14

VCC

70

G01

C/BE3

CLK48

185

W11

VCC

91

G19

CLOCK

154

F15

VCC

118

J19

DATA

155

E17

VCC

133

N01

198

F07

VCC

143

N19

DEVSEL

194

E08

VCC

174

W08

FRAME

GND

6

A06

VCC

195

W13

GND

24

A09

VCCA

114

P19

GND

43

A14

VCCB

47

R01

GND

62

E01

VCCP

180

A10

GND

81

F19

29

L01

VR_EN

GND

95

K01

VR_OUT

128

K19

GND

110

P01

2−11

The terminals are grouped in tables by functionality, such as PCI system function and power supply function, for quick reference (see Table 2−5 through Table 2−15). The terminal names and numbers are also listed for convenient reference.

Table 2−5. Power Supply Terminals

			TERMINAL
	NAME			NO.		I/O	DESCRIPTION
			PDV		GHK
	GND		6, 24, 43, 62,		A06, A09, A14,	−	Device ground terminals
			95, 110, 147,		E01, F19, K01,
			166, 185, 199		P01, R19, W06,
					W14
	VCC		14, 39, 70, 91,		A07, A12, G01,	−	3.3-V power terminals
			118, 133, 143,		G19, J19, N01,
			174, 195		N19, W08, W13
	VCCA		114		P19	−	PC Card A signaling rail power input; clamped per PC Card specification
	VCCB		47		R01	−	PC Card B signaling rail power input; clamped per PC Card specification
	VCCP		180		A10	−	PCI signaling clamp rail power input; clamped per PCI specification
			29		L01	I	Internal voltage regulator enable. Active-low
	VR_EN
	VR_OUT		128		K19	O	Internal voltage regulator output (1.8 V) for external bypass capacitor

					Table 2−6. PC Card Power Switch Terminals
TERMINAL
NAME	NO.			I/O	DESCRIPTION
	PDV		GHK
					Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults
					to an input, but can be changed to a PCI1620 output by using bit 27 (P2CCLK) in the system control register
					(PCI offset 80h, see Section 4.31). For use with the TPS222X, the maximum frequency of this signal is limited
CLOCK	154		F15	I/O	to 2 MHz. However, the PCI1620 requires a 16-KHz to 100-KHz frequency range. As an input, this terminal
					requires an external 32-kHz clock. If a system design defines this terminal as an output, then this terminal
					requires an external pulldown resistor. The frequency of the PCI1620 output CLOCK is derived from the
					internal ring oscillator (16 kHz typical).
DATA	155		E17	O	Power switch data. DATA is used to communicate socket power control information serially to the power
					switch.
					Power switch latch. LATCH is asserted by the PCI1620 to indicate to the power switch that the data on the
LATCH	153		E18	I/O	DATA line is valid. The LATCH terminal is also used to indicate the presence of an external EEPROM; when
					a pulldown resistor is implemented on this terminal, the MFUNC1 and MFUNC4 terminals provide the serial
					EEPROM SDA and SCL interface.

2−12

Table 2−7. PCI System Terminals

TERMINAL

NAME

NO.

I/O

DESCRIPTION

PDV

GHK

Global reset. When the global reset is asserted, the

GRST

signal causes the PCI1620 to place all output

buffers in a high-impedance state and reset all internal registers. When

GRST

is asserted, the device is

completely in its default state. For systems that require wake-up from D3, GRST normally is asserted only

during initial boot. PRST should be asserted during GRST and for resets subsequent to the initial GRST so

GRST

177

C11

I

that PME context is retained during the transition from D3 to D0. For systems that do not require wake-up

from D3, GRST should be tied to PRST.

mode is enabled together with

the device is protected from

the internal

When the

SUSPEND

GRST,

GRST;

registers are not reset, but all outputs are placed in a high-impedance state.

PCLK

182

C10

I

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the

rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted,

PRST

causes the PCI1620 to reset internal registers and

place all output buffers in a high-impedance state. When PRST is asserted, the device can generate the

PME

168

C13

I

signal only if it is enabled. After PRST is deasserted, the PCI1620 is in a default state.

PRST

When the

SUSPEND

mode is enabled together with

PRST,

the device is protected from

PRST

and the

internal registers are preserved, but all outputs are placed in a high-impedance state.

2−13

							Table 2−8. PCI Address and Data Terminals
	TERMINAL
NAME			NO.			I/O					DESCRIPTION
			PDV	GHK
AD31			171		E12
AD30			172		C12
AD29			175		A11
AD28			176		B11
AD27			178		E11
AD26			179		F11
AD25			167		F12
AD24			181		B10
AD23			184		F10
AD22			186		B09
AD21			187		C09
AD20			188		F09
AD19			189		E09
AD18			190		A08
AD17			191		B08		PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
AD16			192		C08
						I/O	interface. During the address phase of a primary bus PCI cycle, AD31−AD0 contain a 32-bit address or other
AD15			205		B05
							destination information. During the data phase, AD31−AD0 contain data.
AD14			206		E06
AD13			207		C05
AD12			208		A04
AD11			173		B12
AD10			1		D01
AD9			2		E03
AD8			3		F05
AD7			5		E02
AD6			7		F03
AD5			8		F02
AD4			9		G05
AD3			10		F01
AD2			11		H06
AD1			12		G03
AD0			13		G02
			164		B14		PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
C/BE3
							the address phase of a primary bus PCI cycle, C/BE3−C/BE0 define the bus command. During the data
C/BE2			193		F08
						I/O	phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit
C/BE1			204		F06
							data bus carry meaningful data. C/BE0 applies to byte 0 (AD7−AD0), C/BE1 applies to byte 1 (AD15−AD8),
C/BE0			4		G06
							C/BE2 applies to byte 2 (AD23−AD16), and C/BE3 applies to byte 3 (AD31−AD24).
							PCI bus parity. In all PCI bus read and write cycles, the PCI1620 calculates even parity across the
PAR			203		A05	I/O	AD31−AD0 and C/BE3		−C/BE0 buses. As an initiator during PCI cycles, the PCI1620 outputs this parity
							indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the parity
							indicator of the initiator. A compare error results in the assertion of a parity error (PERR).

2−14