PCA8550
NONVOLATILE 5-BIT REGISTER
WITH I2C INTERFACE
SCPS050A ± MARCH 1999 ± REVISED APRIL 1999
D EPIC (Enhanced-Performance Implanted |
D, DB, OR PW PACKAGE |
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CMOS) Submicron Process |
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D Useful for Jumperless Configuration of PC |
I2C SCL |
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VCC |
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16 |
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Motherboard |
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I2C SDA |
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2 |
15 |
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WP |
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D Inputs Accept Voltages to 5.5 V |
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OVERRIDE |
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3 |
14 |
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NON-MUXED OUT |
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D MUX OUT Signals are 2.5-V Outputs |
MUX IN A |
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4 |
13 |
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MUX SELECT |
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D NON-MUXED OUT Signal is a 3.3-V Output |
MUX IN B |
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5 |
12 |
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MUX OUT A |
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MUX IN C |
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6 |
11 |
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MUX OUT B |
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D Minimum of 1000 Write Cycles |
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MUX IN D |
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7 |
10 |
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MUX OUT C |
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D Minimum of 10 Years Data Retention |
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GND |
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8 |
9 |
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MUX OUT D |
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D Package Options Include Plastic |
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Small-Outline (D), Shrink Small-Outline |
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(DB), and Thin Shrink Small-Outline (PW) |
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description
This 4-bit 1-of-2 multiplexer with I2C input interface is designed for 3-V to 3.6-V VCC operation.
The PCA8550 is designed to multiplex four bits of data from parallel inputs or from I2C input data stored in a nonvolatile register. An additional bit of register output also is provided, which is latched to prevent changes in the output value during the write cycle. The factory default for the contents of the register is all low. These stored values can be read from, or written to, using the I2C bus. The ability to control writing to the register is provided by the write protect (WP) input. The override (OVERRIDE) input forces all the register outputs to a low.
This device provides a fast-mode (400 kbit/s) or standard-mode (100 kbit/s) I2C serial interface for data input and output. The implementation is as a slave. The device address is specified in the I2C interface definition table. Both of the I2C Schmitt-trigger inputs (SCL and SDA) provide integrated pullup resistors and are 5-V tolerant.
The PCA8550 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
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OUTPUTS |
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NON-MUXED |
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MUX SELECT |
OVERRIDE |
MUX OUT |
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OUT |
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L |
L |
L |
L |
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L |
H |
Nonvolatile |
Nonvolatile |
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register |
register |
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Latched |
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H |
X |
MUX IN |
NON-MUXED |
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OUT² |
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²The latched NON-MUXED OUT state is the value present on the NON-MUXED OUT output at the time the MUX SELECT input transitions from the low to the high state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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PCA8550
NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE
SCPS050A ± MARCH 1999 ± REVISED APRIL 1999
logic diagram (positive logic)
VCC
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1 |
I2C |
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SCL |
Interface |
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Logic |
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SDA |
2 |
Address: |
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1001110 |
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VCC |
VCC
15
WP
3
OVERRIDE
VCC
4 MUX IN A 
5
MUX IN B
6
MUX IN C
7
MUX IN D
5-Bit Nonvolatile Register
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1-Bit |
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Transparent |
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Latch |
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14 |
NON-MUXED |
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OUT |
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12 |
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MUX OUT A |
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11 |
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MUX OUT B |
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4-Bit 1-of-2 Multiplexer |
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10 |
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MUX OUT C |
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9 |
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MUX OUT D |
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VCC
13
MUX SELECT
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
PCA8550
NONVOLATILE 5-BIT REGISTER
WITH I2C INTERFACE
SCPS050A ± MARCH 1999 ± REVISED APRIL 1999
I2C interface
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the serial data (SDA) input/output while the serial clock (SCL) input is high. After the start condition, the device address byte is sent, MSB first, including the data-direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA input/output during the high of the acknowledge-related clock pulse.
The data byte follows the address acknowledge. If the R/W bit is high, the data from this device are the values read from the nonvolatile register. If the R/W bit is low, the data are from the master, to be written into the register. A valid data byte is one in which the three high-order bits are low. The first valid data byte that is received is written into the register, following the stop condition. If an invalid data byte is received, it is acknowledged, but is not written into the register. The data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the master following the acknowledge, they are ignored by this device.
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master. If the WP input is low during the falling edge of the first valid data byte acknowledge on the SCL input and the R/W bit is low, the stop condition causes the I2C interface logic to write the data byte value into the nonvolatile register. Data are written only if complete bytes are received and acknowledged. Writing to the register takes time (twr), during which the device does not respond to its slave address. If the WP input is high, the I2C interface logic does not write to the register.
I2C INTERFACE DEFINITION TABLE
BYTE |
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BIT |
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7 (MSB) |
6 |
5 |
4 |
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3 |
2 |
1 |
0 (LSB) |
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Address |
H |
L |
L |
H |
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H |
H |
L |
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R/W |
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NON- |
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MUX OUT |
MUX OUT |
MUX OUT |
MUX OUT |
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Data |
L |
L |
L |
MUXED |
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D |
C |
B |
A |
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OUT |
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . ±0.5 V to 6.5 V |
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Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . ±0.5 V to 6.5 |
V |
Output voltage range, VO (SDA) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . ±0.5 V to 6.5 |
V |
Output voltage range, VO (MUX OUT outputs) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . ±0.5 V to 2.9 |
V |
Output voltage range, VO (NON-MUXED OUT output) (see Notes 1 and 2) . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Input clamp current, IIK (VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±50 mA |
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Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . |
. . . ±50 mA, +10 mA |
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Input/output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±50 mA |
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Continuous output current, IO (VO = 0 to VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±15 mA |
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Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±30 mA |
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Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . 113°C/W |
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DB package . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . 131°C/W |
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PW package . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . 149°C/W |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . ±65°C to 85°C |
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² Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2.The value of VCC is provided in the recommended operating conditions table.
3.The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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