Texas Instruments PCI1410ARFP, PCI1410GGU, PCI1410PGE, PCI1410RFP, PCI1410AGHK Datasheet

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Data Manual

2000	PCIBus Solutions



	Printed in U.S.A.	SCPS045C
03/00

PCI1410

PC Card Controllers

Data Manual

Literature Number: SCPS045C

March 2000

Printed on Recycled Paper

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (ªCRITICAL APPLICATIONSº). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.

Contents

Section	Title	Page
1 Introduction . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	1±1

1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1±1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1±1

1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1±2

1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1±2

2 Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±1

3 Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±1

3.1	Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3±1
3.2	I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3±2
3.3	Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3±2
3.4	Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . .			3±2
	3.4.1	PCI Bus Lock		3±2
	3.4.1	PCI Bus Lock	(LOCK)	3±2
	3.4.2	Loading Subsystem Identification . . . . . . . . . . . . . . . . . . . . .		3±3
3.5	PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3±3
	3.5.1	PC Card Insertion/Removal and Recognition . . . . . . . . . . .		3±3
	3.5.2	P2C Power-Switch Interface (TPS2211) . . . . . . . . . . . . . . .		3±4
	3.5.3	Zoomed Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3±5
	3.5.4	Ultra Zoomed Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3±6
	3.5.5	Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3±6
	3.5.6	Integrated Pullup Resistors For PC Card Interface . . . . . .		3±7
	3.5.7	SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . .		3±7
	3.5.8	LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . .		3±8
	3.5.9	PC Card-16 Distributed DMA Support . . . . . . . . . . . . . . . . .		3±8
	3.5.10	PC Card-16 PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3±10
	3.5.11	CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .		3±10
3.6	Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3±11
	3.6.1	Serial Bus Interface Implementation . . . . . . . . . . . . . . . . . . .		3±11
	3.6.2	Serial Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . .		3±11
	3.6.3	Serial Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . .		3±13
	3.6.4	Accessing Serial Bus Devices Through Software . . . . . . . .		3±14
3.7	Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3±15

3.7.1PC Card Functional and Card Status Change Interrupts . 3±15

3.7.2 Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±17 3.7.3 Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3±17 3.7.4 Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3±18

iii

3.7.5 Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . . 3±18 3.7.6 SMI Support in the PCI1410 . . . . . . . . . . . . . . . . . . . . . . . . . . 3±18 3.8 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±19 3.8.1 Clock Run Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±19 3.8.2 CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3±19 3.8.3 16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . . 3±19 3.8.4 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±20 3.8.5 Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . . 3±21 3.8.6 Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±21 3.8.7 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±22 3.8.8 CardBus Bridge Power Management . . . . . . . . . . . . . . . . . . 3±23 3.8.9 ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±23

3.8.10Master List of PME Context Bits and

Global Reset Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±24

4 PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±1

4.1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±1 4.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±2 4.3 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±2 4.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±3 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±4 4.6 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±5 4.7 PCI Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±5 4.8 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±5 4.9 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±6 4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±6 4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±6 4.12 CardBus Socket/ExCA Base-Address Register . . . . . . . . . . . . . . . . . . 4±7 4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±7 4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±8 4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±9 4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±9 4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±9 4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±10 4.19 Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±10 4.20 Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±11 4.21 I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±11 4.22 I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±12 4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±12 4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±13 4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±14 4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±15 4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±15 4.28 PC Card 16-bit I/F Legacy-Mode Base-Address Register . . . . . . . . . 4±15 4.29 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±16

4.30 Multifunction Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±19 4.31 Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±20 4.32 Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±21 4.33 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±22 4.34 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±23 4.35 Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±24 4.36 Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±25 4.37 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±26 4.38 Next-Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±26 4.39 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 4±27 4.40 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . 4±28

4.41Power Management Control/Status Bridge Support Extensions

Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±29 4.42 Power Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±29 4.43 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . 4±30 4.44 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . 4±31 4.45 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±32 4.46 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±33 4.47 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±33 4.48 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±34 4.49 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±34 4.50 Serial Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 4±35

5 ExCA Compatibility Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±1

5.1 ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . 5±4 5.2 ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±5 5.3 ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±6 5.4 ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . 5±8 5.5 ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±9 5.6 ExCA Card Status-Change-Interrupt Configuration Register . . . . . . . 5±10 5.7 ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 5±11 5.8 ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±12

5.9ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . . 5±13

5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . . 5±13

5.11ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . . 5±14

5.12ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . . 5±14

5.13ExCA Memory Windows 0±4 Start-Address Low-Byte Registers . . . 5±15

5.14 ExCA Memory Windows 0±4 Start-Address High-Byte Registers . . . 5±16 5.15 ExCA Memory Windows 0±4 End-Address Low-Byte Registers . . . . 5±17

5.16ExCA Memory Windows 0±4 End-Address High-Byte Registers . . . 5±18

5.17 ExCA Memory Windows 0±4 Offset-Address Low-Byte Registers . . 5±19

5.18ExCA Memory Windows 0±4 Offset-Address High-Byte Registers . 5±20

5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . 5±21 5.20 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±22 5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . . 5±23

5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . . 5±23 5.23 ExCA Memory Windows 0±4 Page Register . . . . . . . . . . . . . . . . . . . . 5±24

6 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±1

6.1 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±2 6.2 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±3 6.3 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±4 6.4 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±6 6.5 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±8 6.6 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±9

7 Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±1

7.1 DDMA Current Address/Base-Address Register . . . . . . . . . . . . . . . . . 7±1 7.2 DDMA Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±2 7.3 DDMA Current Count/Base Count Register . . . . . . . . . . . . . . . . . . . . . 7±2 7.4 DDMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±3 7.5 DDMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±3 7.6 DDMA Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±4 7.7 DDMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±4 7.8 DDMA Master Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±5 7.9 DDMA Multichannel/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±5

8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8±1

8.1Absolute Maximum Ratings Over Operating

Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8±1

8.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 8±2

8.3Electrical Characteristics Over Recommended

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8±3

8.4PCI Clock/Reset Timing Requirements Over Recommended

Ranges of Supply Voltage and Operating Free-Air Temperature . . . 8±4

8.5PCI Timing Requirements Over Recommended Ranges

of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . 8±4 8.6 PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8±4

9 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9±1

List of Illustrations

Figure			Title	Page
2±1 PCI-to-CardBus Terminal Diagram			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2±1
2±2 PCI-to-PC Card (16-Bit) Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .				2±2
2±3 GGU Package Terminal Diagram . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2±3
2±4 GHK Package Terminal Diagram . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2±3
3±1 PCI1410 Simplified Block Diagram .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±1
3±2 3-State Bidirectional Buffer . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±2
3±3 TPS2211 Terminal Assignments . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±4
3±4 TPS2211 Typical Application . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±5
3±5 Zoomed Video Implementation Using PCI1410 . . . . . . . . . . . . . . . . . . . . . . .				3±5
3±6 Zoomed Video Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				3±6
3±7 Sample Application of SPKROUT and CAUDPWM . . . . . . . . . . . . . . . . . . . .				3±8
3±8 Two Sample LED Circuits . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±8
3±9 Serial EEPROM Application . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±11
3±10 Serial Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . .				3±12
3±11 Serial Bus Protocol Acknowledge .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±12
3±12 Serial Bus Protocol ± Byte Write . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±13
3±13 Serial Bus Protocol ± Byte Read . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±13
3±14 EEPROM Interface Doubleword Data Collection . . . . . . . . . . . . . . . . . . . . .				3±13
3±15 EEPROM Data Format . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±14
3±16 IRQ Implementation . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±18
3±17 Suspend Logic Diagram . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±20
3±18 Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				3±21
3±19		Functional Diagram		3±22
	RI_OUT		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3±20 Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				3±24
5±1 ExCA Register Access Through I/O			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5±1
5±2 ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				5±1
6±1 Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . . .				6±1

vii

List of Tables

Table	Title	Page
2±1 CardBus and 16-Bit PC Card Signal Names by GGU Terminal Number . .		2±4
2±2 CardBus and 16-Bit PC Card Signal Names by PGE Terminal Number . . .		2±5
2±3 CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number . . .		2±6
2±4 CardBus PC Card Signal Names Sorted Alphabetically to
GGU/PGE/GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		2±8
2±5 16-Bit PC Card Signal Names Sorted Alphabetically to
GGU/PGE/GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		2±10
2±6 Power Supply Terminals . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2±12
2±7 PC Card Power Switch Terminals . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2±12
2±8 PCI System Terminals . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2±12
2±9 PCI Address and Data Terminals . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2±13
2±10 PCI Interface Control Terminals . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	2±14
2±11 Multifunction and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . .		2±15
2±12 16-Bit PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . .		2±16
2±13 16-Bit PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . .		2±17
2±14 CardBus PC Card Interface System Terminals . . . . . . . . . . . . . . . . . . . . . . .		2±18
2±15 CardBus PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . .		2±19
2±16 CardBus PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . .		2±20
3±1 PC Card Card-Detect and Voltage-Sense Connections . . . . . . . . . . . . . . . .		3±4
3±2 Distributed DMA Registers . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±9
3±3 PC/PCI Channel Assignments . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±10
3±4 I/O Addresses Used for PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3±10
3±5 CardBus Socket Registers . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±11
3±6 Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . . . . . . .		3±13
3±7 PCI1410 Registers Used to Program Serial Bus Devices . . . . . . . . . . . . . . .		3±14
3±8 Interrupt Mask and Flag Registers .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±16
3±9 PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3±16
3±10 SMI Control . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±18
3±11 Power Management Registers . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3±23
4±1 PCI Configuration Registers . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±1
4±2 Bit Field Access Tag Descriptions . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±2
4±3 Command Register . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±3
4±4 Status Register . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±4
4±5 Secondary Status Register . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±8
4±6 Bridge Control Register . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±14
4±7 System Control Register . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±17
4±8 Multifunction Routing Register . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±19
4±9 Retry Status Register . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±20

viii

4±10 Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±21 4±11 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±22 4±12 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±23 4±13 Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±24 4±14 Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±25 4±15 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±27 4±16 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . 4±28

4±17 Power Management Control/Status Bridge Support

Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±29 4±18 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±30 4±19 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±31 4±20 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±32 4±21 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±33 4±22 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±33 4±23 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±34 4±24 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±34 4±25 Serial Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±35 5±1 ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±2 5±2 ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±4 5±3 ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±5 5±4 ExCA Power Control Register 82365SL Support . . . . . . . . . . . . . . . . . . . . . . 5±6 5±5 ExCA Power Control Register 82365SL-DF Support . . . . . . . . . . . . . . . . . . . 5±7 5±6 ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 5±8 5±7 ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±9 5±8 ExCA Card Status-Change-Interrupt Configuration Register . . . . . . . . . . . . 5±10 5±9 ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±11 5±10 ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±12 5±11 ExCA Memory Windows 0±4 Start-Address High-Byte Registers . . . . . . . 5±16 5±12 ExCA Memory Windows 0±4 End-Address High-Byte Registers . . . . . . . . 5±18 5±13 ExCA Memory Windows 0±4 Offset-Address High-Byte Registers . . . . . . 5±20 5±14 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . . . . . . 5±21 5±15 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±22 6±1 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±1 6±2 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±2 6±3 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±3 6±4 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±4 6±5 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±7 6±6 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±8 6±7 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±9

7±1 Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±1 7±2 DDMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±3 7±3 DDMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±3 7±4 DDMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±4 7±5 DDMA Multichannel/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±5

1 Introduction

1.1 Description

The TI PCI1410 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant with the 1997 PC Card Standard. The PCI1410 provides features that make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1410 supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required.

The PCI1410 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bridging transactions. The PCI1410 is also compliant with the latest PCI Bus Power Management Interface Specification and PCI Bus Power Management Interface Specification for PCI to CardBus Bridges.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1410 is register compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The PCI1410 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1410 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1410, such as socket activity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.

1.2 Features

The PCI1410 supports the following features:

•Ability to wake from D3hot and D3cold

•Fully compatible with the Intel 430TX (Mobile Triton II) chipset

•A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGA ball grid array (GGU) package, or 209-terminal MicroStar BGA (GHK) package

•3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

•Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards

•Single PC Card or CardBus slot with hot insertion and removal

•Burst transfers to maximize data throughput on the PCI bus and the CardBus bus

•Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI interrupts, and serial ISA IRQ and PCI interrupts

TI is a trademark of Texas Instruments.

MicroStar BGA is a trademark of Texas Instruments.

Intel is a trademark of Intel Corporation.

Other trademarks are the property of their respective owners.

1±1

•Serial EEPROM interface for loading subsystem ID and subsystem vendor ID

•Pipelined architecture allows greater than 130-Mbps sustained throughput from CardBus to PCI and from PCI to CardBus

•Interface to parallel single-slot PC Card power interface switches like the TI TPS2211

•Up to five general-purpose I/Os

•Programmable output select for CLKRUN

•Five PCI memory windows and two I/O windows available to the 16-bit PC Card socket

•Two I/O windows and two memory windows available to the CardBus socket

•Exchangeable card architecture (ExCA) compatible registers are mapped in memory and I/O space

•Intel 82365SL-DF and 82365SL register compatible

•Distributed DMA (DDMA) and PC/PCI DMA

•16-Bit DMA on the PC Card socket

•Ring indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN

•Socket activity LED pins

•PCI bus lock (LOCK)

•Advanced submicron, low-power CMOS technology

•Internal ring oscillator

1.3Related Documents

•Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0)

•PCI Bus Power Management Interface Specification (Revision 1.1)

•PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (Revision 0.6)

•PCI Local Bus Specification (Revision 2.2)

•PCI Mobile Design Guide (Revision 1.0)

•PCI14xx Implementation Guide for D3 Wake-Up

•1997 PC Card Standard

•PC 98

•PC 99

•Serialized IRQ Support for PCI Systems (Revision 6)

1.4Ordering Information

ORDERING NUMBER	NAME	VOLTAGE	PACKAGE

PCI1410	PC Card Controller	3.3-V, 5-V tolerant I/Os	144-terminal LQFP
			144-terminal PBGA
			209-terminal PBGA

1±2

2 Terminal Descriptions

The PCI1410 is packaged in either a 144-terminal GGU MicroStar BGA or a 144-terminal PGE package. It is also packaged in a 209-terminal GHK MicroStar BGA that is pin compatible with the TI PCI4410. The PCI4410 is a single-socket CardBus bridge with integrated OHCI link. Figure 2±1 is a PGE-package terminal diagram showing PCI-to-CardBus signal names, and Figure 2±2 is a PGE-package terminal diagram showing PCI-to-PC Card signal names. Figure 2±3 and Figure 2±4 are terminal diagrams for the GGU and GHK packages, respectively.

PGE LOW-PROFILE QUAD FLAT PACKAGE

(TOP VIEW)

							CCLK	CDEVSEL	CGNT	CSTOP	CPERR	CBLOCK V			CPAR		CRSVD		CC/BE1		CAD16		CAD14		CAD15		CAD12	GND		CAD13		CAD11	CAD10		V		CAD9		CC/BE0		CAD8		V		CAD7		CRSVD		CAD5		CAD6	CAD3		CAD4	CAD1		GND		CAD2		CAD0	CCD1		VCCD1	VCCD0
														CC																						CCCB								CC




						108		107	106	105	104	103	102		101		100		99		98		97		96		95	94	93		92		91		90		89		88	87			86		85		84		83		82	81		80	79		78		77		76	75	74		73	VPPD1
						108		107	106	105	104	103	102		101		100		99		98		97		96		95	94	93		92		91		90		89		88	87			86		85		84		83		82	81		80	79		78		77		76	75	74		73
			CTRDY			109																																																											72
			CIRDY			110																																																											71	VPPD0
	CFRAME					111																																																											70		SUSPEND
	CFRAME					111																																																											70		SUSPEND
		CC/BE2				112																																																											69	MFUNC6
		CC/BE2				112																																																											69	MFUNC6
			CAD17			113																																																											68	MFUNC5
			CAD17			113																																																											68	MFUNC5
					GND	114																																																											67	MFUNC4
					GND	114																																																											67	MFUNC4
			CAD18			115																																																											66	GRST
			CAD18			115																																																											66	GRST
			CAD19			116																																																											65	MFUNC3
			CAD19			116																																																											65	MFUNC3
					CVS2	117																																																											64	MFUNC2
					CVS2	117																																																											64	MFUNC2
			CAD20			118																																																											63	VCCI
			CAD20			118																																																											63	VCCI
					CRST	119																																																											62	SPKROUT
					CRST	119																																																											62	SPKROUT
			CAD21			120																																																											61	MFUNC1
			CAD21			120																																																											61	MFUNC1
			CAD22			121																																																											60	MFUNC0
			CAD22			121																																																											60	MFUNC0
					VCC	122
																																																																	59	RI_OUT/PME
																																																																	59	RI_OUT/PME
				CREQ		123																																																											58	GND
				CREQ		123																																																											58	GND
			CAD23			124																																																											57	AD0
			CAD23			124																																																											57	AD0
		CC/BE3				125																																																											56	AD1
		VCCCB				126																																																											55	AD2
		VCCCB				126																																																											55	AD2
			CAD24			127																																																											54	AD3
			CAD24			127																																																											54	AD3
			CAD25			128																																																											53	AD4
			CAD25			128																																																											53	AD4
			CAD26			129																																																											52	AD5
			CAD26			129																																																											52	AD5
					GND	130																																																											51	AD6
					GND	130																																																											51	AD6
				CVS1		131																																																											50	VCC
				CVS1		131																																																											50	VCC
					CINT	132																																																											49	AD7
					CINT	132																																																											49	AD7

		CSERR				133																																																											48	C/BE0
		CSERR				133																																																											48	C/BE0
	CAUDIO					134																																																											47	AD8
	CAUDIO					134																																																											47	AD8
CSTSCHG						135																																																											46	AD9
CSTSCHG						135																																																											46	AD9
CCLKRUN						136																																																											45	AD10
				CCD2		137																																																											44	VCCP
					VCC	138																																																											43	AD11
					VCC	138																																																											43	AD11
			CAD27			139																																																											42	GND
			CAD28			140																																																											41	AD12
			CAD28			140																																																											41	AD12
			CAD29			141																																																											40	AD13
			CAD29			141																																																											40	AD13
			CAD30			142																																																											39	AD14
			CAD30			142																																																											39	AD14
		CRSVD				143																																																											38	AD15
		CRSVD				143																																																											38	AD15
			CAD31			144
																																																																	37	C/BE1
																																																																	37	C/BE1
																			10		11		12		13		14	15	16		17		18		19		20		21	22			23		24		25		26		27	28		29	30		31		32		33	34	35		36
						1		2	3	4	5	6	7		8		9		10		11		12		13		14	15	16		17		18		19		20		21	22			23		24		25		26		27	28		29	30		31		32		33	34	35		36

							REQ																												AD20																														PAR
							REQ	GNT AD31		AD30	AD29	GND	AD28			AD27		AD26		AD25		AD24		C/BE3		IDSEL V		AD23	AD22			AD21	V		AD20			PRST PCLK				GND AD19				AD18		AD17		AD16	C/BE2		FRAME IRDY V					TRDY		DEVSEL	STOP	PERR	SERR		PAR
																											CC							CCP																						CC

Figure 2±1. PCI-to-CardBus Terminal Diagram

2±1

PGE LOW-PROFILE QUAD FLAT PACKAGE

(TOP VIEW)

									ADDR16	ADDR21	WE	ADDR20	ADDR14	ADDR19	V		ADDR13		ADDR18	ADDR8		ADDR17		ADDR9	IOWR		ADDR11	GND	IORD OE		CE2	V			ADDR10	CE1	DATA15	V		DATA7		DATA14		DATA6		DATA13	DATA5		DATA12	DATA4	GND		DATA11		DATA3	CD1	VCCD1	VCCD0
																CC																	CCCB						CC

	ADDR22						108			107	106	105	104	103	102		101		100	99		98	97		96		95	94	93	92	91	90		89		88	87	86		85		84		83		82	81		80	79	78		77		76	75	74	73	VPPD1
							109																																																			72


	ADDR15						110																																																			71	VPPD0


	ADDR23							111																																																		70		SUSPEND
	ADDR23							111																																																		70		SUSPEND
	ADDR12							112																																																		69	MFUNC6
	ADDR12							112																																																		69	MFUNC6
	ADDR24							113																																																		68	MFUNC5
	ADDR24							113																																																		68	MFUNC5
				GND			114																																																			67	MFUNC4
				GND			114																																																			67	MFUNC4
			ADDR7					115																																																		66	GRST
			ADDR7					115																																																		66	GRST
	ADDR25							116																																																		65	MFUNC3
	ADDR25							116																																																		65	MFUNC3
				VS2				117																																																		64	MFUNC2
				VS2				117																																																		64	MFUNC2
			ADDR6					118																																																		63	VCCI
			ADDR6					118																																																		63	VCCI
			RESET					119																																																		62	SPKROUT
			RESET					119																																																		62	SPKROUT
			ADDR5					120																																																		61	MFUNC1
			ADDR5					120																																																		61	MFUNC1
			ADDR4					121																																																		60	MFUNC0
			ADDR4					121																																																		60	MFUNC0
				VCC			122
																																																										59	RI_OUT/PME
																																																										59	RI_OUT/PME
		INPACK						123																																																		58	GND
		INPACK						123																																																		58	GND
			ADDR3					124																																																		57	AD0
			ADDR3					124																																																		57	AD0
				REG				125																																																		56	AD1
			VCCCB				126																																																			55	AD2
			VCCCB				126																																																			55	AD2
			ADDR2					127																																																		54	AD3
			ADDR2					127																																																		54	AD3
			ADDR1					128																																																		53	AD4
			ADDR1					128																																																		53	AD4
			ADDR0					129																																																		52	AD5
			ADDR0					129																																																		52	AD5
				GND			130																																																			51	AD6
				GND			130																																																			51	AD6
				VS1				131																																																		50	VCC
				VS1				131																																																		50	VCC
READY(				IREQ		)		132																																																		49	AD7
READY(				IREQ		)		132																																																		49	AD7
			WAIT
								133																																																		48	C/BE0
								133																																																		48	C/BE0
					)
BVD2(SPKR								134																																																		47	AD8
BVD2(SPKR								134																																																		47	AD8
																																																											AD9
BVD1(STSCHG/RI)								135																																																		46
BVD1(STSCHG/RI)								135																																																		46
																																																											AD10
	WP(IOIS16)							136																																																		45	AD10
				CD2				137																																																		44	VCCP
				VCC			138																																																			43	AD11
				VCC			138																																																			43	AD11
			DATA0					139																																																		42	GND
			DATA0					139																																																		42	GND
			DATA8					140																																																		41	AD12
			DATA8					140																																																		41	AD12
			DATA1					141																																																		40	AD13
			DATA1					141																																																		40	AD13
			DATA9					142																																																		39	AD14
			DATA9					142																																																		39	AD14
			DATA2					143																																																		38	AD15
			DATA2					143																																																		38	AD15
		DATA10					144
		DATA10					144																																																			37	C/BE1
							1			2	3	4	5	6	7		8		9	10		11	12		13		14	15	16	17	18	19		20		21	22	23		24		25		26		27	28		29	30	31		32		33	34	35	36


									REQ	GNT AD31		AD30	AD29	GND	AD28			AD27	AD26		AD25	AD24		C/BE3		IDSEL V		AD23	AD22	AD21	V	AD20			PRST PCLK		GND AD19				AD18		AD17		AD16	C/BE2		FRAME IRDY V				TRDY		DEVSEL STOP		PERR SERR		PAR
																											CC				CCP																			CC

Figure 2±2. PCI-to-PC Card (16-Bit) Terminal Diagram

2±2

Texas Instruments PCI1410ARFP, PCI1410GGU, PCI1410PGE, PCI1410RFP, PCI1410AGHK Datasheet

1 2 3 4 5 6 7 8 9 10 11 12 13

Figure 2±3. GGU Package Terminal Diagram

1	3		5	7	9	11	13	15	17	19
	2	4	6	8	10	12	14	16		18

Figure 2±4. GHK Package Terminal Diagram

Table 2±1 shows the terminal assignments for the 144-terminal GGU CardBus and 16-bit PC Card signal names. Table 2±2 shows the terminal assignments for the 144-terminal PGE CardBus and 16-bit PC Card signal names. Table 2±3 shows the terminal assignments for the 209-terminal GHK CardBus and 16-bit PC Card signal names. Table 2±4 shows the CardBus PC Card signal names sorted alphabetically to the GGU/PGE/GHK terminal numbers. Table 2±5 shows the 16-bit PC Card signal names sorted alphabetically to the GGU/PGE/GHK terminal numbers.

2±3

Table 2±1. CardBus and 16-Bit PC Card Signal Names by GGU Terminal Number

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

CARD

NO.

16-BIT

NO.

16-BIT

NO.

16-BIT

NO.

16-BIT

BUS

REQ

C11

CGNT

G10

CAD11

GND

CRSVD

DATA2

C12

ADDR20

G11

CAD10

AD9

CSTOP

CE2

CAD28

DATA8

C13

ADDR14

G12

CAD9

ADDR10

VCC

CPERR

CCD2

CD2

AD27

G13

VCCCB

AD2

CSERR

WAIT

AD28

PCLK

RI_OUT/

PME

CAD26

ADDR0

GND

VCCI

VCCCB

AD29

AD19

L10

MFUNC4

CAD23

ADDR3

AD18

L11

CCLKRUN

SUSPEND

(IOIS16)

CAD21

ADDR5

READY

H10

CAD7

DATA7

L12

CINT

CCD1

CD1

(IREQ)

A10

CAD19

ADDR25

CAD25

ADDR1

H11

VCC

L13

CAD0

DATA3

A11

ADDR12

CAD22

ADDR4

H12

CAD8

DATA15

CC/BE2

SERR

A12

ADDR15

CVS2

H13

PAR

CIRDY

VS2

CC/BE0

CE1

A13

ADDR22

D10

CAD17

ADDR24

AD17

AD14

CTRDY

GNT

D11

CBLOCK

ADDR19

AD16

AD11

CAD31

DATA10

D12

VCC

AD8

C/BE2

CAD29

DATA1

D13

CPAR

ADDR13

AD6

FRAME

VCC

J10

CAD3

DATA5

AD4

C/BE3

CAUDIO

BVD2

AD24

J11

CAD6

DATA13

GND

(SPKR)

GND

AD25

J12

CAD5

DATA6

SPKROUT

CC/BE3

REG

AD26

J13

CRSVD

DATA14

M10

GRST

CREQ

INPACK

E10

CRSVD

ADDR18

IRDY

M11

MFUNC6

RESET

E11

ADDR8

VCC

M12

VPPD1

CRST

CC/BE1

B10

CAD18

ADDR7

E12

CAD16

ADDR17

M13

TRDY

VCCD1

B11

ADDR23

E13

CAD14

ADDR9

AD12

CFRAME

C/BE1

B12

CCLK

ADDR16

AD22

AD10

AD15

B13

ADDR21

AD23

AD7

AD13

CDEVSEL

AD30

VCC

AD1

VCCP

AD31

IDSEL

MFUNC0

C/BE0

CAD30

DATA9

F10

CAD15

MFUNC2

AD5

IOWR

CAD27

DATA0

F11

CAD12

ADDR11

K10

CAD2

DATA11

AD3

CSTSCHG

BVD1

F12

GND

K11

GND

AD0

(STSCHG/RI)

CVS1

VS1

F13

CAD13

IORD

K12

CAD1

DATA4

MFUNC1

CAD24

ADDR2

VCCP

K13

CAD4

DATA12

N10

MFUNC3

VCC

AD21

N11

MFUNC5

DEVSEL

CAD20

ADDR6

AD20

N12

VPPD0

STOP

C10

GND

N13

PRST

PERR

VCCD0

2±4

Table 2±2. CardBus and 16-Bit PC Card Signal Names by PGE Terminal Number

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

CARD

NO.

16-BIT

NO.

16-BIT

NO.

16-BIT

NO.

16-BIT

BUS

REQ

C/BE1

VCCD0

109

CTRDY

ADDR22

AD15

110

ADDR15

GNT

VCCD1

CIRDY

AD31

AD14

111

ADDR23

CCD1

CD1

CFRAME

AD30

AD13

CAD0

DATA3

112

ADDR12

CC/BE2

AD29

AD12

CAD2

DATA11

113

CAD17

ADDR24

GND

114

GND

AD28

AD11

CAD1

DATA4

115

CAD18

ADDR7

AD27

VCCP

CAD4

DATA12

116

CAD19

ADDR25

AD26

AD10

CAD3

DATA5

117

CVS2

VS2

AD25

AD9

CAD6

DATA13

118

CAD20

ADDR6

AD24

AD8

CAD5

DATA6

119

RESET

CRST

CRSVD

DATA14

120

CAD21

ADDR5

C/BE3

C/BE0

IDSEL

AD7

CAD7

DATA7

121

CAD22

ADDR4

VCC

122

VCC

AD23

AD6

CAD8

DATA15

123

CREQ

INPACK

AD22

AD5

124

CAD23

ADDR3

CC/BE0

CE1

AD21

AD4

CAD9

ADDR10

125

CC/BE3

REG

VCCP

AD3

VCCCB

126

VCCCB

AD20

AD2

CAD10

127

CAD24

ADDR2

CE2

AD1

CAD11

128

CAD25

ADDR1

PRST

PCLK

AD0

CAD13

129

CAD26

ADDR0

IORD

GND

130

GND

AD19

CAD12

ADDR11

131

CVS1

RI_OUT/

VS1

PME

AD18

MFUNC0

CAD15

132

READY

IOWR

CINT

(IREQ)

AD17

MFUNC1

CAD14

ADDR9

133

CSERR

WAIT

AD16

SPKROUT

CAD16

ADDR17

134

CAUDIO

BVD2

(SPKR)

VCCI

ADDR8

135

CSTSCHG

BVD1

C/BE2

CC/BE1

(STSCHG/RI)

MFUNC2

100

CRSVD

ADDR18

136

FRAME

CCLKRUN

(IOIS16)

MFUNC3

101

CPAR

ADDR13

137

IRDY

CCD2

CD2

VCC

102

VCC

138

VCC

GRST

MFUNC4

103

ADDR19

139

CAD27

DATA0

TRDY

CBLOCK

MFUNC5

104

ADDR14

140

CAD28

DATA8

DEVSEL

CPERR

MFUNC6

105

ADDR20

141

CAD29

DATA1

STOP

CSTOP

106

142

CAD30

DATA9

PERR

SUSPEND

CGNT

VPPD0

107

ADDR21

143

CRSVD

DATA2

SERR

CDEVSEL

PAR

VPPD1

108

CCLK

ADDR16

144

CAD31

DATA10

2±5

Table 2±3. CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

NO.

CARDBUS

16-BIT

NO.

CARDBUS

16-BIT

NO.

CARDBUS

16-BIT

CAD29

DATA1

H17

CAD11

E10

CSTSCHG

H18

CAD10

BVD1(STSCHG/RI)

CE2

E11

GND

H19

VCCCB

E12

AD31

CREQ

INPACK

CAD30

DATA9

E13

CVS2

AD30

VS2

E14

ADDR23

AD29

CCD2

CD2

CFRAME

A10

E17

ADDR21

GND

CINT

READY(IREQ)

CDEVSEL

A11

CAD24

ADDR2

E18

ADDR20

AD28

CSTOP

A12

VCCCB

E19

ADDR19

J14

CBLOCK

CC/BE0

CE1

A13

VCC

J15

CAD9

ADDR10

A14

CAD20

ADDR6

J17

CAD8

DATA15

A15

GND

J18

VCC

A16

ADDR22

J19

CAD7

DATA7

CTRDY

AD27

AD26

AD25

CRSVD

DATA2

CAD28

DATA8

AD24

VCC

F10

CCLKRUN

WP(IOIS16)

C/BE3

B10

F11

CVS1

K14

CRSVD

DATA14

CSERR

WAIT

VS1

B11

CAD25

ADDR1

F12

RESET

K15

CAD5

DATA6

CRST

B12

F13

ADDR12

K17

CAD6

DATA13

CC/BE3

REG

CC/BE2

B13

CAD22

ADDR4

F14

ADDR14

K18

CAD3

DATA5

CPERR

B14

CAD19

ADDR25

F15

K19

CAD4

DATA12

CGNT

B15

CAD17

ADDR24

F17

VCC

IDSEL

F18

CRSVD

ADDR18

VCC

F19

ADDR8

AD23

CC/BE1

AD21

CAD31

DATA10

AD22

CAD27

DATA0

L14

CAD1

DATA4

C10

CAUDIO

L15

GND

BVD2(SPKR)

C11

CAD26

ADDR0

L17

CAD2

DATA11

C12

CAD23

ADDR3

G14

CAD16

ADDR17

L18

CAD0

DATA3

C13

CAD21

ADDR5

G15

CPAR

ADDR13

L19

CCD1

CD1

C14

CAD18

ADDR7

G17

CAD14

ADDR9

VCCP

C15

ADDR15

G18

CAD15

AD20

CIRDY

IOWR

G19

CAD12

ADDR11

PRST

D19

CCLK

ADDR16

GND

GNT

PCLK

REQ

M14

M15

M17

H14

CAD13

M18

IORD

VCCD0

H15

GND

M19

VCCD1

2±6

Table 2±3. CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number (Continued)

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

TERM.

SIGNAL NAME

NO.

CARDBUS

16-BIT

NO.

CARDBUS

16-BIT

NO.

CARDBUS

16-BIT

AD19

U15

TRDY

AD18

AD12

STOP

AD17

VCCP

SERR

AD14

AD7

IRDY

AD16

AD10

AD4

N14

AD6

AD1

N15

GND

V10

MFUNC1

N17

R10

VCCI

V11

GRST

N18

R11

MFUNC6

V12

VPPD0

N19

R12

V13

R13

V14

C/BE2

R14

V15

FRAME

VCC

R17

C/BE1

R18

GND

PERR

R19

AD9

DEVSEL

AD13

PAR

VCC

AD8

T19

AD3

AD15

AD2

RI_OUT/PME

P10

MFUNC2

AD11

W10

MFUNC0

P11

MFUNC5

W11

MFUNC3

C/BE0

P12

AD5

W12

SUSPEND

P13

AD0

W13

P14

U10

SPKROUT

W14

P15

U11

MFUNC4

W15

P17

U12

VPPD1

W16

P18

U13

P19

U14

2±7

Table 2±4. CardBus PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM. NO.

GGU

PGE

GHK

GGU

PGE

GHK

GGU

PGE

GHK

AD0

CAD11

G10

H17

119

F12

CRST

AD1

CAD12

F11

G19

CRSVD

143

AD2

CAD13

F13

H14

CRSVD

E10

100

F18

AD3

CAD14

E13

G17

CRSVD

J13

K14

AD4

CAD15

F10

G18

133

B10

CSERR

AD5

CAD16

E12

G14

C12

105

E18

CSTOP

AD6

CAD17

D10

113

B15

CSTSCHG

135

E10

AD7

CAD18

B10

115

C14

A13

109

A16

CTRDY

AD8

CAD19

A10

116

B14

CVS1

131

F11

AD9

CAD20

118

A14

CVS2

117

E13

AD10

CAD21

120

C13

DEVSEL

AD11

CAD22

121

B13

FRAME

AD12

CAD23

124

C12

GND

A15

AD13

CAD24

127

A11

GND

E11

AD14

CAD25

128

B11

GND

H15

AD15

CAD26

129

C11

GND

AD16

CAD27

139

GND

K11

L15

AD17

CAD28

140

GND

F12

AD18

CAD29

141

GND

C10

114

AD19

CAD30

142

GND

130

AD20

CAD31

144

GNT

AD21

CAUDIO

134

C10

M10

V11

GRST

AD22

IDSEL

C/BE0

AD23

C/BE1

IRDY

AD24

MFUNC0

W10

C/BE2

AD25

MFUNC1

V10

C/BE3

AD26

D11

103

E19

MFUNC2

P10

CBLOCK

AD27

H13

J14

MFUNC3

N10

W11

CC/BE0

AD28

E11

F19

MFUNC4

L10

U11

CC/BE1

AD29

A11

112

F13

MFUNC5

N11

P11

CC/BE2

AD30

125

B12

MFUNC6

M11

R11

CC/BE3

AD31

L12

L19

PAR

CCD1

CAD0

L13

L18

137

PCLK

CCD2

CAD1

K12

L14

CCLK

B12

108

D19

PERR

CAD2

K10

L17

136

F10

CCLKRUN

PRST

CAD3

J10

K18

B13

107

E17

CDEVSEL

REQ

CAD4

K13

K19

B11

111

E14

CFRAME

RI_OUT/PME

CAD5

J12

K15

C11

106

F15

CGNT

SERR

CAD6

J11

K17

132

A10

SPKROUT

U10

CINT

CAD7

H10

J19

A12

110

C15

CIRDY

STOP

CAD8

H12

J17

CPAR

D13

101

G15

L11

W12

SUSPEND

CAD9

G12

J15

C13

104

F14

CPERR

TRDY

CAD10

G11

H18

123

E12

VCC

A13

CREQ

2±8

Table 2±4. CardBus PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number (Continued)

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM. NO.

GGU

PGE

GHK

GGU

PGE

GHK

GGU

PGE

GHK

VCC

138

VCCI

R10

VCC

F17

VCCCB

G13

A12

VCCP

VCC

H11

J18

VCCCB

126

H19

VCCP

VCC

D12

102

N13

M18

VPPD0

N12

V12

VCCD0

VCC

122

M13

M19

VPPD1

M12

U12

VCCD1

2±9

Table 2±5. 16-Bit PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM. NO.

GGU

PGE

GHK

GGU

PGE

GHK

GGU

PGE

GHK

AD0

ADDR11

F11

G19

GND

A15

AD1

ADDR12

A11

112

F13

GND

E11

AD2

ADDR13

D13

101

G15

GND

H15

AD3

ADDR14

C13

104

F14

GND

AD4

ADDR15

A12

110

C15

GND

K11

L15

AD5

ADDR16

B12

108

D19

GND

F12

AD6

ADDR17

E12

G14

GND

C10

114

AD7

ADDR18

E10

100

F18

GND

130

AD8

ADDR19

D11

103

E19

GNT

AD9

ADDR20

C12

105

E18

M10

V11

GRST

AD10

ADDR21

B13

107

E17

IDSEL

AD11

ADDR22

A13

109

A16

123

E12

INPACK

AD12

ADDR23

B11

111

E14

F13

H14

IORD

AD13

ADDR24

D10

113

B15

F10

G18

IOWR

AD14

ADDR25

A10

116

B14

IRDY

AD15

135

E10

MFUNC0

W10

BVD1(STSCHG/RI)

AD16

134

C10

MFUNC1

V10

BVD2(SPKR)

AD17

MFUNC2

P10

C/BE0

AD18

MFUNC3

N10

W11

C/BE1

AD19

MFUNC4

L10

U11

C/BE2

AD20

MFUNC5

N11

P11

C/BE3

AD21

L12

L19

MFUNC6

M11

R11

CD1

AD22

137

G10

H17

CD2

AD23

H13

J14

PAR

CE1

AD24

G11

H18

PCLK

CE2

AD25

DATA0

139

PERR

AD26

DATA1

141

PRST

AD27

DATA2

143

132

A10

READY(IREQ)

AD28

DATA3

L13

L18

125

B12

REG

AD29

DATA4

K12

L14

REQ

AD30

DATA5

J10

K18

RESET

119

F12

AD31

DATA6

J12

K15

RI_OUT/PME

ADDR0

129

C11

DATA7

H10

J19

SERR

ADDR1

128

B11

DATA8

140

SPKROUT

U10

ADDR2

127

A11

DATA9

142

STOP

ADDR3

124

C12

DATA10

144

L11

W12

SUSPEND

ADDR4

121

B13

DATA11

K10

L17

TRDY

ADDR5

120

C13

DATA12

K13

K19

VCC

A13

ADDR6

118

A14

DATA13

J11

K17

VCC

ADDR7

B10

115

C14

DATA14

J13

K14

VCC

F17

ADDR8

E11

F19

DATA15

H12

J17

VCC

H11

J18

ADDR9

E13

G17

VCC

D12

102

DEVSEL

ADDR10

G12

J15

VCC

122

FRAME

2±10

Table 2±5. 16-Bit PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number (Continued)

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM. NO.

SIGNAL NAME

TERM. NO.

GGU

PGE

GHK

GGU

PGE

GHK

GGU

PGE

GHK

VCC

138

VCCI

R10

131

F11

VS1

VCCCB

G13

A12

VCCP

117

E13

VS2

VCCCB

126

H19

VCCP

133

B10

WAIT

N13

M18

VPPD0

N12

V12

C11

106

F15

VCCD0

M13

M19

VPPD1

M12

U12

136

F10

VCCD1

WP(IOIS16)

2±11

The terminals are grouped in tables by functionality (see Table 2±6 through Table 2±16), such as PCI system function and power-supply function. The terminal numbers are also listed for convenient reference.

				Table 2±6. Power Supply Terminals
	TERMINAL

NAME		NUMBER			DESCRIPTION
NAME	GGU	PGE	GHK
	GGU	PGE	GHK

	B6, C10,	6, 22, 42,	A15, E11,
GND	D3, F12,	58, 78,	H15, J5,		Device ground terminals
GND	H2, K11,	94, 114,	L15, M5,		Device ground terminals
	H2, K11,	94, 114,	L15, M5,
	L4, M8	130	R9, W5

	B4, C8,	14, 30,	A13, B9,
VCC	D12, F3,	50, 86,	F17, J18,		Power supply terminal for core logic (3.3 V)
VCC	H11, K2,	102, 122,	L2, P3,		Power supply terminal for core logic (3.3 V)
	H11, K2,	102, 122,	L2, P3,
	L6	138	W7

VCCCB	A7, G13	90, 126	A12, H19		Clamp voltage for PC Card interface. Matches card signaling environment, 5 V or 3.3 V.
VCCI	L9	63	R10		Clamp voltage for interrupt subsystem interface and miscellaneous I/O, 5 V or 3.3 V
VCCP	G1, N4	18, 44	M1, V6		Clamp voltage for PCI signaling, 5 V or 3.3 V

							Table 2±7. PC Card Power Switch Terminals
		TERMINAL

	NAME		NUMBER			I/O		DESCRIPTION
	NAME	GGU		PGE	GHK
		GGU		PGE	GHK

		N13		73	M18
	VCCD0	N13		73	M18	O		Logic controls to the TPS2211 PC Card power interface switch to control AVCC.
VCCD1		M13		74	M19	O
VCCD1		M13		74	M19

	VPPD0	N12		71	V12	O		Logic controls to the TPS2211 PC Card power interface switch to control AVPP.
	VPPD1	M12		72	U12	O
	VPPD1	M12		72	U12

Table 2±8. PCI System Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

GGU

PGE

GHK

Global reset. When the global reset is asserted, the

GRST

signal causes the PCI1410 to place all

output buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the

device is completely in its default state. For systems that require wake-up from D3, GRST will

normally be asserted only during initial boot. PRST should be used following initial boot so that PME

GRST

M10

V11

context is retained when transitioning from D3 to D0. For systems that do not require wake-up from

D3, GRST should be tied to PRST.

mode is enabled, the device is protected from the

and the internal

When the

SUSPEND

GRST,

registers are preserved. All outputs are placed in a high-impedance state.

PCLK

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled

at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted,

PRST

causes the PCI1410 to place all output buffers

in a high-impedance state and reset internal registers. When PRST is asserted, the device is

completely nonfunctional. After

PRST

is deasserted, the PCI1410 is in a default state.

PRST

When the

SUSPEND

mode is enabled, the device is protected from the

PRST,

and the internal

registers are preserved. All outputs are placed in a high-impedance state.

2±12

Table 2±9. PCI Address and Data Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

GGU

PGE

GHK

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the

AD16

I/O

primary interface. During the address phase of a primary bus PCI cycle, AD31±AD0 contain a 32-bit

AD15

address or other destination information. During the data phase, AD31±AD0 contain data.

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals.

During the address phase of a primary bus PCI cycle,

BE3

C/BE3±C/BE0 define the bus command.

C/BE2

I/O

During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which

C/BE1

byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7±AD0),

C/BE0

C/BE1 applies to byte 1 (AD15±AD8), C/BE2 applies to byte 2 (AD23±AD16), and C/BE3 applies

to byte 3 (AD31±AD24).

PCI bus parity. In all PCI bus read and write cycles, the PCI1410 calculates even parity across the

AD31±AD0 and C/BE3±C/BE0 buses. As an initiator during PCI cycles, the PCI1410 outputs this

PAR

I/O

parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is

compared to the initiator parity indicator. A compare error results in the assertion of a parity error

(PERR).

2±13

Table 2±10. PCI Interface Control Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

GGU

PGE

GHK

PCI device select. The PCI1410 asserts

DEVSEL

to claim a PCI cycle as the target device. As a PCI

DEVSEL

I/O

initiator on the bus, the PCI1410 monitors DEVSEL until a target responds. If no target responds

before timeout occurs, then the PCI1410 terminates the cycle with an initiator abort.

PCI cycle frame.

FRAME

is driven by the initiator of a bus cycle.

FRAME

is asserted to indicate that

FRAME

I/O

a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME

is deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant.

GNT

is driven by the PCI bus arbiter to grant the PCI1410 access to the PCI bus after

GNT

the current data transaction has completed. GNT may or may not follow a PCI bus request, depending

on the PCI bus parking algorithm.

IDSEL

Initialization device select. IDSEL selects the PCI1410 during configuration space accesses. IDSEL

can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready.

IRDY

indicates the ability of the PCI bus initiator to complete the current data phase

IRDY

I/O

of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY

are asserted. Until

IRDY

and TRDY are both sampled asserted, wait states are inserted.

PCI parity error indicator.

PERR

is driven by a PCI device to indicate that calculated parity does not

PERR

I/O

match PAR when PERR is enabled through bit 6 of the command register (offset 04h, see

Section 4.4).

PCI bus request.

is asserted by the PCI1410 to request access to the PCI bus as an initiator.

REQ

PCI system error.

SERR

is an output that is pulsed from the PCI1410 when enabled through bit 8 of

the command register (offset 04h, see Section 4.4) indicating a system error has occurred. The

SERR

PCI1410 need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the

command register, this signal also pulses, indicating that an address parity error has occurred on a

CardBus interface.

PCI cycle stop signal.

STOP

is driven by a PCI target to request the initiator to stop the current PCI

STOP

I/O

bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that

do not support burst data transfers.

PCI target ready.

TRDY

indicates the ability of the primary bus target to complete the current data

TRDY

I/O

phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and

TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

2±14

Table 2±11. Multifunction and Miscellaneous Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

GGU

PGE

GHK

Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt

INTA,

GPI0,

MFUNC0

W10

I/O

GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a

parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.

Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, socket activity LED

output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See Section 4.30,

Multifunction Routing Register, for configuration details.

MFUNC1

V10

I/O

Serial data (SDA). When

VCCD0

and

VCCD1

are high after a PCI reset, the MFUNC1 terminal

provides the SDA signaling for the serial bus interface. The two-terminal serial interface loads

the subsystem identification and other register defaults from an EEPROM after a PCI reset. See

Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications.

Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2,

MFUNC2

P10

I/O

socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, RI_OUT, or a

parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.

MFUNC3

N10

W11

I/O

Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt

signal IRQSER. See Section 4.30, Multifunction Routing Register, for configuration details.

Multifunction terminal 4. MFUNC4 can be configured as PCI

LOCK, GPI3, GPO3, socket activity

LED output, ZV switching outputs, CardBus audio PWM, GPE, RI_OUT, or a parallel IRQ. See

Section 4.30, Multifunction Routing Register, for configuration details.

MFUNC4

L10

U11

I/O

are high after a PCI reset, the MFUNC4 terminal

Serial clock (SCL). When

VCCD0

and

VCCD1

provides the SCL signaling for the serial bus interface. The two-terminal serial interface loads

the subsystem identification and other register defaults from an EEPROM after a PCI reset. See

Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications.

Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant, GPI4, GPO4,

MFUNC5

N11

P11

I/O

socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ.

See Section 4.30, Multifunction Routing Register, for configuration details.

MFUNC6

M11

R11

I/O

Multifunction terminal 6. MFUNC6 can be configured as a PCI

CLKRUN

or a parallel IRQ. See

Section 4.30, Multifunction Routing Register, for configuration details.

Ring indicate out and power management event output. Terminal provides an output for

RI_OUT/PME

ring-indicate or PME signals.

Speaker output. SPKROUT is the output to the host system that can carry

SPKR

or CAUDIO

SPKROUT

U10

through the PCI1410 from the PC Card interface. SPKROUT is driven as the exclusive-OR

combination of card SPKR//CAUDIO inputs.

Suspend.

SUSPEND

protects the internal registers from clearing when the

GRST

PRST

SUSPEND

L11

W12

signal is asserted. See Section 3.8.4, Suspend Mode, for details.

2±15

Table 2±12. 16-Bit PC Card Address and Data Terminals

	TERMINAL

NAME		NUMBER			I/O	DESCRIPTION
NAME	GGU		PGE	GHK
	GGU		PGE	GHK

ADDR25	A10		116	B14
ADDR24	D10		113	B15
ADDR23	B11		111	E14
ADDR22	A13		109	A16
ADDR21	B13		107	E17
ADDR20	C12		105	E18
ADDR19	D11		103	E19
ADDR18	E10		100	F18
ADDR17	E12		98	G14
ADDR16	B12		108	D19
ADDR15	A12		110	C15
ADDR14	C13		104	F14
ADDR13	D13		101	G15	O	PC Card address. 16-bit PC Card address lines. ADDR25 is the most significant bit.
ADDR12	A11		112	F13	O
ADDR12	A11		112	F13
ADDR11	F11		95	G19
ADDR10	G12		89	J15
ADDR9	E13		97	G17
ADDR8	E11		99	F19
ADDR7	B10		115	C14
ADDR6	C9		118	A14
ADDR5	A9		120	C13
ADDR4	D8		121	B13
ADDR3	A8		124	C12
ADDR2	C7		127	A11
ADDR1	D7		128	B11
ADDR0	A6		129	C11

DATA15	H12		87	J17
DATA14	J13		84	K14
DATA13	J11		82	K17
DATA12	K13		80	K19
DATA11	K10		77	L17
DATA10	B2		144	C8
DATA9	C3		142	A8
DATA8	A3		140	F9	I/O	PC Card data. 16-bit PC Card data lines. DATA15 is the most significant bit.
DATA7	H10		85	J19	I/O
DATA7	H10		85	J19
DATA6	J12		83	K15
DATA5	J10		81	K18
DATA4	K12		79	L14
DATA3	L13		76	L18
DATA2	A2		143	B8
DATA1	B3		141	E9
DATA0	C4		139	C9

2±16

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