Texas Instruments MSP 430 F 423, MSP 430 F 427 INSTALLATION INSTRUCTIONS

MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

DLow Supply-Voltage Range, 1.8 V . . . 3.6 V

DUltralow-Power Consumption:

−Active Mode: 400 A at 1 MHz, 3.0 V

−Standby Mode: 1.6 A

−Off Mode (RAM Retention): 0.1 A

DFive Power-Saving Modes

DWake-Up From Standby Mode in less than 6 s

DFrequency-Locked Loop, FLL+

D16-Bit RISC Architecture, 125-ns Instruction Cycle Time

DThree Independent 16-bit Sigma-Delta A/D Converters with Differential PGA Inputs

D16-Bit Timer_A With Three Capture/Compare Registers

DIntegrated LCD Driver for 128 Segments

DSerial Communication Interface (USART), Asynchronous UART or Synchronous SPI selectable by software

DBrownout Detector

DSupply Voltage Supervisor/Monitor With Programmable Level Detection

DSerial Onboard Programming,

No External Programming Voltage Needed Programmable Code Protection by Security Fuse

DBootstrap Loader in Flash Devices

DFamily Members Include:

− MSP430F423:

8KB + 256B Flash Memory, 256B RAM

− MSP430F425:

16KB + 256B Flash Memory, 512B RAM

− MSP430F427:

32KB + 256B Flash Memory, 1KB RAM

DAvailable in 64-Pin Quad Flat Pack (QFP)

DFor Complete Module Descriptions, Refer to the MSP430x4xx Family User’s Guide, Literature Number SLAU056

description

The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring www.DataSheet4U.com different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s.

The MSP430F42x series are microcontroller configurations with three independent 16-bit sigma-delta A/D converters, each with an integrated differential programmable gain amplifier input stage. Also included is a built-in 16-bit timer, 128 LCD segment drive capability, hardware multiplier and 14 I/O pins.

Typical applications include high resolution applications such as handheld metering equipment, weigh scales and energy meters.

	AVAILABLE OPTIONS
		PACKAGED DEVICES
TA
		PLASTIC 64-PIN QFP
		(PM)

MSP430F423IPM −40 °C to 85°C MSP430F425IPM MSP430F427IPM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.	Copyright 2004 Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

pin designation{

	AV	DV	AV P2.3/SVSIN P2.4/UTXD0 P2.5/URXD0 RST/NMI TCK TMS TDI/TCLK TDO/TDI	P1.0/TA0 P1.1/TA0/MCLK	P1.2/TA1/S31 P1.3/SVSOUT/S30	P1.4/S29
	CC	SS	SS
DVCC	64 63		62 61 60 59 58 57 56 55 54 53 52 51 50 49				P1.5/TACLK/ACLK/S28
	1					48
A0.0+	2					47	P1.6/SIMO0/S27
A0.0−	3					46	P1.7/SOMI0/S26
A1.0+	4					45	P2.0/TA2/S25
A1.0−	5					44	P2.1/UCLK0/S24
A2.0+	6					43	R33
A2.0−	7					42	R23
XIN	8		MSP430F42x			41	R13
XOUT	9					40	R03
VREF	10					39	COM3
P2.2/STE0	11					38	COM2
S0	12					37	COM1
S1	13					36	COM0
S2	14					35	S23
S3	15					34	S22
S4	16					33	S21
	17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

†Open connection recommended for all unused analog inputs.

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MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

functional block diagram

XIN XOUT

P1

P2

DVCC

DVSS AVCC AVSS RST/NMI

8

6

Oscillator

ACLK

32KB Flash

1KB RAM

I/O Port 1/2

USART0

FLL+

SMCLK

14 I/Os,

UART or

16KB Flash

512B RAM

with

Interrupt

SPI

8KB Flash

256B RAM

Capability

Function

MCLK
			MAB,
	Test	MAB,MAB,16 Bit16-Bit	4 Bit
	JTAG
CPU			MCB
Incl. 16 Reg.	Emulation Module
		MDB,MDB,16 Bit16-Bit	Conv
			Bus	MDB, 8 Bit
4

TMS

TCK

Hardware

Watchdog

Timer_A3

SD16

POR/

Basic

LCD

Multiplier

Timer

SVS/

Timer 1

128

Three 16-bit

TDI/TCLK

MPY, MPYS

3 CC Reg

Brownout

Segments

Sigma-Delta

15/16-Bit

1 Interrupt

1,2,3,4 MUX

MAC,MACS

A/D

TDO/TDI

Vector

Converters

f

LCD

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3

MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

			MSP430F42x Terminal Functions
TERMINAL
PN		I/O	DESCRIPTION
NAME	NO.
DVCC	1		Digital supply voltage, positive terminal. Supplies all digital parts.
A0.0+	2	I	Internal connection to SD16 Channel 0, input 0 +. (see Note 1)
A0.0−	3	I	Internal connection to SD16 Channel 0, input 0 −. (see Note 1)
A1.0+	4	I	Internal connection to SD16 Channel 1, input 0 +. (see Note 1)
A1.0−	5	I	Internal connection to SD16 Channel 1, input 0 −. (see Note 1)
A2.0+	6	I	Internal connection to SD16 Channel 2, input 0 +. (see Note 1)
A2.0−	7	I	Internal connection to SD16 Channel 2, input 0 −. (see Note 1)
XIN	8	I	Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT	9	O	Output terminal of crystal oscillator XT1
VREF	10	I/O	Input for an external reference voltage / internal reference voltage output (can be used as mid-voltage)
P2.2/STE0	11	I/O	General-purpose digital I/O / slave transmit enable—USART0/SPI mode
S0	12	O	LCD segment output 0
S1	13	O	LCD segment output 1
S2	14	O	LCD segment output 2
S3	15	O	LCD segment output 3
S4	16	O	LCD segment output 4
S5	17	O	LCD segment output 5
S6	18	O	LCD segment output 6
S7	19	O	LCD segment output 7
S8	20	O	LCD segment output 8
S9	21	O	LCD segment output 9
S10	22	O	LCD segment output 10
S11	23	O	LCD segment output 11
S12	24	O	LCD segment output 12
S13	25	O	LCD segment output 13
S14	26	O	LCD segment output 14
S15	27	O	LCD segment output 15
S16	28	O	LCD segment output 16
S17	29	O	LCD segment output 17
S18	30	O	LCD segment output 18
S19	31	O	LCD segment output 19
S20	32	O	LCD segment output 20
S21	33	O	LCD segment output 21
S22	34	O	LCD segment output 22
S23	35	O	LCD segment output 23
COM0	36	O	Common output, COM0−3 are used for LCD backplanes.
COM1	37	O	Common output, COM0−3 are used for LCD backplanes.
COM2	38	O	Common output, COM0−3 are used for LCD backplanes.
COM3	39	O	Common output, COM0−3 are used for LCD backplanes.
R03	40	I	Input port of fourth positive (lowest) analog LCD level (V5)

NOTE 1: Open connection recommended for all unused analog inputs.

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					MSP430F42x
					MIXED SIGNAL MICROCONTROLLER
					SLAS421 − APRIL 2004
					MSP430F42x Terminal Functions (Continued)
		TERMINAL
		PN		I/O	DESCRIPTION
		NAME	NO.
	R13		41	I	Input port of third most positive analog LCD level (V4 or V3)
	R23		42	I	Input port of second most positive analog LCD level (V2)
	R33		43	O	Output port of most positive analog LCD level (V1)
	P2.1/UCLK0/S24		44	I/O	General-purpose digital I/O / external clock input-USART0/UART or SPI mode, clock output—USART0/SPI
					mode / LCD segment output 24 (See Note 1)
	P2.0/TA2/S25		45	I/O	General-purpose digital I/O / Timer_A Capture: CCI2A input, Compare: Out2 output / LCD segment output
					25 (See Note 1)
	P1.7/SOMI0/S26		46	I/O	General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 26
					(See Note 1)
	P1.6/SIMO0/S27		47	I/O	General-purpose digital I/O / slave in/master out of USART0/SPI mode / LCD segment output 27
					(See Note 1)
	P1.5/TACLK/		48	I/O	General-purpose digital I/O / Timer_A and SD16 clock signal TACLK input / ACLK output (divided by 1,
	ACLK/S28				2, 4, or 8) / LCD segment output 28 (See Note 1)
	P1.4/S29		49	I/O	General-purpose digital I/O / LCD segment output 29 (See Note 1)
	P1.3/SVSOUT/		50	I/O	General-purpose digital I/O / SVS: output of SVS comparator / LCD segment output 30 (See Note 1)
	S30
	P1.2/TA1/S31		51	I/O	General-purpose digital I/O / Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output / LCD segment
					output 31 (See Note 1)
	P1.1/TA0/MCLK		52	I/O	General-purpose digital I/O / Timer_A, Capture: CCI0B input / MCLK output.
					Note: TA0 is only an input on this pin / BSL receive
	P1.0/TA0		53	I/O	General-purpose digital I/O / Timer_A, Capture: CCI0A input, Compare: Out0 output / BSL transmit
	TDO/TDI		54	I/O	Test data output port. TDO/TDI data output or programming data input terminal.
	TDI/TCLK		55	I	Test data input or test clock input. The device protection fuse is connected to TDI.
	TMS		56	I	Test mode select. TMS is used as an input port for device programming and test.
	TCK		57	I	Test clock. TCK is the clock input port for device programming and test.
			58	I	Reset input or nonmaskable interrupt input port
	RST/NMI
	P2.5/URXD0		59	I/O	General-purpose digital I/O / receive data in—USART0/UART mode
	P2.4/UTXD0		60	I/O	General-purpose digital I/O / transmit data out—USART0/UART mode
	P2.3/SVSIN		61	I/O	General-purpose digital I/O / Analog input to brownout, supply voltage supervisor
	AVSS		62		Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, FLL+, and LCD
					resistive divider circuitry.
	DVSS		63		Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
					AVCC/AVSS.
	AVCC		64		Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, FLL+, and LCD
					resistive divider circuitry; must not power up prior to DVCC.
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

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5

MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

instruction set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.

Program Counter	PC/R0
Stack Pointer	SP/R1
	SR/CG1/R2
Status Register
Constant Generator	CG2/R3
	R4
General-Purpose Register
	R5
General-Purpose Register
General-Purpose Register	R6
	R7
General-Purpose Register
General-Purpose Register	R8
	R9
General-Purpose Register
General-Purpose Register	R10
	R11
General-Purpose Register
General-Purpose Register	R12
	R13
General-Purpose Register
General-Purpose Register	R14
	R15
General-Purpose Register

Table 1. Instruction Word Formats

Dual operands, source-destination	e.g. ADD	R4,R5	R4 + R5 −−−> R5
Single operands, destination only	e.g. CALL	R8	PC −−>(TOS), R8−−> PC
Relative jump, un/conditional	e.g. JNE		Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

	ADDRESS MODE		S	D	SYNTAX	EXAMPLE	OPERATION
	Register		D	D	MOV Rs,Rd	MOV R10,R11	R10 −−> R11
	Indexed		D	D	MOV X(Rn),Y(Rm)	MOV 2(R5),6(R6)	M(2+R5)−−> M(6+R6)
	Symbolic (PC relative)		D	D	MOV EDE,TONI		M(EDE) −−> M(TONI)
	Absolute		D	D	MOV &MEM,&TCDAT		M(MEM) −−> M(TCDAT)
	Indirect		D		MOV @Rn,Y(Rm)	MOV @R10,Tab(R6)	M(R10) −−> M(Tab+R6)
	Indirect		D		MOV @Rn+,Rm	MOV @R10+,R11	M(R10) −−> R11
	autoincrement						R10 + 2−−> R10
	Immediate		D		MOV #X,TONI	MOV #45,TONI	#45 −−> M(TONI)
NOTE: S = source		D = destination

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MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

DActive mode AM;

−All clocks are active

DLow-power mode 0 (LPM0);

−CPU is disabled

ACLK and SMCLK remain active, MCLK is available to modules

FLL+ Loop control remains active

DLow-power mode 1 (LPM1);

−CPU is disabled

ACLK and SMCLK remain active, MCLK is available to modules

FLL+ Loop control is disabled

DLow-power mode 2 (LPM2);

−CPU is disabled

MCLK and FLL+ loop control and DCOCLK are disabled

DCO’s dc-generator remains enabled

ACLK remains active

DLow-power mode 3 (LPM3);

−CPU is disabled

MCLK, FLL+ loop control, and DCOCLK are disabled

DCO’s dc-generator is disabled

ACLK remains active

DLow-power mode 4 (LPM4);

−CPU is disabled ACLK is disabled

MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled

Crystal oscillator is stopped

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7

MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the ROM with an address range 0FFFFh − 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

	INTERRUPT SOURCE	INTERRUPT FLAG	SYSTEM INTERRUPT	WORD ADDRESS	PRIORITY
	Power-up	WDTIFG	Reset	0FFFEh	15, highest
	External Reset	KEYV
	Watchdog	(see Note 1)
	Flash memory
	PC Out-of-Range (see Note 4)
	NMI	NMIIFG (see Notes 1 and 3)	(Non)maskable
	Oscillator Fault	OFIFG (see Notes 1 and 3)	(Non)maskable	0FFFCh	14
	Flash memory access violation	ACCVIFG (see Notes 1 and 3)	(Non)maskable
				0FFFAh	13
		SD16CCTLx SD16OVIFG,
	SD16	SD16CCTLx SD16IFG	Maskable	0FFF8h	12
		(see Notes 1 and 2)
				0FFF6h	11
	Watchdog Timer	WDTIFG	Maskable	0FFF4h	10
	USART0 Receive	URXIFG0	Maskable	0FFF2h	9
	USART0 Transmit	UTXIFG0	Maskable	0FFF0h	8
				0FFEEh	7
	Timer_A3	TACCR0 CCIFG (see Note 2)	Maskable	0FFECh	6
		TACCR1 and TACCR2
	Timer_A3	CCIFGs, and TACTL TAIFG	Maskable	0FFEAh	5
		(see Notes 1 and 2)
	I/O port P1 (eight flags)	P1IFG.0 to P1IFG.7	Maskable	0FFE8h	4
		(see Notes 1 and 2)
				0FFE6h	3
				0FFE4h	2
	I/O port P2 (eight flags)	P2IFG.0 to P2IFG.7	Maskable	0FFE2h	1
		(see Notes 1 and 2)
	Basic Timer1	BTIFG	Maskable	0FFE0h	0, lowest

NOTES: 1. Multiple source flags

2.Interrupt flags are located in the module.

3.(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.

4.A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h-01FFh).

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MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

interrupt enable 1 and 2

Address

7

6

5

4

3

2

1

0

0h

UTXIE0

URXIE0

ACCVIE

NMIIE

OFIE

WDTIE

rw–0

rw–0

rw–0

rw–0

rw–0

rw–0

WDTIE:

Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog

timer is configured in interval timer mode.

OFIE:

Oscillator-fault-interrupt enable

NMIIE:

Nonmaskable-interrupt enable

ACCVIE:

Flash access violation interrupt enable

URXIE0:

USART0: UART and SPI receive-interrupt enable

UTXIE0:

USART0: UART and SPI transmit-interrupt enable

Address

7

6

5

4

3

2

1

0

1h

BTIE

rw-0

BTIE:

Basic Timer1 interrupt enable

interrupt flag register 1 and 2

Address

7

6

5

4

3

2

1

0

02h

UTXIFG0

URXIFG0

NMIIFG

OFIFG

WDTIFG

rw–1

rw–0

rw–0

rw–1

rw–0

WDTIFG:

Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC

power up or a reset condition at the RST/NMI pin in reset mode.

OFIFG:

Flag set on oscillator fault

NMIIFG:

Set via

RST/NMI pin

URXIFG0:

USART0: UART and SPI receive flag

UTXIFG0:

USART0: UART and SPI transmit flag

Address

7

6

5

4

3

2

1

0

3h

BTIFG

rw-0

BTIFG:

Basic Timer1 interrupt flag

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9

MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

module enable registers 1 and 2

Address	7	6		5	4	3	2	1	0
04h	UTXE0		URXE0
			USPIE0
	rw–0	rw–0

URXE0:

USART0: UART mode receive enable

UTXE0:

USART0: UART mode transmit enable

USPIE0:

USART0: SPI mode transmit and receive enable

Address

7

6

5

4

3

2

1

0

05h

Legend: rw:

Bit Can Be Read and Written

rw-0:

Bit Can Be Read and Written. It Is Reset by PUC.

SFR Bit Not Present in Device

memory organization

		MSP430F423	MSP430F425	MSP430F427
Memory	Size	8KB	16KB	32KB
Interrupt vector	Flash	0FFFFh − 0FFE0h	0FFFFh − 0FFE0h	0FFFFh − 0FFE0h
Code memory	Flash	0FFFFh − 0E000h	0FFFFh − 0C000h	0FFFFh − 08000h
Information memory	Size	256 Byte	256 Byte	256 Byte
		010FFh − 01000h	010FFh − 01000h	010FFh − 01000h
Boot memory	Size	1kB	1kB	1kB
		0FFFh − 0C00h	0FFFh − 0C00h	0FFFh − 0C00h
RAM	Size	256 Byte	512 Byte	1KB
		02FFh − 0200h	03FFh − 0200h	05FFh − 0200h
Peripherals	16-bit	01FFh − 0100h	01FFh − 0100h	01FFh − 0100h
	8-bit	0FFh − 010h	0FFh − 010h	0FFh − 010h
	8-bit SFR	0Fh − 00h	0Fh − 00h	0Fh − 00h

bootstrap loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.

BSL Function	PM Package Pins
Data Transmit	53 - P1.0
Data Receive	52 - P1.1

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MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

DFlash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.

DSegments 0 to n may be erased in one step, or each segment may be individually erased.

DSegments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory.

DNew devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use.

	8KB	16KB	32KB
	0FFFFh	0FFFFh	0FFFFh
				Segment 0
	0FE00h	0FE00h	0FE00h	With Interrupt Vectors
	0FDFFh	0FDFFh	0FDFFh
				Segment 1
	0FC00h	0FC00h	0FC00h
	0FBFFh	0FBFFh	0FBFFh	Segment 2
	0FA00h	0FA00h	0FA00h
	0F9FFh	0F9FFh	0F9FFh

Main Memory

0E400h	0C400h	08400h
0E3FFh	0C3FFh	083FFh		Segment n−1
0E200h	0C200h	08200h
0E1FFh	0C1FFh	081FFh		Segment n
0E000h	0C000h	08000h
010FFh	010FFh	010FFh		Segment A
01080h	01080h	01080h			Information Memory
0107Fh	0107Fh	0107Fh
				Segment B
01000h	01000h	01000h

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11

MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421 − APRIL 2004

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature number SLAU056.

oscillator and system clock

The clock system in the MSP430F42x family of devices is supported by the FLL+ module that includes support for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:

DAuxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.

DMain clock (MCLK), the system clock used by the CPU.

DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.

brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not

have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).

digital I/O

There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external pins):

DAll individual I/O bits are independently programmable.

DAny combination of input, output, and interrupt conditions is possible.

DEdge-selectable interrupt input capability for all the eight bits of port P1 and six bits of P2.

DRead/write access to port-control registers is supported by all instructions.

NOTE:

Six bits of port P2, P2.0 to P2.5, are available on external pins - but all control and data bits for port P2 are implemented.

Basic Timer1

The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module.

LCD drive

The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.

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