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MSP430P325 |
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MIXED SIGNAL MICROCONTROLLER |
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SLAS164A ± FEBRUARY 1998 ± REVISED MARCH 2000 |
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D Low Supply Voltage Range, 2.7 V ± 5.5 V |
D Integrated 12+2 Bit A/D Converter |
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D Low Operation Current, 3 mA at 1 MHz, |
D |
Family Members Include: |
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3 V |
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± MSP430P325, 16KB OTP, 512 Byte RAM |
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D Ultralow Power Consumption (Standby |
D EPROM Version Available for Prototyping: |
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Mode Down to 0.1 mA) |
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PMS430E325 |
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D Five Power-Saving Modes |
D |
Serial Onboard Programming |
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D Wakeup From Standby Mode in 6 ms |
D Programmable Code Protection by Security |
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D 16-Bit RISC Architecture, 300 ns Instruction |
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Fuse |
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Cycle Time |
D Avaliable in 64 Pin Quad Flatpack (QFP), |
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D Single Common 32 kHz Crystal, Internal |
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68 Pin Plastic J-Leaded Chip Carrier |
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System Clock up to 3.3 MHz |
(PLCC), 68 Pin J-Leaded Ceramic Chip |
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Carrier (JLCC) Package (EPROM Version) |
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D Integrated LCD Driver for up to 84 |
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Segments |
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description
The Texas Instruments MSP430 is an ultralow-power mixed-signal microcontroller family consisting of several devices which feature different sets of modules targeted to various applications. The microcontroller is designed to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated registers on the CPU, and a constant generator, the MSP430 achieves maximum code efficiency. The digitallycontrolled oscillator, together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode to active mode in less than 6 ms.
PG Package
(TOP VIEW)
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AV |
A1 |
A0 |
XBUF |
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RST/NMI |
TCK |
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TMS |
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TDI/VPP |
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TDO/TDI |
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COM3 |
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COM2 |
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COM1 |
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SS |
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64 636261 60 595857 56 55 545352 |
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AVCC |
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1 |
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COM0 |
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DVCC |
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S20/O20/CMPI |
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SVCC |
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S19/O19 |
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Rext |
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48 |
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S18/O18 |
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A2 |
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5 |
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S17/O17 |
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A3 |
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46 |
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S16/O16 |
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A4 |
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45 |
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S15/O15 |
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A5 |
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44 |
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S14/O14 |
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Xin |
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9 |
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43 |
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S13/O13 |
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Xout/TCLK |
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10 |
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42 |
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S12/O12 |
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CIN |
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41 |
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S11/O11 |
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TP0.0 |
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40 |
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S10/O10 |
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TP0.1 |
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39 |
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S9/O9 |
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TP0.2 |
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S8/O8 |
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TP0.3 |
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S7/O7 |
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TP0.4 |
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S6/O6 |
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TP0.5 |
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35 |
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S5/O5 |
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P0.0 |
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S4/O4 |
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P0.1/RXD |
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19 |
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33 |
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S3/O3 |
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20 2122 23 2425 26 27282930 31 32 |
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P0.2/TXD |
P0.3 |
P0.4 |
P0.5 |
P0.6 |
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P0.7 |
R33 |
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R23 |
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R13 |
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R03 |
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S0 |
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S1 |
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S2/O2 |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A ± FEBRUARY 1998 ± REVISED MARCH 2000
description (continued)
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. The MSP430x32x offers an integrated 12+2 bit A/D converter with six multiplexed inputs.
AVAILABLE OPTIONS
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PACKAGED DEVICES |
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TA |
PLASTIC |
PLASTIC |
PLASTIC |
CERAMIC |
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64-PIN QFP |
64-PIN QFP |
68-PIN PLCC |
68-PIN JLCC |
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(PG) |
(PM) |
(FN) |
(FZ) |
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±40°C to 85°C |
MSP430P325IPG |
MSP430P325IPM |
MSP430P325IFN |
Ð |
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25°C |
Ð |
Ð |
Ð |
PMS430E325FZ |
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functional block diagram
XIN Xout/TCLK |
XBUF |
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RST/NMI |
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P0.0 |
P0.7 |
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Oscillator |
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ACLK |
8/16 kB ROM |
256/512 B |
Power-on- |
8 b Timer/ |
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I/O Port |
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FLL |
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16 kB OTP |
RAM |
Reset |
Counter |
TXD |
8 I/O's, All With |
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System Clock |
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MCLK |
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Serial Protocol |
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Interr. Cap. |
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'C': ROM |
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Support |
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3 Int. Vectors |
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TDI/VPP |
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'P': OTP |
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RXD |
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TDO/TDI |
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MAB, 16 Bit |
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MAB, 4 Bit |
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CPU |
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Test |
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MCB |
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Incl. 16 Reg. |
JTAG |
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MDB, 16 Bit |
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MDB, 8 Bit |
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Bus |
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Conv |
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TMS |
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TCK |
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ADC |
Watchdog |
Timer/Port |
Basic |
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LCD |
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12 + 2 Bit |
Timer |
Applications: |
Timer1 |
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84 Segments |
Com0±3 |
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6 Channels |
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A/D Conv. |
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15/16 Bit |
f LCD |
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S0±19/O2±19 |
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Current S. |
Timer, O/P |
1, 2, 3, 4 MUX |
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S20/O20CMPI |
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CMPI |
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6 |
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6 |
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A0±5 |
SVCC |
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TP0.0±5 |
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R33 |
R13 |
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Rext |
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CIN |
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R23 |
R03 |
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2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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MSP430P325 |
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MIXED SIGNAL MICROCONTROLLER |
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SLAS164A ± FEBRUARY 1998 ± REVISED MARCH 2000 |
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Terminal Functions |
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TERMINAL |
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I/O |
DESCRIPTION |
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NAME |
NO. |
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AVCC |
1 |
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Positive analog supply voltage |
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AVSS |
63 |
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Analog ground reference |
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A0 |
61 |
I |
Analog-to-digital converter input port 0 or digital input port 0 |
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A1 |
62 |
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Analog-to-digital converter input port 1 or digital input port 1 |
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A2±A5 |
5±8 |
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Analog-to-digital converter inputs ports 2±5 or digital inputs ports 2±5 |
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CIN |
11 |
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Input used as enable of counter TPCNT1 ± Timer/Port |
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COM0±3 |
51±54 |
O |
Common outputs, used for LCD backplanes ± LCD |
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DVCC |
2 |
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Positive digital supply voltage |
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DVSS |
64 |
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Digital ground reference |
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P0.0 |
18 |
I/O |
General-purpose digital I/O |
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P0.1/RXD |
19 |
I/O |
General-purpose digital I/O, receive digital input port, 8-Bit Timer/Counter |
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P0.2/TXD |
20 |
I/O |
General-purpose digital I/O, transmit data output port, 8-Bit Timer/Counter |
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P0.3±P0.7 |
21±25 |
I/O |
Five general-purpose digital I/Os, bit 3 to bit 7 |
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Rext |
4 |
I |
Programming resistor input of internal current source |
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59 |
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Reset input or non-maskable interrupt input |
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RST/NMI |
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R03 |
29 |
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Input of fourth positive analog LCD level (V4) ± LCD |
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R13 |
28 |
I |
Input of third positive analog LCD level (V3) ± LCD |
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R23 |
27 |
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Input of second positive analog LCD level (V2) ± LCD |
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R33 |
26 |
O |
Output of first positive analog LCD level (V1) ± LCD |
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SVCC |
3 |
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Switched AVCC to analog-to-digital converter |
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S0 |
30 |
O |
Segment line S0 ± LCD |
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S1 |
31 |
O |
Segment line S1 ± LCD |
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S2±S5/O2±O5 |
32±35 |
O |
Segment lines S2 to S5 or digital output ports O2±O5, group 1 ± LCD |
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S20/O20/CMPI |
50 |
I/O |
Segment line S20 can be used as comparator input port CMPI ± Timer/Port |
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S6±S9/O6±O9 |
36±39 |
O |
Segment lines S6 to S9 or digital output ports O6±O9, group 2 ± LCD |
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S10±S13/O10±O13 |
40±43 |
O |
Segment lines S10 to S13 or digital output ports O10±O13, group 3 ± LCD |
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S14±S17/O14±O17 |
44±47 |
O |
Segment lines S14 to S17 or digital output ports O14 to O17, group 4 ± LCD |
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S18-S19/O18-O19 |
48, 49 |
O |
Segment lines S18 and S19 or digital output port O18 and O19, group 5 ± LCD |
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TCK |
58 |
I |
Test clock, clock input terminal for device programming and test |
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TDO/TDI |
55 |
I/O |
Test data output, data output terminal or data input during programming |
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TDI/VPP |
56 |
I |
Test data input, data input terminal or input of programming voltage |
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TMS |
57 |
I |
Test mode select, input terminal for device programming and test |
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TP0.0 |
12 |
O |
General-purpose 3-state digital output port, bit 0 ± Timer/Port |
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TP0.1 |
13 |
O |
General-purpose 3-state digital output port, bit 1 ± Timer/Port |
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TP0.2 |
14 |
O |
General-purpose 3-state digital output port, bit 2 ± Timer/Port |
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TP0.3 |
15 |
O |
General-purpose 3-state digital output port, bit 3 ± Timer/Port |
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TP0.4 |
16 |
O |
General-purpose 3-state digital output port, bit 4 ± Timer/Port |
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TP0.5 |
17 |
I/O |
General-purpose digital input/output port, bit 5 ± Timer/Port |
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XBUF |
60 |
O |
Clock signal output of system clock MCLK or crystal clock ACLK |
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Xin |
9 |
I |
Input terminal of crystal oscillator |
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Xout/TCLK |
10 |
I/O |
Output terminal of crystal oscillator or test clock input |
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A ± FEBRUARY 1998 ± REVISED MARCH 2000
short-form description
processing unit
The processing unit is based on a consistent and orthogonally-designed CPU and instruction set. This design structure results in a RISC-like architecture, highly transparent to the application development, and it is distinguished by ease of programming. All operations other than program-flow instructions are consequently performed as register operations in conjunction with seven addressing modes for source and four modes for destination operand.
Program Counter |
PC/R0 |
CPU
Sixteen registers are located inside the CPU, providing reduced instruction execution time. This reduces a register-register operation execution time to one cycle of the processor frequency.
Four of the registers are reserved for special use as a program counter, a stack pointer, a status register, and a constant generator. The remaining registers are available as general-purpose registers.
Peripherals are connected to the CPU using a data address and control bus and can be handled easily with all instructions for memory manipulation.
instruction set
Stack Pointer |
SP/R1 |
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SR/CG1/R2 |
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Status Register |
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CG2/R3 |
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Constant Generator |
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R4 |
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General-Purpose Register |
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R5 |
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General-Purpose Register |
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General-Purpose Register |
R14 |
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R15 |
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General-Purpose Register |
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The instruction set for this register-register architecture provides a powerful and easy-to-use assembler language. The instruction set consists of 51 instructions with three formats and seven addressing modes. Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are listed in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination |
e.g. ADD R4, R5 |
R4 + R5 → R5 |
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Single operands, destination only |
e.g. CALL R8 |
PC → (TOS), R8 → PC |
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Relative jump, un-/conditional |
e.g. JNE |
Jump-on equal bit = 0 |
Each instruction that operates on word and byte data is identified by the suffix B.
Examples: |
Instructions for word operation |
Instructions for byte operation |
||
|
MOV |
EDE, TONI |
MOV.B |
EDE, TONI |
|
ADD |
#235h, &MEM |
ADD.B |
#35h, &MEM |
|
PUSH |
R5 |
PUSH.B |
R5 |
|
SWPB |
R5 |
Ð |
|
4 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A ± FEBRUARY 1998 ± REVISED MARCH 2000
Table 2. Address Mode Descriptions
ADDRESS MODE |
|
s |
|
d |
SYNTAX |
EXAMPLE |
OPERATION |
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Register |
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√ |
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√ |
MOV Rs, Rd |
MOV R10, R11 |
R10 → R11 |
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Indexed |
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√ |
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√ |
MOV X(Rn), Y(Rm) |
MOV 2(R5), 5(R6) |
M(2 + R5) → M(6 + R6) |
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Symbolic (PC relative) |
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√ |
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√ |
MOV EDE, TONI |
|
M(EDE) → M(TONI) |
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Absolute |
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√ |
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√ |
MOV &MEM, &TCDAT |
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M(MEM) → M(TCDAT) |
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Indirect |
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√ |
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MOV @Rn, Y(Rm) |
MOV @R10, Tab(R6) |
M(R10) → M(Tab + R6) |
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Indirect autoincrement |
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√ |
|
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MOV @Rn+, RM |
MOV @R10+, R11 |
M(R10) → R11, R10 + 2 → R10 |
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Immediate |
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√ |
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MOV #X, TONI |
MOV #45, TONI |
#45 → M(TONI) |
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NOTE: s = source |
d = destination |
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Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and calls. The full use of this programming capability permits a program structure different from conventional 8- and 16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks instead of using flag type programs for flow control.
operation modes and interrupts
The MSP430 operating modes support various advanced requirements for ultralow power and ultralow energy consumption. This is achieved by the intelligent management of the operations during the different module operation modes and CPU states. The requirements are fully supported during interrupt event handling. An interrupt event awakens the system from each of the various operating modes and returns with the RETI instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK. ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock.
The software can configure five operating modes:
DActive mode (AM). The CPU is enabled with different combinations of active peripheral modules.
DLow power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals are active, and loop control for MCLK is active.
DLow power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals are active, and loop control for MCLK is inactive.
DLow power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active, and MCLK and loop control for MCLK are inactive.
DLow power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active, MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO) (³MCLK generator) is switched off.
DLow power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive (crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO is switched off.
The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or enabled. However, some peripheral current-saving functions are accessed through the state of local register bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned on or off using one register bit.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
5 |
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A ± FEBRUARY 1998 ± REVISED MARCH 2000
operation modes and interrupts (continued)
The most general bits that influence current consumption and support fast turnon from low-power operating modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator: SCG1, SCG0, OscOff, and CPUOff.
15 |
9 |
8 |
7 |
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0 |
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Reserved For Future |
|
V |
SCG1 |
SCG0 |
OscOff |
CPUOff |
GIE |
N |
Z |
C |
|||
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Enhancements |
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rw-0
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
INTERRUPT SOURCE |
INTERRUPT FLAG |
SYSTEM INTERRUPT |
WORD ADDRESS |
PRIORITY |
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Power-up, external reset, watchdog |
WDTIFG (see Note1) |
Reset |
0FFFEh |
15, highest |
|
NMI, oscillator fault |
NMIIFG (see Notes 1 and 3) |
Non-maskable, |
0FFFCh |
14 |
|
OFIFG (see Notes 1 and 4) |
(Non)-maskable |
||||
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Dedicated I/O P0.0 |
P0.0IFG |
Maskable |
0FFFAh |
13 |
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Dedicated I/O P0.1 or 8-Bit Timer/Counter |
P0.1IFG |
Maskable |
0FFF8h |
12 |
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RXD |
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0FFF6h |
11 |
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Watchdog Timer |
WDTIFG |
Maskable |
0FFF4h |
10 |
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0FFF2h |
9 |
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0FFF0h |
8 |
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0FFEEh |
7 |
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0FFECh |
6 |
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ADC |
ADCIFG |
Maskable |
0FFEAh |
5 |
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Timer/Port |
RC1FG, RC2FG, EN1FG |
Maskable |
0FFE8h |
4 |
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(see Note 2) |
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0FFE6h |
3 |
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0FFE4h |
2 |
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Basic Timer1 |
BTIFG |
Maskable |
0FFE2h |
1 |
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I/O port 0, P0.2±7 |
P0.27IFG (see Note 1) |
Maskable |
0FFE0h |
0, lowest |
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NOTES: 1. Multiple source flags
2.Timer/Port interrupt flags are located in the T/P registers
3.Non-maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.
4.(Non)-maskable: the individual interrupt enable bit can disable on interrupt event, but the general interrupt enable bit cannot.
6 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A ± FEBRUARY 1998 ± REVISED MARCH 2000
operation modes and interrupts (continued)
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple SW access is provided with this arrangement.
interrupt enable 1 and 2
Address |
7 |
6 |
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5 |
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4 |
3 |
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2 |
1 |
0 |
|||
0h |
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P0IE.1 |
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P0IE.0 |
OFIE |
WDTIE |
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rw-0 |
rw-0 |
rw-0 |
rw-0 |
||
WDTIE: |
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Watchdog Timer enable signal |
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||||||
OFIE: |
|
Oscillator fault enable signal |
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P0IE.0: |
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Dedicated I/O P0.0 |
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P0IE.1: |
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P0.1 or 8-Bit Timer/Counter, RXD |
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||||||
Address |
7 |
6 |
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5 |
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4 |
3 |
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2 |
1 |
0 |
|||
01h |
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BTIE |
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TPIE |
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ADIE |
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rw-0 |
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rw-0 |
rw-0 |
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ADIE: |
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A/D converter enable signal |
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|||||
TPIE: |
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Timer/Port enable signal |
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BTIE: |
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Basic Timer1 enable signal |
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interrupt flag register 1 and 2 |
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Address |
7 |
6 |
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5 |
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4 |
3 |
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2 |
1 |
0 |
|||
02h |
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NMIIFG |
P0IFG.1 |
|
P0IFG.0 |
OFIFG |
WDTIFG |
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rw-0 |
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rw-0 |
rw-0 |
rw-1 |
rw-0 |
||
WDTIFG: |
|
Set on overflow or security key violation |
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||||||||
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or |
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Reset on VCC power on or reset condition at |
RST/NMI-pin |
|
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||||||||
OFIFG: |
|
Flag set on oscillator fault |
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P0.0IFG: |
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Dedicated I/O P0.0 |
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P0.1IFG: |
|
P0.1 or 8-Bit Timer/Counter, RXD |
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||||||
NMIIFG: |
|
Signal at |
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RST/NMI-pin |
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||||||
Address |
7 |
6 |
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5 |
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4 |
3 |
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2 |
1 |
0 |
|||
03h |
|
BTIFG |
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ADIFG |
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rw |
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rw-0 |
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BTIFG |
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Basic Timer1 flag |
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|||||
ADFIG |
|
Analog-to-digital converter flag |
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|
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
7 |
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A ± FEBRUARY 1998 ± REVISED MARCH 2000
operation modes and interrupts (continued)
module enable register 1 and 2
Address |
7 |
6 |
5 |
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4 |
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3 |
2 |
1 |
0 |
04h |
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Address |
7 |
6 |
5 |
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4 |
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3 |
2 |
1 |
0 |
05h |
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Legend |
rw: |
Bit can be read and written. |
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||
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rw-0: |
Bit can be read and written. It is reset by PUC. |
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SFR bit not present in device. |
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memory organization
MSP430P325
PMS430E325
FFFFh
Int. Vector
FFE0h
FFDFh
16 kB OTP or EPROM
C000h
03FFh |
512B RAM |
|
0200h |
||
|
||
01FFh |
|
|
16b Per. |
||
0100h |
||
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00FFh |
8b Per. |
|
0010h |
||
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000Fh |
SFR |
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0000h |
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8 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A ± FEBRUARY 1998 ± REVISED MARCH 2000
peripherals
Peripherals connect to the CPU through data, address, and control busses and can be handled easily with all instructions for memory manipulation.
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog |
|
Watchdog Timer control |
|
WDTCTL |
0120h |
|
|
|
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|
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ADC |
|
Data register |
|
ADAT |
0118h |
|
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Reserved |
|
|
0116h |
|
|
Control register |
|
ACTL |
0114h |
|
|
Input enable register |
|
AEN |
o112h |
|
|
Input register |
|
AIN |
0110h |
|
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|
|
PERIPHERALS WITH BYTE ACCESS |
|
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||
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EPROM |
|
EPROM control |
|
EPCTL |
054h |
|
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Crystal buffer |
|
Crystal buffer control |
|
CBCTL |
053h |
|
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System clock |
|
SCG frequency control |
|
SCFQCTL |
052h |
|
|
SCG frequency integrator |
|
SCFI1 |
051h |
|
|
SCG frequency integrator |
|
SCFI0 |
050h |
|
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Timer/Port |
|
Timer/Port enable |
|
TPE |
04Fh |
|
|
Timer/Port data |
|
TPD |
04Eh |
|
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Timer/Port counter2 |
|
TPCNT2 |
04Dh |
|
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Timer/Port counter1 |
|
TPCNT1 |
04Ch |
|
|
Timer/Port control |
|
TPCTL |
04Bh |
|
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|
8-Bit Timer/Counter |
|
8-Bit Timer/Counter data |
|
TCDAT |
044h |
|
|
8-Bit Timer/Counter preload |
|
TCPLD |
043h |
|
|
8-Bit Timer/Counter control |
|
TCCTL |
042h |
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Basic Timer1 |
|
Basic Timer counter2 |
|
BTCNT2 |
047h |
|
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Basic Timer counter1 |
|
BTCNT1 |
046h |
|
|
Basic Timer control |
|
BTCTL |
040h |
|
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LCD |
|
LCD memory 15 |
|
LCDM15 |
03Fh |
|
|
: |
|
: |
: |
|
|
LCD memory 1 |
|
LCDM1 |
031h |
|
|
LCD control & mode |
|
LCDCTL |
030h |
|
|
|
|
|
|
Port P0 |
|
Port P0 interrupt enable |
|
P0IE |
015h |
|
|
Port P0 interrupt edge select |
|
P0IES |
014h |
|
|
Port P0 interrupt flag |
|
P0IFG |
013h |
|
|
Port P0 direction |
|
P0DIR |
012h |
|
|
Port P0 output |
|
P0OUT |
011h |
|
|
Port P0 input |
|
P0IN |
010h |
|
|
|
|
|
|
Special function |
|
SFR interrupt flag2 |
|
IFG2 |
003h |
|
|
SFR interrupt flag1 |
|
IFG1 |
002h |
|
|
SFR interrupt enable2 |
|
IE2 |
001h |
|
|
SFR interrupt enable1 |
|
IE1 |
000h |
oscillator and system clock
Two clocks are used in the system, the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency. The special design of the oscillator supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected across two terminals without any other external components being required.
The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK are accessible for use by external devices at output terminal XBUF.
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MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A ± FEBRUARY 1998 ± REVISED MARCH 2000
oscillator and system clock (continued)
The controller system clock has to operate with different requirements according to the application and system conditions. Requirements include:
DHigh frequency in order to react quickly to system hardware requests or events
DLow frequency in order to minimize current consumption, EMI, etc.
DStable frequency for timer applications e.g. real-time clock (RTC)
DEnable start-stop operation with a minimum of delay
These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The compromise selected for the MSP430 uses a low-crystal frequency, which is multiplied to achieve the desired nominal operating range:
f(system) = (N+1) × f(crystal)
The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator (DCO) provides immediate start-up capability together with long term crystal stability. The frequency variation of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 µs the maximum possible variation is 0.33 ns. For more precise timing, the FLL can be used forcing longer cycle times, if the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to meet the chosen system frequency over a long period of time.
The start-up operation of the system clock depends on the previous machine state. During a power-up clear (PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after recognition of PUC. Connect operation of the FLL control logic requires the presence of a stable crystal oscillator.
digital I/O
One 8-Bit I/O port (Port0) is implemented. Six control registers give maximum flexibility of digital input/output to the application:
DAll individual I/O bits are programmable independently.
DAny combination of input, output, and interrupt conditions is possible.
DInterrupt processing of external events is fully implemented for all eight bits of port P0.
DProvides read/write access to all registers with all instructions
The six registers are:
D |
Input register |
Contains information at the pins |
D |
Output register |
Contains output information |
D |
Direction register |
Controls direction |
D |
Interrupt flags |
Indicates if interrupt(s) are pending |
D |
Interrupt edge select |
Contains input signal change necessary for interrupt |
D |
Interrupt enable |
Contains interrupt enable pins |
All six registers contain eight bits except for the interrupt flag register and the interrupt enable register. The two LSBs of the interrupt flag and interrupt enable registers are located in the special functions register (SFR). Three interrupt vectors are implemented, one for Port0.0, one for Port0.1, and one commonly used for any interrupt event on Port0.2 to Port0.7. The Port0.1 and Port0.2 pin function is shared with the 8-Bit Timer/Counter.
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