MSP430F155IPM |
MSP430x15x, MSP430x16x, MSP430x161x |
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MIXED SIGNAL MICROCONTROLLER |
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005 |
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DLow Supply-Voltage Range, 1.8 V . . . 3.6 V
DUltralow-Power Consumption:
−Active Mode: 330 A at 1 MHz, 2.2 V
−Standby Mode: 1.1 A
−Off Mode (RAM Retention): 0.2 A
DFive Power-Saving Modes
DWake-Up From Standby Mode in less than 6 s
D16-Bit RISC Architecture, 125-ns Instruction Cycle Time
DThree-Channel Internal DMA
D12-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature
DDual 12-Bit D/A Converters With Synchronization
D16-Bit Timer_A With Three Capture/Compare Registers
D16-Bit Timer_B With Three or Seven Capture/Compare-With-Shadow Registers
DOn-Chip Comparator
DSerial Communication Interface (USART0), Functions as Asynchronous UART or Synchronous SPI or I2CTM Interface
DSerial Communication Interface (USART1), Functions as Asynchronous UART or Synchronous SPI Interface
DSupply Voltage Supervisor/Monitor With Programmable Level Detection
DBrownout Detector
DBootstrap Loader
I2C is a registered trademark of Philips Incorporated.
description
DSerial Onboard Programming,
No External Programming Voltage Needed Programmable Code Protection by Security Fuse
DFamily Members Include: − MSP430F155:
16KB+256B Flash Memory 512B RAM
− MSP430F156:
24KB+256B Flash Memory 1KB RAM
− MSP430F157:
32KB+256B Flash Memory, 1KB RAM
− MSP430F167:
32KB+256B Flash Memory, 1KB RAM
− MSP430F168:
48KB+256B Flash Memory, 2KB RAM
− MSP430F169:
60KB+256B Flash Memory, 2KB RAM
− MSP430F1610:
32KB+256B Flash Memory 5KB RAM
− MSP430F1611:
48KB+256B Flash Memory 10KB RAM
− MSP430F1612:
55KB+256B Flash Memory 5KB RAM
DAvailable in 64-Pin Quad Flat Pack (QFP) and 64-pin QFN (see Available Options)
DFor Complete Module Descriptions, See the
MSP430x1xx Family User’s Guide, Literature Number SLAU049
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s.
The MSP430x15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), I2C, DMA, and 48 I/O pins. In addition, the MSP430x161x series offers extended RAM addressing for memory-intensive applications and large C-stack requirements.
Typical applications include sensor systems, industrial control applications, hand-held meters, etc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION |
DATA information is current as of publication date. |
Copyright |
2002 − 2005, Texas Instruments Incorporated |
Products conform to specifications per the terms of Texas Instruments |
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standard warranty. Production processing does not necessarily include |
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testing of all |
parameters. |
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POST OFFICE BOX 655303 • |
DALLAS, TEXAS 75265 |
1 |
MSP430x15x, MSP430x16x, |
MSP430x161x |
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MIXED SIGNAL MICROCONTROLLER |
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005 |
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AVAILABLE OPTIONS |
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TA |
PACKAGED DEVICES |
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PLASTIC 64-PIN QFP (PM) |
PLASTIC 64-PIN QFN (RTD) |
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MSP430F155IPM |
MSP430F155IRTD† |
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MSP430F156IPM |
MSP430F156IRTD† |
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MSP430F157IPM |
MSP430F157IRTD† |
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MSP430F167IPM |
MSP430F167IRTD† |
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− 40° C to 85° C |
MSP430F168IPM |
MSP430F168IRTD† |
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MSP430F169IPM |
MSP430F169IRTD† |
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MSP430F1610IPM |
MSP430F1610IRTD |
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MSP430F1611IPM |
MSP430F1611IRTD |
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MSP430F1612IPM |
MSP430F1612IRTD |
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† Product Preview
pin designation, MSP430F155, MSP430F156, and MSP430F157
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PM, RTD PACKAGE |
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(TOP VIEW) |
XT2OUT P5.7/TBOUTH/SVSOUT |
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AV |
DV |
AV |
P6.2/A2 |
P6.1/A1 |
P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN |
P5.6/ACLK |
P5.5/SMCLK |
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CC |
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DVCC |
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64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 |
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P6.3/A3 |
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P6.4/A4 |
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P6.5/A5 |
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P6.6/A6/DAC0 |
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P6.7/A7/DAC1/SVSIN |
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VREF+ |
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7 |
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XIN |
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8 |
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41 |
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XOUT |
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VeREF+ |
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VREF− /VeREF− |
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P1.0/TACLK |
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12 |
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37 |
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P1.1/TA0 |
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P1.2/TA1 |
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P1.3/TA2 |
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P1.4/SMCLK |
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 |
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P1.5/TA0 |
P1.6/TA1 |
P1.7/TA2 |
P2.0/ACLK |
P2.1/TAINCLK |
P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/R P2.6/ADC12CLK/DMAE0 P2.7/TA0 P3.0/STE0 |
P3.1/SIMO0/SDA P3.2/SOMI0 |
P3.3/UCLK0/SCL |
P3.4/UTXD0 |
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OSC |
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P5.4/MCLK
P5.3
P5.2
P5.1
P5.0
P4.7/TBCLK
P4.6
P4.5
P4.4
P4.3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7
P3.6
P3.5/URXD0
2 |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
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MSP430x15x, |
MSP430x16x, MSP430x161x |
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MIXED |
SIGNAL MICROCONTROLLER |
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005 |
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pin designation, MSP430F167, MSP430F168, MSP430F169 |
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PM, RTD PACKAGE |
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(TOP VIEW) |
XT2OUT P5.7/TBOUTH/SVSOUT |
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AV |
DV |
AV P6.2/A2 |
P6.1/A1 |
P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN |
P5.6/ACLK |
P5.5/SMCLK |
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CC |
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SS |
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DVCC |
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P5.4/MCLK |
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P6.3/A3 |
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P5.3/UCLK1 |
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P6.4/A4 |
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P5.2/SOMI1 |
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P6.5/A5 |
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P5.1/SIMO1 |
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P6.6/A6/DAC0 |
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44 |
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P5.0/STE1 |
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P6.7/A7/DAC1/SVSIN |
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6 |
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43 |
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P4.7/TBCLK |
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VREF+ |
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7 |
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42 |
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P4.6/TB6 |
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XIN |
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8 |
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41 |
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P4.5/TB5 |
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XOUT |
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9 |
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40 |
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P4.4/TB4 |
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VeREF+ |
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10 |
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39 |
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P4.3/TB3 |
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VREF− /VeREF− |
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11 |
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38 |
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P4.2/TB2 |
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P1.0/TACLK |
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12 |
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37 |
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P4.1/TB1 |
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P1.1/TA0 |
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13 |
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36 |
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P4.0/TB0 |
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P1.2/TA1 |
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14 |
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35 |
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P3.7/URXD1 |
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P1.3/TA2 |
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15 |
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34 |
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P3.6/UTXD1 |
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P1.4/SMCLK |
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16 |
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33 |
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P3.5/URXD0 |
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 |
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P1.5/TA0 |
P1.6/TA1 |
P1.7/TA2 P2.0/ACLK |
P2.1/TAINCLK |
P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/R P2.6/ADC12CLK/DMAE0 P2.7/TA0 P3.0/STE0 |
P3.1/SIMO0/SDA P3.2/SOMI0 |
P3.3/UCLK0/SCL |
P3.4/UTXD0 |
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OSC |
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|||||||
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
3 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
pin designation, MSP430F1610, MSP430F1611, MSP430F1612
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PM, RTD PACKAGE |
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(TOP VIEW) |
XT2OUT P5.7/TBOUTH/SVSOUT |
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AV |
DV |
AV |
P6.2/A2 |
P6.1/A1 |
P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN |
P5.6/ACLK |
P5.5/SMCLK |
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CC |
SS |
SS |
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DVCC |
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64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 |
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P5.4/MCLK |
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1 |
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48 |
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P6.3/A3 |
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2 |
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47 |
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P5.3/UCLK1 |
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P6.4/A4 |
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3 |
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46 |
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P5.2/SOMI1 |
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P6.5/A5 |
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4 |
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45 |
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P5.1/SIMO1 |
||
P6.6/A6/DAC0 |
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5 |
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44 |
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P5.0/STE1 |
||
P6.7/A7/DAC1/SVSIN |
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6 |
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43 |
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P4.7/TBCLK |
||
VREF+ |
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7 |
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42 |
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P4.6/TB6 |
||
XIN |
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8 |
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41 |
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P4.5/TB5 |
||
XOUT |
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9 |
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40 |
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P4.4/TB4 |
||
VeREF+ |
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10 |
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39 |
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P4.3/TB3 |
|||
VREF− /VeREF− |
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11 |
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38 |
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P4.2/TB2 |
|||
P1.0/TACLK |
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12 |
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37 |
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P4.1/TB1 |
|||
P1.1/TA0 |
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13 |
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36 |
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P4.0/TB0 |
|||
P1.2/TA1 |
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14 |
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35 |
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P3.7/URXD1 |
|||
P1.3/TA2 |
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15 |
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34 |
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P3.6/UTXD1 |
|||
P1.4/SMCLK |
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16 |
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33 |
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P3.5/URXD0 |
|||
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 |
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P1.5/TA0 |
P1.6/TA1 |
P1.7/TA2 |
P2.0/ACLK |
P2.1/TAINCLK |
P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/R P2.6/ADC12CLK/DMAE0 P2.7/TA0 P3.0/STE0 |
P3.1/SIMO0/SDA P3.2/SOMI0 |
P3.3/UCLK0/SCL |
P3.4/UTXD0 |
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OSC |
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|||||||
4 |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
functional block diagrams
MSP430x15x |
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XIN |
XOUT |
|
DVCC |
DVSS |
AVCC |
AVSS |
RST/NMI |
P1 |
P2 |
P3 |
P4 |
P5 |
P6 |
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8 |
8 |
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8 |
8 |
8 |
8 |
ROSC |
Oscillator |
ACLK |
32KB Flash |
1KB RAM |
|
ADC12 |
DAC12 |
I/O Port 1/2 |
I/O Port 3/4 |
I/O Port 5/6 |
||||||
XT2IN |
System |
SMCLK |
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16 I/Os, |
16 I/Os |
16 I/Os |
|
||||
24KB Flash |
1KB RAM |
|
12-Bit |
12-Bit |
with |
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|||||
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Clock |
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||||||||
XT2OUT |
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8 Channels |
2 Channels |
Interrupt |
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|||
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|||||
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16KB Flash |
512B RAM |
<10 s Conv. |
Voltage out |
Capability |
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|||
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MCLK |
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MAB, |
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Test |
MAB,MAB,16 Bit16-Bit |
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4 Bit |
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JTAG |
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CPU |
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MCB |
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Incl. 16 Reg. |
Emulation Module |
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MDB,MDB,16 Bit16-Bit |
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Bus |
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MDB, 8 Bit |
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|||
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Conv |
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4 |
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TMS |
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TCK |
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DMA |
Watchdog |
|
Timer_B3 |
Timer_A3 |
POR |
|
Comparator |
USART0 |
|
|||
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|
Controller |
Timer |
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SVS |
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A |
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||||
TDI/TCLK |
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3 CC Reg |
3 CC Reg |
Brownout |
|
|
UART Mode |
|||
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3 Channels |
15/16-Bit |
|
Shadow |
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SPI Mode |
||||
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|||||||
TDO/TDI |
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Reg |
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I2C Mode |
|
|
MSP430x16x |
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XIN |
XOUT |
|
DVCC |
DVSS |
AVCC |
AVSS |
RST/NMI |
P1 |
P2 |
P3 |
P4 |
P5 |
P6 |
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8 |
8 |
|
8 |
8 |
8 |
8 |
|
ROSC |
Oscillator |
ACLK |
60KB Flash |
2KB RAM |
|
ADC12 |
DAC12 |
I/O Port 1/2 |
I/O Port 3/4 |
I/O Port 5/6 |
|
||||||
XT2IN |
System |
SMCLK |
|
|
|
|
|
|
16 I/Os, |
16 I/Os |
16 I/Os |
|
|
||||
48KB Flash |
2KB RAM |
|
12-Bit |
12-Bit |
with |
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|||||
|
Clock |
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||||||||
XT2OUT |
|
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|
8 Channels |
2 Channels |
Interrupt |
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|||
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|||||
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|
32KB Flash |
1KB RAM |
<10 s Conv. |
Voltage out |
Capability |
|
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|||
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MCLK |
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MAB, |
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Test |
MAB,MAB,16 Bit16-Bit |
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4 Bit |
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JTAG |
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||
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CPU |
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MCB |
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Incl. 16 Reg. |
Emulation Module |
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MDB,MDB,16 Bit16-Bit |
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Bus |
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MDB, 8 Bit |
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Conv |
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4 |
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TMS |
Hardware |
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DMA |
Watchdog |
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Timer_B7 |
Timer_A3 |
POR |
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Comparator |
USART0 |
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USART1 |
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TCK |
Multiplier |
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Controller |
Timer |
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SVS |
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A |
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TDI/TCLK |
MPY, MPYS |
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7 CC Reg |
3 CC Reg |
Brownout |
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UART Mode |
UART Mode |
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3 Channels |
15/16-Bit |
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Shadow |
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SPI Mode |
SPI Mode |
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MAC,MACS |
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TDO/TDI |
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Reg |
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I2C Mode |
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
5 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
functional block diagrams (continued)
MSP430x161x |
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XIN |
XOUT |
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DVCC |
DVSS |
AVCC |
AVSS |
RST/NMI |
P1 |
P2 |
P3 |
P4 |
P5 |
P6 |
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8 |
8 |
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8 |
8 |
8 |
8 |
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ROSC |
Oscillator |
ACLK |
55KB Flash |
5KB RAM |
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ADC12 |
DAC12 |
I/O Port 1/2 |
I/O Port 3/4 |
I/O Port 5/6 |
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XT2IN |
System |
SMCLK |
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16 I/Os, |
16 I/Os |
16 I/Os |
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48KB Flash |
10KB RAM |
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12-Bit |
12-Bit |
with |
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Clock |
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XT2OUT |
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8 Channels |
2 Channels |
Interrupt |
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32KB Flash |
5KB RAM |
<10 s Conv. |
Voltage out |
Capability |
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MCLK |
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MAB, |
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Test |
MAB,MAB,16 Bit16-Bit |
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4 Bit |
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JTAG |
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CPU |
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MCB |
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Incl. 16 Reg. |
Emulation Module |
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MDB,MDB,16 Bit16-Bit |
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Bus |
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MDB, 8 Bit |
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Conv |
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4 |
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TMS |
Hardware |
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DMA |
Watchdog |
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Timer_B7 |
Timer_A3 |
POR |
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Comparator |
USART0 |
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USART1 |
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TCK |
Multiplier |
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Controller |
Timer |
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SVS |
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A |
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TDI/TCLK |
MPY, MPYS |
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7 CC Reg |
3 CC Reg |
Brownout |
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UART Mode |
UART Mode |
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3 Channels |
15/16-Bit |
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Shadow |
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SPI Mode |
SPI Mode |
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MAC,MACS |
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TDO/TDI |
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Reg |
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I2C Mode |
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6 |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
|
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MSP430x15x, MSP430x16x, MSP430x161x |
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MIXED SIGNAL MICROCONTROLLER |
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005 |
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Terminal Functions |
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TERMINAL |
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I/O |
DESCRIPTION |
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NAME |
NO. |
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AVCC |
64 |
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Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12. |
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AVSS |
62 |
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Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12. |
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DVCC |
1 |
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Digital supply voltage, positive terminal. Supplies all digital parts. |
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DVSS |
63 |
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Digital supply voltage, negative terminal. Supplies all digital parts. |
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P1.0/TACLK |
12 |
I/O |
General-purpose digital I/O pin/Timer_A, clock signal TACLK input |
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P1.1/TA0 |
13 |
I/O |
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit |
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P1.2/TA1 |
14 |
I/O |
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output |
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P1.3/TA2 |
15 |
I/O |
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output |
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P1.4/SMCLK |
16 |
I/O |
General-purpose digital I/O pin/SMCLK signal output |
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P1.5/TA0 |
17 |
I/O |
General-purpose digital I/O pin/Timer_A, compare: Out0 output |
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P1.6/TA1 |
18 |
I/O |
General-purpose digital I/O pin/Timer_A, compare: Out1 output |
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P1.7/TA2 |
19 |
I/O |
General-purpose digital I/O pin/Timer_A, compare: Out2 output |
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P2.0/ACLK |
20 |
I/O |
General-purpose digital I/O pin/ACLK output |
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P2.1/TAINCLK |
21 |
I/O |
General-purpose digital I/O pin/Timer_A, clock signal at INCLK |
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P2.2/CAOUT/TA0 |
22 |
I/O |
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive |
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P2.3/CA0/TA1 |
23 |
I/O |
General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input |
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P2.4/CA1/TA2 |
24 |
I/O |
General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input |
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P2.5/Rosc |
25 |
I/O |
General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency |
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P2.6/ADC12CLK/ |
26 |
I/O |
General-purpose digital I/O pin/conversion clock – 12-bit ADC/DMA channel 0 external trigger |
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DMAE0 |
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P2.7/TA0 |
27 |
I/O |
General-purpose digital I/O pin/Timer_A, compare: Out0 output |
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P3.0/STE0 |
28 |
I/O |
General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode |
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P3.1/SIMO0/SDA |
29 |
I/O |
General-purpose digital I/O pin/slave in/master out of USART0/SPI mode, I2C data − USART0/I2C mode |
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P3.2/SOMI0 |
30 |
I/O |
General-purpose digital I/O pin/slave out/master in of USART0/SPI mode |
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P3.3/UCLK0/SCL |
31 |
I/O |
General-purpose digital I/O pin/external clock input − USART0/UART or SPI mode, clock output – |
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USART0/SPI mode, I2C clock − USART0/I2C mode |
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P3.4/UTXD0 |
32 |
I/O |
General-purpose digital I/O pin/transmit data out – USART0/UART mode |
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P3.5/URXD0 |
33 |
I/O |
General-purpose digital I/O pin/receive data in – USART0/UART mode |
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P3.6/UTXD1† |
34 |
I/O |
General-purpose digital I/O pin/transmit data out – USART1/UART mode |
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P3.7/URXD1† |
35 |
I/O |
General-purpose digital I/O pin/receive data in – USART1/UART mode |
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P4.0/TB0 |
36 |
I/O |
General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output |
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P4.1/TB1 |
37 |
I/O |
General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output |
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P4.2/TB2 |
38 |
I/O |
General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output |
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P4.3/TB3† |
39 |
I/O |
General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output |
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P4.4/TB4† |
40 |
I/O |
General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output |
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P4.5/TB5† |
41 |
I/O |
General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output |
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P4.6/TB6† |
42 |
I/O |
General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output |
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P4.7/TBCLK |
43 |
I/O |
General-purpose digital I/O pin/Timer_B, clock signal TBCLK input |
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P5.0/STE1† |
44 |
I/O |
General-purpose digital I/O pin/slave transmit enable – USART1/SPI mode |
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P5.1/SIMO1† |
45 |
I/O |
General-purpose digital I/O pin/slave in/master out of USART1/SPI mode |
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P5.2/SOMI1† |
46 |
I/O |
General-purpose digital I/O pin/slave out/master in of USART1/SPI mode |
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P5.3/UCLK1† |
47 |
I/O |
General-purpose digital I/O pin/external clock input – USART1/UART or SPI mode, clock output – |
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USART1/SPI mode |
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† 16x, 161x devices only |
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
7 |
MSP430x15x, |
MSP430x16x, MSP430x161x |
|
||||
MIXED SIGNAL |
MICROCONTROLLER |
|
||||
SLAS368D− OCTOBER 2002− REVISED MARCH 2005 |
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|||||
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Terminal Functions (Continued) |
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TERMINAL |
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I/O |
DESCRIPTION |
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NAME |
NO. |
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P5.4/MCLK |
48 |
I/O |
General-purpose digital I/O pin/main system clock MCLK output |
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P5.5/SMCLK |
49 |
I/O |
General-purpose digital I/O pin/submain system clock SMCLK output |
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P5.6/ACLK |
50 |
I/O |
General-purpose digital I/O pin/auxiliary clock ACLK output |
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P5.7/TBOUTH/ |
51 |
I/O |
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B TB0 to |
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SVSOUT |
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TB6/SVS comparator output |
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P6.0/A0 |
59 |
I/O |
General-purpose digital I/O pin/analog input a0 – 12-bit ADC |
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P6.1/A1 |
60 |
I/O |
General-purpose digital I/O pin/analog input a1 – 12-bit ADC |
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P6.2/A2 |
61 |
I/O |
General-purpose digital I/O pin/analog input a2 – 12-bit ADC |
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P6.3/A3 |
2 |
I/O |
General-purpose digital I/O pin/analog input a3 – 12-bit ADC |
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P6.4/A4 |
3 |
I/O |
General-purpose digital I/O pin/analog input a4 – 12-bit ADC |
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P6.5/A5 |
4 |
I/O |
General-purpose digital I/O pin/analog input a5 – 12-bit ADC |
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P6.6/A6/DAC0 |
5 |
I/O |
General-purpose digital I/O pin/analog input a6 – 12-bit ADC/DAC12.0 output |
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P6.7/A7/DAC1/ |
6 |
I/O |
General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1 output/SVS input |
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SVSIN |
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58 |
I |
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). |
|
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RST/NMI |
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TCK |
57 |
I |
Test clock. TCK is the clock input port for device programming test and bootstrap loader start |
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TDI/TCLK |
55 |
I |
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. |
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TDO/TDI |
54 |
I/O |
Test data output port. TDO/TDI data output or programming data input terminal |
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TMS |
56 |
I |
Test mode select. TMS is used as an input port for device programming and test. |
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VeREF+ |
10 |
I |
Input for an external reference voltage |
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VREF+ |
7 |
O |
Output of positive terminal of the reference voltage in the ADC12 |
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VREF− /VeREF− |
11 |
I |
Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external |
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applied reference voltage |
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XIN |
8 |
I |
Input port for crystal oscillator XT1. Standard or watch crystals can be connected. |
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XOUT |
9 |
O |
Output terminal of crystal oscillator XT1 |
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XT2IN |
53 |
I |
Input port for crystal oscillator XT2. Only standard crystals can be connected. |
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XT2OUT |
52 |
O |
Output terminal of crystal oscillator XT2 |
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QFN Pad |
NA |
NA |
QFN package pad connection to DVSS recommended (RTD package only) |
|
|
8 |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.
instruction set
The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.
Program Counter |
PC/R0 |
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Stack Pointer |
SP/R1 |
|
SR/CG1/R2 |
|
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Status Register |
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Constant Generator |
CG2/R3 |
|
R4 |
|
|
General-Purpose Register |
|
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R5 |
|
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General-Purpose Register |
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General-Purpose Register |
R6 |
|
R7 |
|
|
General-Purpose Register |
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General-Purpose Register |
R8 |
|
R9 |
|
|
General-Purpose Register |
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General-Purpose Register |
R10 |
|
R11 |
|
|
General-Purpose Register |
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General-Purpose Register |
R12 |
|
R13 |
|
|
General-Purpose Register |
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General-Purpose Register |
R14 |
|
R15 |
|
|
General-Purpose Register |
|
|
|
Table 1. Instruction Word Formats
Dual operands, source-destination |
e.g. ADD |
R4,R5 |
R4 + R5 −−− > R5 |
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|
Single operands, destination only |
e.g. CALL |
R8 |
PC −− >(TOS), R8−− > PC |
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Relative jump, un/conditional |
e.g. JNE |
|
Jump-on-equal bit = 0 |
Table 2. Address Mode Descriptions
|
ADDRESS MODE |
|
S |
D |
SYNTAX |
EXAMPLE |
OPERATION |
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||
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|
Register |
|
D |
D |
MOV Rs,Rd |
MOV R10,R11 |
R10 |
−− > R11 |
|
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|
Indexed |
|
D |
D |
MOV X(Rn),Y(Rm) |
MOV 2(R5),6(R6) |
M(2+R5)−− |
> M(6+R6) |
|
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|
Symbolic (PC relative) |
|
D |
D |
MOV EDE,TONI |
|
M(EDE) −− |
> M(TONI) |
|
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||
|
Absolute |
|
D |
D |
MOV &MEM,&TCDAT |
|
M(MEM) −− > M(TCDAT) |
|
||
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||
|
Indirect |
|
D |
|
MOV @Rn,Y(Rm) |
MOV @R10,Tab(R6) |
M(R10) −− > M(Tab+R6) |
|
||
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Indirect |
|
D |
|
MOV @Rn+,Rm |
MOV @R10+,R11 |
M(R10) −− |
> R11 |
|
|
|
autoincrement |
|
|
R10 + 2−− |
> R10 |
|
||||
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Immediate |
|
D |
|
MOV #X,TONI |
MOV #45,TONI |
#45 −− > M(TONI) |
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||
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|
NOTE: S = source |
D = destination |
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|
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
9 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode AM;
−All clocks are active
DLow-power mode 0 (LPM0);
−CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DLow-power mode 1 (LPM1);
−CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
DLow-power mode 2 (LPM2);
−CPU is disabled
MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active
DLow-power mode 3 (LPM3);
−CPU is disabled
MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active
DLow-power mode 4 (LPM4);
−CPU is disabled ACLK is disabled
MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped
10 |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE |
INTERRUPT FLAG |
SYSTEM INTERRUPT |
WORD ADDRESS |
PRIORITY |
|
|
|
|
|
|
|
Power-up |
WDTIFG |
Reset |
0FFFEh |
15, highest |
|
External Reset |
KEYV |
|
|
|
|
Watchdog |
(see Note 1) |
|
|
|
|
Flash memory |
|
|
|
|
|
|
|
|
|
|
|
NMI |
NMIIFG (see Notes 1 & 3) |
(Non)maskable |
|
|
|
Oscillator Fault |
OFIFG (see Notes 1 & 3) |
(Non)maskable |
0FFFCh |
14 |
|
Flash memory access violation |
ACCVIFG (see Notes 1 & 3) |
(Non)maskable |
|
|
|
|
|
|
|
|
|
Timer_B7 (see Note 5) |
TBCCR0 CCIFG |
Maskable |
0FFFAh |
13 |
|
|
(see Note 2) |
|
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|
|
TBCCR1 to TBCCR6 |
|
|
|
|
Timer_B7 (see Note 5) |
CCIFGs, TBIFG |
Maskable |
0FFF8h |
12 |
|
|
(see Notes 1 & 2) |
|
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|
|
Comparator_A |
CAIFG |
Maskable |
0FFF6h |
11 |
|
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|
|
Watchdog timer |
WDTIFG |
Maskable |
0FFF4h |
10 |
|
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|
|
USART0 receive |
URXIFG0 |
Maskable |
0FFF2h |
9 |
|
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|
|
USART0 transmit |
UTXIFG0 |
Maskable |
0FFF0h |
8 |
|
I2C transmit/receive/others |
I2CIFG (see Note 4) |
|
|
|
|
ADC12 |
ADC12IFG |
Maskable |
0FFEEh |
7 |
|
|
(see Notes 1 & 2) |
|
|
|
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|
|
Timer_A3 |
TACCR0 CCIFG |
Maskable |
0FFECh |
6 |
|
|
(see Note 2) |
|
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|
|
TACCR1 and TACCR2 |
|
|
|
|
Timer_A3 |
CCIFGs, TAIFG |
Maskable |
0FFEAh |
5 |
|
|
(see Notes 1 & 2) |
|
|
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|
|
|
|
|
|
|
I/O port P1 (eight flags) |
P1IFG.0 to P1IFG.7 |
Maskable |
0FFE8h |
4 |
|
(see Notes 1 & 2) |
|||||
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||
|
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|
|
|
USART1 receive |
URXIFG1 |
Maskable |
0FFE6h |
3 |
|
|
|
|
|
|
|
USART1 transmit |
UTXIFG1 |
Maskable |
0FFE4h |
2 |
|
|
|
|
|
|
|
I/O port P2 (eight flags) |
P2IFG.0 to P2IFG.7 |
Maskable |
0FFE2h |
1 |
|
(see Notes 1 & 2) |
|||||
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||
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|
|
DAC12 |
DAC12_0IFG, |
Maskable |
0FFE0h |
0, lowest |
|
DMA |
DAC12_1IFG |
|
|
|
|
|
DMA0IFG, DMA1IFG, |
|
|
|
|
|
DMA2IFG (see Notes 1 & 2) |
|
|
|
|
NOTES: 1. Multiple source flags |
|
|
|
|
2.Interrupt flags are located in the module.
3.(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4.I2C interrupt flags located in the module
5.Timer_B7 in MSP430x16x/161x family has 7 CCRs; Timer_B3 in MSP430x15x family has 3 CCRs; in Timer_B3 there are only interrupt flags TBCCR0, 1 and 2 CCIFGs and the interrupt-enable bits TBCCR0, 1 and 2 CCIEs.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
11 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.
interrupt enable 1 and 2
Address |
7 |
|
6 |
5 |
4 |
3 |
2 |
|
1 |
0 |
|
0h |
|
UTXIE0 |
URXIE0 |
ACCVIE |
NMIIE |
|
|
|
OFIE |
WDTIE |
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|
rw-0 |
|
rw-0 |
rw-0 |
rw-0 |
|
|
|
rw-0 |
rw-0 |
|
WDTIE: |
|
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. |
|
||||||||
|
|
|
Active if watchdog timer is configured as general-purpose timer. |
|
|
||||||
OFIE: |
|
Oscillator-fault-interrupt enable |
|
|
|
|
|
||||
NMIIE: |
|
Nonmaskable-interrupt enable |
|
|
|
|
|
||||
ACCVIE: |
Flash memory access violation interrupt enable |
|
|
|
|
||||||
URXIE0: |
USART0: UART and SPI receive-interrupt enable |
|
|
|
|
||||||
UTXIE0: |
USART0: UART and SPI transmit-interrupt enable |
|
|
|
|
||||||
Address |
7 |
|
6 |
5 |
4 |
3 |
2 |
|
1 |
0 |
|
01h |
|
|
|
|
UTXIE1 |
URXIE1 |
|
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|
rw-0 rw-0
URXIE1†: USART1: UART and SPI receive-interrupt enable
UTXIE1†: USART1: UART and SPI transmit-interrupt enable
† URXIE1 and UTXIE1 are not present in MSP430x15x devices.
interrupt flag register 1 and 2
Address |
7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
0 |
||
02h |
UTXIFG0 |
URXIFG0 |
|
NMIIFG |
|
|
|
OFIFG |
WDTIFG |
|||
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rw-1 |
|
rw-0 |
|
rw-0 |
|
|
|
rw-1 |
rw-(0) |
||
WDTIFG: |
Set on watchdog-timer overflow (in watchdog mode) or security key violation |
|||||||||||
|
|
Reset on VCC power-on, or a reset condition at the |
|
|
||||||||
|
|
RST/NMI pin in reset mode |
||||||||||
OFIFG: |
Flag set on oscillator fault |
|
|
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|
|||||
NMIIFG: |
Set via |
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|
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|
|
|
|||
RST/NMI pin |
|
|
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|
|
|
||||||
URXIFG0: |
USART0: UART and SPI receive flag |
|
|
|
|
|
||||||
UTXIFG0: |
USART0: UART and SPI transmit flag |
|
|
|
|
|
||||||
Address |
7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
0 |
||
03h |
|
|
|
|
|
UTXIFG1 |
URXIFG1 |
|
|
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|
|
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|
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|
|
|
|
|
rw-1 rw-0
URXIFG1‡: USART1: UART and SPI receive flag
UTXIFG1‡: USART1: UART and SPI transmit flag
‡ URXIFG1 and UTXIFG1 are not present in MSP430x15x devices.
12 |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
|
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|
|
MSP430x15x, |
MSP430x16x, |
MSP430x161x |
||||||
|
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|
|
|
|
MIXED |
SIGNAL MICROCONTROLLER |
|||||||
|
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|
|
SLAS368D− OCTOBER 2002− REVISED MARCH 2005 |
|||||||
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|
|||
module enable registers 1 and 2 |
|
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|
|
|
|
|
||||||
Address |
|
7 |
|
6 |
5 |
4 |
3 |
|
2 |
1 |
|
0 |
|
|
||
04h |
|
UTXE0 |
URXE0 |
|
|
|
|
|
|
|
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|
||
|
|
|
|
USPIE0 |
|
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|
rw-0 |
|
|
rw-0 |
|
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|
|
|
|
URXE0: |
|
|
USART0: UART mode receive enable |
|
|
|
|
|
|
|
|
|
||||
UTXE0: |
|
|
USART0: UART mode transmit enable |
|
|
|
|
|
|
|
|
|
||||
USPIE0: |
|
USART0: SPI mode transmit and receive enable |
|
|
|
|
|
|
|
|||||||
Address |
|
7 |
|
6 |
5 |
4 |
3 |
|
2 |
1 |
|
0 |
|
|
||
05h |
|
|
|
|
|
UTXE1 |
URXE1 |
|
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|
USPIE1 |
|
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|
|
rw-0 |
rw-0 |
|
|
|
|
|
|
|
|
|
URXE1†: USART1: UART mode receive enable
UTXE1†: USART1: UART mode transmit enable
USPIE1†: USART1: SPI mode transmit and receive enable
† URXE1, UTXE1, and USPIE1 are not present in MSP430x15x devices.
Legend: rw: |
Bit Can Be Read and Written |
|
rw-0: |
Bit Can Be Read and Written. It Is Reset by PUC. |
|
|
|
SFR Bit Not Present in Device |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
13 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
memory organization (MSP430F15x)
|
|
MSP430F155 |
MSP430F156 |
MSP430F157 |
|||
|
|
|
|
|
|||
Memory |
Size |
16KB |
24KB |
32KB |
|||
Main: interrupt vector |
Flash |
0FFFFh − |
0FFE0h |
0FFFFh − |
0FFE0h |
0FFFFh − |
0FFE0h |
Main: code memory |
Flash |
0FFFFh − |
0C000h |
0FFFFh − |
0A000h |
0FFFFh − 08000h |
|
|
|
|
|
|
|||
Information memory |
Size |
256 Byte |
256 Byte |
256 Byte |
|||
|
Flash |
010FFh − |
01000h |
010FFh − |
01000h |
010FFh − |
01000h |
|
|
|
|
|
|||
Boot memory |
Size |
1KB |
1KB |
1KB |
|||
|
ROM |
0FFFh − 0C00h |
0FFFh − 0C00h |
0FFFh − 0C00h |
|||
|
|
|
|
|
|||
RAM |
Size |
512B |
1KB |
1KB |
|||
|
|
03FFh − |
0200h |
05FFh − |
0200h |
05FFh − |
0200h |
|
|
|
|
|
|
|
|
Peripherals |
16-bit |
01FFh − |
0100h |
01FFh − |
0100h |
01FFh − |
0100h |
|
8-bit |
0FFh − |
010h |
0FFh − |
010h |
0FFh − |
010h |
|
8-bit SFR |
0Fh − |
00h |
0Fh − |
00h |
0Fh − |
00h |
|
|
|
|
|
|
|
|
memory organization (MSP430F16x) |
|
|
|
|
|
||
|
|
MSP430F167 |
MSP430F168 |
MSP430F169 |
|||
|
|
|
|
|
|||
Memory |
Size |
32KB |
48KB |
60KB |
|||
Main: interrupt vector |
Flash |
0FFFFh − |
0FFE0h |
0FFFFh − |
0FFE0h |
0FFFFh − |
0FFE0h |
Main: code memory |
Flash |
0FFFFh − 08000h |
0FFFFh − 04000h |
0FFFFh − 01100h |
|||
|
|
|
|
|
|||
Information memory |
Size |
256 Byte |
256 Byte |
256 Byte |
|||
|
Flash |
010FFh − |
01000h |
010FFh − |
01000h |
010FFh − |
01000h |
|
|
|
|
|
|||
Boot memory |
Size |
1KB |
1KB |
1KB |
|||
|
ROM |
0FFFh − 0C00h |
0FFFh − 0C00h |
0FFFh − 0C00h |
|||
|
|
|
|
|
|||
RAM |
Size |
1KB |
2KB |
2KB |
|||
|
|
05FFh − |
0200h |
09FFh − |
0200h |
09FFh − |
0200h |
|
|
|
|
|
|
|
|
Peripherals |
16-bit |
01FFh − |
0100h |
01FFh − |
0100h |
01FFh − |
0100h |
|
8-bit |
0FFh − |
010h |
0FFh − |
010h |
0FFh − |
010h |
|
8-bit SFR |
0Fh − |
00h |
0Fh − |
00h |
0Fh − |
00h |
|
|
|
|
|
|
|
|
memory organization (MSP430F161x) |
|
|
|
|
|||
|
|
MSP430F1610 |
MSP430F1611 |
MSP430F1612 |
|
|||
|
|
|
|
|
|
|||
Memory |
Size |
32KB |
48KB |
55KB |
|
|||
Main: interrupt vector |
Flash |
0FFFFh − |
0FFE0h |
0FFFFh − |
0FFE0h |
0FFFFh − |
0FFE0h |
|
Main: code memory |
Flash |
0FFFFh − 08000h |
0FFFFh − 04000h |
0FFFFh − 02500h |
|
|||
|
|
|
|
|
|
|||
RAM (Total) |
Size |
5KB |
10KB |
5KB |
|
|||
|
|
024FFh − 01100h |
038FFh − 01100h |
024FFh − 01100h |
|
|||
Extended |
Size |
3KB |
8KB |
3KB |
|
|||
|
|
024FFh − |
01900h |
038FFh − |
01900h |
024FFh − |
01900h |
|
Mirrored |
Size |
2KB |
2KB |
2KB |
|
|||
|
|
018FFh − 01100h |
018FFh − 01100h |
018FFh − 01100h |
|
|||
|
|
|
|
|
|
|||
Information memory |
Size |
256 Byte |
256 Byte |
256 Byte |
|
|||
|
Flash |
010FFh − |
01000h |
010FFh − |
01000h |
010FFh − |
01000h |
|
|
|
|
|
|
|
|||
Boot memory |
Size |
1KB |
1KB |
1KB |
|
|||
|
ROM |
0FFFh − 0C00h |
0FFFh − 0C00h |
0FFFh − 0C00h |
|
|||
|
|
|
|
|
|
|||
RAM |
Size |
2KB |
2KB |
2KB |
|
|||
(mirrored at |
|
09FFh − |
0200h |
09FFh − |
0200h |
09FFh − |
0200h |
|
018FFh - 01100h) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Peripherals |
16-bit |
01FFh − |
0100h |
01FFh − |
0100h |
01FFh − |
0100h |
|
|
8-bit |
0FFh − |
010h |
0FFh − |
010h |
0FFh − |
010h |
|
|
8-bit SFR |
0Fh − |
00h |
0Fh − |
00h |
0Fh − |
00h |
|
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14 |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.
BSL Function |
PM, RTD Package Pins |
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Data Transmit |
13 - P1.1 |
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Data Receive |
22 - P2.2 |
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A and B can be erased individually, or as a group with segments 0− n. Segments A and B are also called information memory.
DNew devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use.
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MSP430F15x and MSP430F16x |
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MSP430F161x |
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16KB |
24KB |
32KB |
48KB |
60KB |
32KB |
48KB |
55KB |
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0FFFFh |
0FFFFh |
0FFFFh |
0FFFFh |
0FFFFh |
0FFFFh |
0FFFFh |
0FFFFh |
Segment 0 |
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w/ Interrupt Vectors |
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0FE00h |
0FE00h |
0FE00h |
0FE00h |
0FE00h |
0FE00h |
0FE00h |
0FE00h |
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0FDFFh |
0FDFFh |
0FDFFh |
0FDFFh |
0FDFFh |
0FDFFh |
0FDFFh |
0FDFFh |
Segment 1 |
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0FC00h |
0FC00h |
0FC00h |
0FC00h |
0FC00h |
0FC00h |
0FC00h |
0FC00h |
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0FBFFh |
0FBFFh |
0FBFFh |
0FBFFh |
0FBFFh |
0FBFFh |
0FBFFh |
0FBFFh |
Segment 2 |
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0FA00h |
0FA00h |
0FA00h |
0FA00h |
0FA00h |
0FA00h |
0FA00h |
0FA00h |
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Main |
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0F9FFh |
0F9FFh |
0F9FFh |
0F9FFh |
0F9FFh |
0F9FFh |
0F9FFh |
0F9FFh |
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Memory |
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04400h |
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0C400h |
0A400h |
08400h |
04400h |
01400h |
08400h |
02800h |
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0C3FFh |
0A3FFh |
083FFh |
043FFh |
013FFh |
083FFh |
043FFh |
027FFh |
Segment n-1 |
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0C200h |
0A200h |
08200h |
04200h |
01200h |
08200h |
04200h |
02600h |
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0C1FFh |
0A1FFh |
081FFh |
041FFh |
011FFh |
081FFh |
041FFh |
025FFh |
Segment n† |
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0C000h |
0A000h |
08000h |
04000h |
01100h |
08000h |
04000h |
02500h |
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024FFh |
038FFh |
024FFh |
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RAM |
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01100h |
01100h |
01100h |
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(’F161x |
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only) |
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010FFh |
010FFh |
010FFh |
010FFh |
010FFh |
010FFh |
010FFh |
010FFh |
Segment A |
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Info |
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01080h |
01080h |
01080h |
01080h |
01080h |
01080h |
01080h |
01080h |
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0107Fh |
0107Fh |
0107Fh |
0107Fh |
0107Fh |
0107Fh |
0107Fh |
0107Fh |
Segment B |
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Memory |
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01000h |
01000h |
01000h |
01000h |
01000h |
01000h |
01000h |
01000h |
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† MSP430F169 and MSP430F1612 flash segment n = 256 bytes.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
15 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.
oscillator and system clock
The clock system in the MSP430x15x and MSP430x16x(x) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The basic clock module provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
DMain clock (MCLK), the system clock used by the CPU.
DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented— ports P1 through P6:
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
hardware multiplier (MSP430x16x/161x Only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16, 16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.
16 |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
USART0
The MSP430x15x and the MSP430x16x(x) have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered transmit and receive channels.
The I2C support is compliant with the Philips I2C specification version 2.1 and supports standard mode (up to 100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported, as well as master and slave modes. The USART0 also supports 16-bit-wide I2C data transfers and has two dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I2C mode.
USART1 (MSP430x16x/161x Only)
The MSP430x16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit (USART1) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. With the exception of I2C support, operation of USART1 is identical to USART0.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer_A3 Signal Connections
Input Pin Number |
Device Input Signal |
Module Input Name |
Module Block |
Module Output Signal |
Output Pin Number |
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12 - P1.0 |
TACLK |
TACLK |
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ACLK |
ACLK |
Timer |
NA |
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SMCLK |
SMCLK |
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21 - P2.1 |
TAINCLK |
INCLK |
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13 - P1.1 |
TA0 |
CCI0A |
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13 - P1.1 |
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22 - P2.2 |
TA0 |
CCI0B |
CCR0 |
TA0 |
17 - P1.5 |
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DVSS |
GND |
27 - P2.7 |
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DVCC |
VCC |
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14 - P1.2 |
TA1 |
CCI1A |
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14 - P1.2 |
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CAOUT (internal) |
CCI1B |
CCR1 |
TA1 |
18 - P1.6 |
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DVSS |
GND |
23 - P2.3 |
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DVCC |
VCC |
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ADC12 (internal) |
15 - P1.3 |
TA2 |
CCI2A |
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15 - P1.3 |
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ACLK (internal) |
CCI2B |
CCR2 |
TA2 |
19 - P1.7 |
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DVSS |
GND |
24 - P2.4 |
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DVCC |
VCC |
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timer_B3 (MSP430x15x Only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
17 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
timer_B7 (MSP430x16x/161x Only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer_B3/B7 Signal Connections†
Input Pin Number |
Device Input Signal |
Module Input Name |
Module Block |
Module Output Signal |
Output Pin Number |
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43 - P4.7 |
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TBCLK |
TBCLK |
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ACLK |
ACLK |
Timer |
NA |
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SMCLK |
SMCLK |
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43 - P4.7 |
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INCLK |
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TBCLK |
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36 - P4.0 |
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TB0 |
CCI0A |
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36 - P4.0 |
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36 - P4.0 |
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TB0 |
CCI0B |
CCR0 |
TB0 |
ADC12 (internal) |
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DVSS |
GND |
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DVCC |
VCC |
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37 - P4.1 |
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TB1 |
CCI1A |
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37 - P4.1 |
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37 - P4.1 |
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TB1 |
CCI1B |
CCR1 |
TB1 |
ADC12 (internal) |
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DVSS |
GND |
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DVCC |
VCC |
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38 - P4.2 |
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TB2 |
CCI2A |
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38 - P4.2 |
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38 - P4.2 |
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TB2 |
CCI2B |
CCR2 |
TB2 |
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DVSS |
GND |
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DVCC |
VCC |
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39 - P4.3 |
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TB3 |
CCI3A |
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39 - P4.3 |
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39 - P4.3 |
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TB3 |
CCI3B |
CCR3 |
TB3 |
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DVSS |
GND |
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DVCC |
VCC |
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40 - P4.4 |
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TB4 |
CCI4A |
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40 - P4.4 |
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40 - P4.4 |
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TB4 |
CCI4B |
CCR4 |
TB4 |
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DVSS |
GND |
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DVCC |
VCC |
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41 - P4.5 |
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TB5 |
CCI5A |
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41 - P4.5 |
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41 - P4.5 |
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TB5 |
CCI5B |
CCR5 |
TB5 |
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DVSS |
GND |
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DVCC |
VCC |
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42 - P4.6 |
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TB6 |
CCI6A |
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42 - P4.6 |
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ACLK (internal) |
CCI6B |
CCR6 |
TB6 |
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DVSS |
GND |
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DVCC |
VCC |
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† Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
18 |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
comparator_A
The primary function of the comparator_A module is to support precision slope analog− to− digital conversions, battery− voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
19 |
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
peripheral file map
PERIPHERAL FILE MAP
DMA |
DMA channel 2 transfer size |
DMA2SZ |
01F6h |
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DMA channel 2 destination address |
DMA2DA |
01F4h |
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DMA channel 2 source address |
DMA2SA |
01F2h |
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DMA channel 2 control |
DMA2CTL |
01F0h |
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DMA channel 1 transfer size |
DMA1SZ |
01EEh |
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DMA channel 1 destination address |
DMA1DA |
01ECh |
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DMA channel 1 source address |
DMA1SA |
01EAh |
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DMA channel 1 control |
DMA1CTL |
01E8h |
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DMA channel 0 transfer size |
DMA0SZ |
01E6h |
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DMA channel 0 destination address |
DMA0DA |
01E4h |
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DMA channel 0 source address |
DMA0SA |
01E2h |
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DMA channel 0 control |
DMA0CTL |
01E0h |
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DMA module control 1 |
DMACTL1 |
0124h |
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DMA module control 0 |
DMACTL0 |
0122h |
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DAC12 |
DAC12_1 data |
DAC12_1DAT |
01CAh |
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DAC12_1 control |
DAC12_1CTL |
01C2h |
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DAC12_0 data |
DAC12_0DAT |
01C8h |
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DAC12_0 control |
DAC12_0CTL |
01C0h |
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ADC12 |
Interrupt-vector-word register |
ADC12IV |
01A8h |
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Inerrupt-enable register |
ADC12IE |
01A6h |
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Inerrupt-flag register |
ADC12IFG |
01A4h |
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Control register 1 |
ADC12CTL1 |
01A2h |
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Control register 0 |
ADC12CTL0 |
01A0h |
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Conversion memory 15 |
ADC12MEM15 |
015Eh |
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Conversion memory 14 |
ADC12MEM14 |
015Ch |
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Conversion memory 13 |
ADC12MEM13 |
015Ah |
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Conversion memory 12 |
ADC12MEM12 |
0158h |
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Conversion memory 11 |
ADC12MEM11 |
0156h |
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Conversion memory 10 |
ADC12MEM10 |
0154h |
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Conversion memory 9 |
ADC12MEM9 |
0152h |
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Conversion memory 8 |
ADC12MEM8 |
0150h |
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Conversion memory 7 |
ADC12MEM7 |
014Eh |
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Conversion memory 6 |
ADC12MEM6 |
014Ch |
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Conversion memory 5 |
ADC12MEM5 |
014Ah |
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Conversion memory 4 |
ADC12MEM4 |
0148h |
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Conversion memory 3 |
ADC12MEM3 |
0146h |
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Conversion memory 2 |
ADC12MEM2 |
0144h |
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Conversion memory 1 |
ADC12MEM1 |
0142h |
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Conversion memory 0 |
ADC12MEM0 |
0140h |
20 |
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
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MSP430x15x, MSP430x16x, MSP430x161x |
||||
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MIXED SIGNAL |
MICROCONTROLLER |
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005 |
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peripheral file map (continued) |
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PERIPHERAL FILE MAP (CONTINUED) |
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ADC12 |
ADC memory-control register15 |
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ADC12MCTL15 |
08Fh |
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(continued) |
ADC memory-control register14 |
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ADC12MCTL14 |
08Eh |
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ADC memory-control register13 |
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ADC12MCTL13 |
08Dh |
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ADC memory-control register12 |
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ADC12MCTL12 |
08Ch |
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ADC memory-control register11 |
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ADC12MCTL11 |
08Bh |
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ADC memory-control register10 |
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ADC12MCTL10 |
08Ah |
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ADC memory-control register9 |
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ADC12MCTL9 |
089h |
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ADC memory-control register8 |
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ADC12MCTL8 |
088h |
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ADC memory-control register7 |
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ADC12MCTL7 |
087h |
|
|
|
|
ADC memory-control register6 |
|
ADC12MCTL6 |
086h |
|
|
|
|
ADC memory-control register5 |
|
ADC12MCTL5 |
085h |
|
|
|
|
ADC memory-control register4 |
|
ADC12MCTL4 |
084h |
|
|
|
|
ADC memory-control register3 |
|
ADC12MCTL3 |
083h |
|
|
|
|
ADC memory-control register2 |
|
ADC12MCTL2 |
082h |
|
|
|
|
ADC memory-control register1 |
|
ADC12MCTL1 |
081h |
|
|
|
|
ADC memory-control register0 |
|
ADC12MCTL0 |
080h |
|
|
|
Timer_B7/ |
Capture/compare register 6 |
|
TBCCR6 |
019Eh |
|
|
|
Timer_B3 |
Capture/compare register 5 |
|
TBCCR5 |
019Ch |
|
|
|
(see Note 1) |
|
|
||||
|
Capture/compare register 4 |
|
TBCCR4 |
019Ah |
|
|
|
|
|
|
|
||||
|
|
|
|
||||
|
|
Capture/compare register 3 |
|
TBCCR3 |
0198h |
|
|
|
|
Capture/compare register 2 |
|
TBCCR2 |
0196h |
|
|
|
|
Capture/compare register 1 |
|
TBCCR1 |
0194h |
|
|
|
|
Capture/compare register 0 |
|
TBCCR0 |
0192h |
|
|
|
|
Timer_B register |
|
TBR |
0190h |
|
|
|
|
Capture/compare control 6 |
|
TBCCTL6 |
018Eh |
|
|
|
|
Capture/compare control 5 |
|
TBCCTL5 |
018Ch |
|
|
|
|
Capture/compare control 4 |
|
TBCCTL4 |
018Ah |
|
|
|
|
Capture/compare control 3 |
|
TBCCTL3 |
0188h |
|
|
|
|
Capture/compare control 2 |
|
TBCCTL2 |
0186h |
|
|
|
|
Capture/compare control 1 |
|
TBCCTL1 |
0184h |
|
|
|
|
Capture/compare control 0 |
|
TBCCTL0 |
0182h |
|
|
|
|
Timer_B control |
|
TBCTL |
0180h |
|
|
|
|
Timer_B interrupt vector |
|
TBIV |
011Eh |
|
|
|
|
|
|
|
|
|
|
|
Timer_A3 |
Reserved |
|
|
017Eh |
|
|
|
|
Reserved |
|
|
017Ch |
|
|
|
|
Reserved |
|
|
017Ah |
|
|
|
|
Reserved |
|
|
0178h |
|
|
|
|
Capture/compare register 2 |
|
TACCR2 |
0176h |
|
|
|
|
Capture/compare register 1 |
|
TACCR1 |
0174h |
|
|
|
|
Capture/compare register 0 |
|
TACCR0 |
0172h |
|
|
|
|
Timer_A register |
|
TAR |
0170h |
|
|
|
|
Reserved |
|
|
016Eh |
|
|
|
|
Reserved |
|
|
016Ch |
|
|
|
|
Reserved |
|
|
016Ah |
|
|
|
|
Reserved |
|
|
0168h |
|
|
|
|
|
|
|
|
|
|
NOTE 1: Timer_B7 in MSP430x16x/161x family has 7 CCRs, Timer_B3 in MSP430x15x family has 3 CCRs.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 |
21 |
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