Fairchild Semiconductor DM74ALS74ASJX, DM74ALS74ASJ, DM74ALS74AN, DM74ALS74AMX, DM74ALS74AM Datasheet
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September 1986
Revised February 2000
DM74ALS74A
Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
General Description
The DM74ALS74A contains two independent positive edge-triggered flip-flops. Each flip-flop has individual D, clock, clear and preset inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal.
Features
■Switching specifications at 50 pF
■Switching specifications guaranteed over full temperature and VCC range
■Advanced oxide-isolated, ion-implanted Schottky TTL process
■Functionally and pin-for-pin compatible with Schottky and LS TTL counterpart
■Improved AC performance over LS74 at approximately half the power
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74ALS74AM |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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DM74ALS74ASJ |
M14D |
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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DM74ALS74AN |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Function Table |
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Inputs |
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Outputs |
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PR |
CLR |
CLK |
D |
Q |
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Q |
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L |
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H |
X |
X |
H |
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L |
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H |
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L |
X |
X |
L |
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H |
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L |
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L |
X |
X |
H (Note 1) |
H (Note 1) |
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H |
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H |
− |
H |
H |
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L |
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H |
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H |
− |
L |
L |
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H |
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H |
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H |
L |
X |
Q0 |
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Q |
0 |
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L = LOW State
H = HIGH State
X = Don't Care
− = Positive Edge Transition
Q0 = Previous Condition of Q
Note 1: This condition is nonstable; it will not persist when preset and clear inputs return to their inactive (HIGH) level. The output levels in this condition are not guaranteed to meet the VOH specification.
Clear and Preset with Flop-Flip Triggered-Edge-Positive D Dual DM74ALS74A
© 2000 Fairchild Semiconductor Corporation |
DS006109 |
www.fairchildsemi.com |
DM74ALS74A
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 2)
Supply Voltage |
7V |
Input Voltage |
7V |
Operating Free Air Temperature Range |
0°C to +70°C |
Storage Temperature Range |
−65°C to +150°C |
Typical θJA |
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N Package |
87.0°C/W |
M Package |
117.0°C/W |
Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol |
Parameter |
Min |
Nom |
Max |
Units |
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VCC |
Supply Voltage |
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4.5 |
5 |
5.5 |
V |
VIH |
HIGH Level Input Voltage |
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2 |
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V |
VIL |
LOW Level Input Voltage |
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0.8 |
V |
IOH |
HIGH Level Output Current |
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−0.4 |
mA |
IOL |
LOW Level Output Current |
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8 |
mA |
fCLK |
Clock Frequency |
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0 |
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34 |
MHz |
tW(CLK) |
Width of Clock Pulse |
HIGH |
14.5 |
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ns |
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LOW |
14.5 |
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ns |
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tW |
Pulse Width |
LOW |
14.5 |
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ns |
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Preset & Clear |
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tSU |
Data Setup Time |
Data |
15− (Note 3) |
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PRE or CLR |
10− (Note 3) |
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ns |
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Inactive |
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tH |
Data Hold Time |
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0− (Note 3) |
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ns |
TA |
Free Air Operating Temperature |
0 |
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70 |
°C |
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Note 3: The (−) arrow indicates the positive edge of the Clock is used for reference.
DM74ALS74A
3 |
www.fairchildsemi.com |
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