September 1986
Revised February 2000
DM74ALS574A
Octal D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs
General Description
These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the DM74ALS574A are edge-trig- gered D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.
A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-imped- ance state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.
Features
■Switching specifications at 50 pF
■Switching specifications guaranteed over full temperature and VCC range
■Advanced oxide-isolated, ion-implanted Schottky TTL process
■Functionally equivalent with DM74LS374
■Improved AC performance over DM74LS374 at approximately half the power
■3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74ALS574AWM |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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DM74ALS574ASJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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DM74ALS574AN |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Outputs STATE-3 with Flop-Flip Triggered-Edge Type-D Octal DM74ALS574A
© 2000 Fairchild Semiconductor Corporation |
DS006110 |
www.fairchildsemi.com |
DM74ALS574A
Function Table |
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Logic Diagram |
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Output |
Clock |
D |
Output |
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Control |
Q |
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L |
− |
H |
H |
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L |
− |
L |
L |
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L |
L |
X |
Q0 |
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H |
X |
X |
Z |
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L = LOW State
H = HIGH State
X = Don’t Care
− = Positive Edge Transition
Z = High Impedance State
Q0 = Previous Condition of Q
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage |
7V |
Input Voltage |
7V |
Voltage Applied to Disabled Output |
5.5V |
Operating Free Air Temperature Range |
0°C to +70°C |
Storage Temperature Range |
−65°C to +150°C |
Typical θJA |
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N Package |
56.0°C/W |
M Package |
75.0°C/W |
Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol |
Parameter |
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Min |
Nom |
Max |
Units |
VCC |
Supply Voltage |
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4.5 |
5 |
5.5 |
V |
VIH |
HIGH Level Input Voltage |
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2 |
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V |
VIL |
LOW Level Input Voltage |
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0.8 |
V |
IOH |
HIGH Level Output Current |
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−2.6 |
mA |
IOL |
LOW Level Output Current |
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24 |
mA |
fCLOCK |
Clock Frequency |
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0 |
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35 |
MHz |
tW |
Width of Clock Pulse |
HIGH |
14 |
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ns |
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LOW |
14 |
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ns |
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tSU |
Data Setup Time |
(Note 2) |
15 − |
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ns |
tH |
Data Hold Time |
(Note 2) |
0 − |
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ns |
TA |
Free Air Operating Temperature |
0 |
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70 |
°C |
Note 2: The (−) arrow indicates the positive edge of the Clock is used for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
Symbol |
Parameter |
Conditions |
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Min |
Typ |
Max |
Units |
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VIK |
Input Clamp Voltage |
VCC = 4.5V, II = −18 mA |
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−1.2 |
V |
VOH |
HIGH Level |
VCC = 4.5V |
IOH = Max |
2.4 |
3.2 |
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V |
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Output Voltage |
VIL = VIL Max |
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VCC = 4.5V to 5.5V |
IOH = −400 μA |
VCC − 2 |
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V |
VOL |
LOW Level |
VCC = 4.5V |
IOL = 12 mA |
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0.25 |
0.4 |
V |
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Output Voltage |
VIH = 2V |
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IOL = 24 mA |
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0.35 |
0.5 |
V |
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II |
Input Current at Max Input Voltage |
VCC = 5.5V, VIH = 7V |
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0.1 |
mA |
IIH |
HIGH Level Input Current |
VCC = 5.5V, VIH = 2.7V |
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20 |
μA |
IIL |
LOW Level Input Current |
VCC = 5.5V, VIL = 0.4V |
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−0.2 |
mA |
IO |
Output Drive Current |
VCC = 5.5V, VO = 2.25V |
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−30 |
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−112 |
mA |
IOZH |
OFF-State Output Current |
VCC = 5.5V, VIH = 2V |
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20 |
μA |
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HIGH Level Voltage Applied |
VO = 2.7V |
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IOZL |
OFF-State Output Current d |
VCC = 5.5V, VIH = 2V |
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−20 |
μA |
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LOW Level Voltage Applied |
VO = 0.4V |
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ICC |
Supply Current |
VCC = 5.5V |
Outputs HIGH |
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11 |
18 |
mA |
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Outputs Open |
Outputs LOW |
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17 |
27 |
mA |
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Outputs Disabled |
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17 |
28 |
mA |
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DM74ALS574A
3 |
www.fairchildsemi.com |