April 1984
Revised February 2000
DM74ALS534
Octal D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs
General Description
These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the DM74ALS534 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the complement of the logic states that were set up at the D inputs.
A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-imped- ance state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are off.
Features
■Switching specifications at 50 pF
■Switching specifications guaranteed over full temperature and VCC range
■Advanced oxide-isolated, ion-implanted Schottky TTL process
■3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74ALS534WM |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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DM74ALS534N |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Outputs STATE-3 with Flop-Flip Triggered-Edge Type-D Octal DM74ALS534
© 2000 Fairchild Semiconductor Corporation |
DS006223 |
www.fairchildsemi.com |
DM74ALS534
Function Table |
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Logic Diagram |
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Output |
Clock |
D |
Output |
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Control |
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Q |
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L |
− |
H |
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L |
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L |
− |
L |
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H |
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L |
L |
X |
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Q |
0 |
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H |
X |
X |
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Z |
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L = LOW State
H = HIGH State
X = Don’t Care
− = Positive Edge Transition
Z = High Impedance State
Q0 = Previous Condition of Q
www.fairchildsemi.com |
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