ST STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD User Manual

STM32F103xC STM32F103xD

STM32F103xE

High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

Features

■Core: ARM 32-bit Cortex™-M3 CPU

–72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access

–Single-cycle multiplication and hardware division

■Memories

–256 to 512 Kbytes of Flash memory

–up to 64 Kbytes of SRAM

–Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories

–LCD parallel interface, 8080/6800 modes

■Clock, reset and supply management

–2.0 to 3.6 V application supply and I/Os

–POR, PDR, and programmable voltage detector (PVD)

–4-to-16 MHz crystal oscillator

–Internal 8 MHz factory-trimmed RC

–Internal 40 kHz RC with calibration

–32 kHz oscillator for RTC with calibration

■Low power

–Sleep, Stop and Standby modes

–VBAT supply for RTC and backup registers

■3 × 12-bit, 1 µs A/D converters (up to 21 channels)

–Conversion range: 0 to 3.6 V

–Triple-sample and hold capability

–Temperature sensor

■2 × 12-bit D/A converters

■DMA: 12-channel DMA controller

–Supported peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs

■Debug mode

–Serial wire debug (SWD) & JTAG interfaces

–Cortex-M3 Embedded Trace Macrocell™

FBGA

		WLCSP64
	LQFP64 10 × 10 mm,	LFBGA100 10 × 10 mm
	LQFP100 14 × 14 mm,
		LFBGA144 10 × 10 mm
	LQFP144 20 × 20 mm

■Up to 112 fast I/O ports

–51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

■Up to 11 timers

–Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

–2 × 16-bit motor control PWM timers with dead-time generation and emergency stop

–2 × watchdog timers (Independent and Window)

–SysTick timer: a 24-bit downcounter

–2 × 16-bit basic timers to drive the DAC

■Up to 13 communication interfaces

–Up to 2 × I2C interfaces (SMBus/PMBus)

–Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)

–Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed

–CAN interface (2.0B Active)

–USB 2.0 full speed interface

–SDIO interface

■CRC calculation unit, 96-bit unique ID

■ECOPACK® packages

Table 1. Device summary

Reference

Part number

STM32F103xC

STM32F103RC STM32F103VC

STM32F103ZC

STM32F103xD

STM32F103RD STM32F103VD

STM32F103ZD

STM32F103xE

STM32F103RE STM32F103ZE

STM32F103VE

April 2011

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Contents	STM32F103xC, STM32F103xD, STM32F103xE

Contents

1	Introduction		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
2	Description . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.1	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	2.2	Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	2.3	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
		2.3.1	ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . .	15
		2.3.2	Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
		2.3.3	CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . .	15
		2.3.4	Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
		2.3.5	FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . .	15
		2.3.6	LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
		2.3.7	Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . .	16
		2.3.8	External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . .	16
		2.3.9	Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
		2.3.10	Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
		2.3.11	Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
		2.3.12	Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
		2.3.13	Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
		2.3.14	Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
		2.3.15	DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
		2.3.16	RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . .	18
		2.3.17	Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
		2.3.18	I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

2.3.19Universal synchronous/asynchronous receiver transmitters (USARTs) 21

2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.21 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.22 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.28 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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2.3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.30 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3	Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
4	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
	5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
5.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		42
	5.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 42
	5.3.2	Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . .	. 43
	5.3.3	Embedded reset and power control block characteristics . . . . . . . . . .	. 43
	5.3.4	Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
	5.3.5	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
	5.3.6	External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
	5.3.7	Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
	5.3.8	PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
	5.3.9	Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
	5.3.10	FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	63
	5.3.11	EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
	5.3.12	Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . .	84
	5.3.13	I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .	85
	5.3.14	I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	86
	5.3.15	NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
	5.3.16	TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	92
	5.3.17	Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	93
	5.3.18	CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . .	102
	5.3.19	12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	103

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5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			111
	6.1	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		111
	6.2	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		120
		6.2.1	Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 120
		6.2.2	Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . .	. 121
7	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			123
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			124

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STM32F103xC, STM32F103xD, STM32F103xE	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . 11 Table 3. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. High-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 7. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 8. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 9. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 11. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 12. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 13. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 14. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 15. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 47 Table 17. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 48 Table 18. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 19. Typical current consumption in Sleep mode, code running from Flash or

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 20. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 21. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 22. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 23. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 24. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 25. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 26. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 28. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 29. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 30. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 64 Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 65 Table 33. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 34. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 35. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 36. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 37. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 38. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 39. Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 79 Table 40. Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 82 Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

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Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 50. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 51. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 52. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 53. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 54. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 55. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 56. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 57. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 58. USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 59. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 60. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 61. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 62. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 63. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 64. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 65. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 112 Table 66. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 69. Recommended PCB design rules (0.5mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 70. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 117 Table 71. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 118 Table 72. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 119 Table 73. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 74. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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STM32F103xC, STM32F103xD, STM32F103xE	List of figures

List of figures

Figure 1.	STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12
Figure 2.	Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Figure 3.	STM32F103xC and STM32F103xE performance line BGA144 ballout . . . . . . . . . . . . . . .	24
Figure 4.	STM32F103xC and STM32F103xE performance line BGA100 ballout . . . . . . . . . . . . . . .	25
Figure 5.	STM32F103xC and STM32F103xE performance line LQFP144 pinout. . . . . . . . . . . . . . .	26
Figure 6.	STM32F103xC and STM32F103xE performance line LQFP100 pinout. . . . . . . . . . . . . . .	27
Figure 7.	STM32F103xC and STM32F103xE performance line
	LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 8.	STM32F103xC and STM32F103xE performance line
	WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Figure 9.	Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Figure 10.	Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
Figure 11.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
Figure 12.	Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 13.	Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 14.	Typical current consumption in Run mode versus frequency (at 3.6 V) -
	code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . .	46
Figure 15.	Typical current consumption in Run mode versus frequency (at 3.6 V)-
	code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . .	46
Figure 16.	Typical current consumption on VBAT with RTC on vs. temperature at different VBAT
	values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 17.	Typical current consumption in Stop mode with regulator in run mode
	versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 18.	Typical current consumption in Stop mode with regulator in low-power
	mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
Figure 19.	Typical current consumption in Standby mode versus temperature at
	different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
Figure 20.	High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
Figure 21.	Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
Figure 22.	Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
Figure 23.	Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
Figure 24.	Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . .	64
Figure 25.	Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . .	65
Figure 26.	Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . .	66
Figure 27.	Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . .	68
Figure 28.	Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
Figure 29.	Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
Figure 30.	Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . .	73
Figure 31.	Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	74
Figure 32.	PC Card/CompactFlash controller waveforms for common memory read access . . . . . . .	75
Figure 33.	PC Card/CompactFlash controller waveforms for common memory write access . . . . . . .	76
Figure 34.	PC Card/CompactFlash controller waveforms for attribute memory read
	access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
Figure 35.	PC Card/CompactFlash controller waveforms for attribute memory write
	access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	78
Figure 36.	PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . .	78
Figure 37.	PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . .	79
Figure 38.	NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81

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List of figures		STM32F103xC, STM32F103xD, STM32F103xE
Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 81
Figure 40. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . .			. 81
Figure 41. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . .			. 82
Figure 42. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 87
Figure 43. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 87
Figure 44. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			88
Figure 45. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			88
Figure 46. I/O AC characteristics definition . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
Figure 47. Recommended NRST pin protection . . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
Figure 48. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			94
Figure 49. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			96
Figure 50. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			96
Figure 51. SPI timing diagram - master mode(1) . . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
Figure 52. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			99
Figure 53. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			99
Figure 54. SDIO high-speed mode . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	100
Figure 55. SD default mode . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	100
Figure 56. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . .			102
Figure 57. ADC accuracy characteristics . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	105
Figure 58. Typical connection diagram using the ADC		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	106
Figure 59. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . .			106
Figure 60. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . .			107
Figure 61. 12-bit buffered /non-buffered DAC . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	109
Figure 62. BGA pad footprint . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	112
Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
	0.8 mm pitch, package outline . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	113
Figure 64. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
	outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	114
Figure 65. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale
	package outline. . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	115
Figure 66. BGA pad footprint . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	116
Figure 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad
	flat package outline . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	117
Figure 68.	Recommended footprint(1) . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	117
Figure 69. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . .			118
Figure 70.	Recommended footprint(1) . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	118
Figure 71. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . .			119
Figure 72.	Recommended footprint(1) . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	119
Figure 73.	LQFP100 PD max vs. TA . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	122

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STM32F103xC, STM32F103xD, STM32F103xE	Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family.

The high-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

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Description	STM32F103xC, STM32F103xD, STM32F103xE

2 Description

The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance ARM® Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals

connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16bit timers plus two PWM timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN.

The STM32F103xx high-density performance line family operates in the –40 to +105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

These features make the STM32F103xx high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems video intercom, and HVAC.

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STM32F103xC, STM32F103xD, STM32F103xE	Description

2.1Device overview

The STM32F103xx high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

Figure 1 shows the general block diagram of the device family.

Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts

Peripherals		STM32F103Rx					STM32F103Vx				STM32F103Zx
Flash memory in Kbytes		256		384		512	256		384	512	256	384		512
SRAM in Kbytes		48		64(1)			48		64		48		64
FSMC				No					Yes(2)			Yes
	General-purpose							4
Timers	Advanced-control							2
	Basic							2
	SPI(I2S)(3)							3(2)
	I2C							2
Comm	USART							5
	USB							1
	CAN							1
	SDIO							1
GPIOs			51					80			112
12-bit ADC			3					3			3
Number of channels			16					16			21
12-bit DAC								2
Number of channels								2
CPU frequency							72 MHz
Operating voltage							2.0 to 3.6 V
Operating temperatures		Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 10)
			Junction temperature: –40 to + 125 °C (see Table 10)
Package		LQFP64, WLCSP64					LQFP100, BGA100				LQFP144, BGA144

1.64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only.

2.For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.

3.The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.

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Description	STM32F103xC, STM32F103xD, STM32F103xE

Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram

TRACECLK TRACED[0:3] as AS

NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF

TPIU					@VDD
Trace/trig	Pbus	Trace			Power
SW/JTAG		controller
					VDD
		obl			Volt. reg.
	Ibus		ce	Flash 512 Kbytes	3.3 V to 1.8 V
		Flash	interfa
Cortex-M3 CPU
				64 bit	@VDDA
	Dbus
Fmax: 48/72 MHz					Supply
					supervision

	NVIC	aMtrix					@VDDA	POR			PVD
								Int
			64 KB
		System	SRAM					Reset			POR /PDR
		Bus
							RC 8 MHz

VSS

NRST

VDDA VSSA

							GP DMA1
A[25:0]
							7 channels
D[15:0]
CLK
NOE							GP DMA2
							5 channels
NWE
NE[4:1]
NBL[1:0]
NWAIT							FSMC
NL (or NADV)
as AF
D[7:0]							SDIO
CMD
CK as AF

MHz

/7284

Reset &

=

Clock

control

Fmax

AHB:

AHB2

AHB2

APB2 APB1

RC 40 kHz

@VDD

OSC_IN

PLL

XTAL OSC

OSC_OUT

4-16 MHz

PCLK1

IWDG

PCLK2

Standby

HCLK

interface

VBAT =1.8 V to 3.6 V

FCLK

@VBAT

OSC32_IN

XTAL32kHz

OSC32_OUT

RTC

Backup

TAMPER-RTC/

AWU

reg

ALARM/SECOND OUT

Backup

interface

4 channels, ETR as AF

TIM2

112AF EXT.IT WKUP

PA[15:0] GPIO port A PB[15:0] GPIO port B PC[15:0] GPIO port C

PD[15:0]					GPIO port D
PE[15:0]					GPIO port E

PF[15:0] GPIO port F

PG[15:0] GPIO port G

4 channels

3 compl. channels TIM1 BKIN, ETR as AF

APB2: Fmax = 48/72 MHz

MHz						TIM3
						TIM4
324/6
						TIM5
=
						USART2
max
F						USART3
APB1:
						UART4
						UART5
						SPI2/ I2S2
						2x(8x16it)b
						SPI3 / I2S3
						2x(8x16it)b

4 channels, ETR as AF

4 channels, ETR as AF 4 channels as AF

RX, TX, CTS, RTS,

CK as AF

RX, TX, CTS, RTS,

CK as AF

RX,TX as AF

RX,TX as AF

MOSI/SD, MISO

SCK/CK, MCK, NSS/WS as AF

MOSI/SD, MISO

SCK/CK, MCK, NSS/WS as AF

4 channels

TIM8

I2C1

3 compl. channels

SCL, SDA, SMBA as AF

BKIN, ETR as AF

SCL, SDA, SMBA as AF

MOSI, MISO,

SPI1

SRAM 512 B

I2C2

SCK, NSS as AF

RX, TX, CTS,

USART1

WWDG

bxCAN device

USBDP/CAN_TX

RTS, CK as AF

USB 2.0 FS

USBDM/CAN_RX

Temp. sensor

device

8 ADC123_INs

TIM6

IF

12bit DAC1

DAC_OUT1 as AF

12-bit ADC1

IF

common to the 3 ADCs

TIM7

IF

DAC_OUT2 as AF

12bit DAC 2

8 ADC12_INs common

12-bit ADC2

IF

to ADC1 & ADC2

5 ADC3_INs on ADC3

12-bit ADC3

IF

@VDDA

VREF–

VREF+

@ VDDA

ai14666f

1.TA = –40 °C to +85 °C (suffix 6, see Table 74) or –40 °C to +105 °C (suffix 7, see Table 74), junction temperature up to 105 °C or 125 °C, respectively.

2.AF = alternate function on I/O port pin.

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STM32F103xC, STM32F103xD, STM32F103xE	Description

Figure 2.	Clock tree
						FLITFCLK
						to Flash programming interface
					USB	48 MHz		USBCLK
					Prescaler			to USB interface
					/1, 1.5
						I2S3CLK				to I2S3
					Peripheral clock
					enable	I2S2CLK				to I2S2
					Peripheral clock					SDIOCLK
	8 MHz				enable						to SDIO
						Peripheral clock
		HSI
	HSI RC					enable				FSMCCLK
											to FSMC
						Peripheral clock
		/2
						enable			HCLK
						72 MHz max
									to AHB bus, core,
						Clock			memory and DMA
						Enable (4 bits)				to Cortex System timer
	PLLSRC			SW		/8
		PLLMUL							FCLK Cortex
		..., x16	HSI	SYSCLK	AHB	APB1			free running clock
							36 MHz max				PCLK1
		x2, x3, x4	PLLCLK	72 MHz	Prescaler	Prescaler
											to APB1
		PLL			/1, 2..512	/1, 2, 4, 8, 16
				max			Peripheral Clock				peripherals
			HSE
							Enable (20 bits)
						TIM2,3,4,5,6,7				to TIM2,3,4,5,6 and 7
						If (APB1 prescaler =1) x1
										TIMXCLK
				CSS			else	x2
									Peripheral Clock
									Enable (6 bits)
		PLLXTPRE				APB2	72 MHz max				PCLK2
						Prescaler
OSC_OUT										peripherals to APB2
	4-16 MHz					/1, 2, 4, 8, 16
							Peripheral Clock
OSC_IN	HSE OSC	/2					Enable (15 bits)
						TIM1 & 8 timers					to TIM1 and TIM8
						If (APB2 prescaler =1) x1
										TIMxCLK
							else x2
										Peripheral Clock
		/128
						ADC				Enable (2 bit)
OSC32_IN				to RTC							to ADC1, 2 or 3
	LSE OSC	LSE				Prescaler	ADCCLK
	32.768 kHz		RTCCLK			/2, 4, 6, 8
OSC32_OUT

RTCSEL[1:0]

/2

HCLK/2

To SDIO AHB interface

to Independent Watchdog (IWDG)

Peripheral clock

LSI RC

LSI

enable

40 kHz

IWDGCLK

Main

Legend:

/2

PLLCLK

MCO

Clock Output

HSI

HSE = High Speed External clock signal

HSI = High Speed Internal clock signal

HSE

LSI = Low Speed Internal clock signal

SYSCLK

LSE = Low Speed External clock signal

MCO

ai14752b

1.When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz.

2.For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz.

3.To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.

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Description	STM32F103xC, STM32F103xD, STM32F103xE

2.2Full compatibility throughout the family

The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices.

Low-density and high-density devices are an extension of the STM32F103x8/B mediumdensity devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC while remaining fully compatible with the other members of the family.

The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for the STM32F103x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices.

Table 3.

STM32F103xx family

Low-density devices

Medium-density devices

High-density devices

Pinout

16 KB

32 KB

64 KB

128 KB

256 KB

384 KB

512 KB

Flash

Flash(1)

Flash

Flash

Flash

Flash

Flash

6 KB RAM

10 KB RAM

20 KB RAM

20 KB RAM

48 RAM

64 KB RAM

64 KB RAM

144

5

× USARTs

4

× 16-bit timers, 2 × basic timers

100

3

× USARTs

3

× SPIs, 2 × I2Ss, 2 × I2Cs

2

× USARTs

3

× 16-bit timers

USB, CAN, 2 × PWM timers

64

2

× SPIs, 2 × I2Cs, USB,

3

× ADCs, 2 × DACs, 1 × SDIO

2

× 16-bit timers

CAN, 1 × PWM timer

FSMC (100and 144-pin packages(2))

1

× SPI, 1 × I2C, USB,

2

× ADCs

48

CAN, 1 × PWM timer

2

× ADCs

36

1.For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices.

2.Ports F and G are not available in devices delivered in 100-pin packages.

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STM32F103xC, STM32F103xD, STM32F103xE	Description

2.3Overview

2.3.1ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

With its embedded ARM core, STM32F103xC, STM32F103xD and STM32F103xE performance line family is compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2Embedded Flash memory

Up to 512 Kbytes of embedded Flash is available for storing programs and data.

2.3.3CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

2.3.4Embedded SRAM

Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

2.3.5FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND.

Functionality overview:

●The three FSMC interrupt lines are ORed in order to be connected to the NVIC

●Write FIFO

●Code execution from external memory except for NAND Flash and PC Card

●The targeted frequency, fCLK, is HCLK/2, so external access is at 36 MHz when HCLK is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz

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Description	STM32F103xC, STM32F103xD, STM32F103xE

2.3.6LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.

2.3.7Nested vectored interrupt controller (NVIC)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

●Closely coupled NVIC gives low latency interrupt processing

●Interrupt entry vector table address passed directly to the core

●Closely coupled NVIC core interface

●Allows early processing of interrupts

●Processing of late arriving higher priority interrupts

●Support for tail-chaining

●Processor state automatically saved

●Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

2.3.8External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines.

2.3.9Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. See Figure 2 for details on the clock tree.

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STM32F103xC, STM32F103xD, STM32F103xE	Description

2.3.10Boot modes

At startup, boot pins are used to select one of three boot options:

●Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes.

●Boot from system memory

●Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1.

2.3.11Power supply schemes

●VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins.

●VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is used). VDDA and VSSA must be connected to VDD and VSS, respectively.

●VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

For more details on how to connect power pins, refer to Figure 12: Power supply scheme.

2.3.12Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher

than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.

2.3.13Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●MR is used in the nominal regulation mode (Run)

●LPR is used in the Stop modes.

●Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

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Description	STM32F103xC, STM32F103xD, STM32F103xE

2.3.14Low-power modes

The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

●Stop mode

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.

●Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

Note:	The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
	or Standby mode.

2.3.15 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to- peripheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced-control timers TIMx, DAC, I2S, SDIO and ADC.

2.3.16 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present.

They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a

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STM32F103xC, STM32F103xD, STM32F103xE	Description

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.17Timers and watchdogs

The high-density STM32F103xx performance line devices include up to two advancedcontrol timers, up to four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer.

Table 4 compares the features of the advanced-control, general-purpose and basic timers.

Table 4.		High-density timer feature comparison
Timer		Counter	Counter	Prescaler	DMA request	Capture/compare	Complementary
		resolution	type	factor	generation	channels	outputs
TIM1,			Up,	Any integer
		16-bit	down,	between 1	Yes	4	Yes
TIM8
			up/down	and 65536
TIM2,			Up,	Any integer
TIM3,
		16-bit	down,	between 1	Yes	4	No
TIM4,
			up/down	and 65536
TIM5
TIM6,				Any integer
		16-bit	Up	between 1	Yes	0	No
TIM7
				and 65536

Advanced-control timers (TIM1 and TIM8)

The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:

●Input capture

●Output compare

●PWM generation (edge or center-aligned modes)

●One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.

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Description	STM32F103xC, STM32F103xD, STM32F103xE

General-purpose timers (TIMx)

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages.

The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

●A 24-bit down counter

●Autoreload capability

●Maskable system interrupt generation when the counter reaches 0.

●Programmable clock source

2.3.18I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

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2.3.19Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.

2.3.20Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

2.3.21Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 48 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

2.3.22SDIO

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD Memory Card Specifications Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital protocol Rev1.1.

2.3.23Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.

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Description	STM32F103xC, STM32F103xD, STM32F103xE

2.3.24Universal serial bus (USB)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

2.3.25GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

2.3.26ADC (analog to digital converter)

Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD and STM32F103xE performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

●Simultaneous sample and hold

●Interleaved sample and hold

●Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

2.3.27DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

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This dual digital Interface supports the following features:

●two DAC converters: one for each output channel

●8-bit or 12-bit monotonic output

●left or right data alignment in 12-bit mode

●synchronized update capability

●noise-wave generation

●triangular-wave generation

●dual DAC channel independent or simultaneous conversions

●DMA capability for each channel

●external triggers for conversion

●input voltage reference VREF+

Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

2.3.28Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

2.3.29Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

2.3.30Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

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Pinouts and pin descriptions	STM32F103xC, STM32F103xD, STM32F103xE

3 Pinouts and pin descriptions

Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout

1

2

3

4

5

6

7

8

9

10

11

12

A

PC13-

PE3

PE2

PE1

PE0

PB4

PB3

PD6

PD7

PA15

PA14

PA13

JTRST

JTDO

JTDI

JTCK

JTMS

TAMPER-RTC

B

PC14-

PE4

PE5

PE6

PB9

PB5

PG15

PG12

PD5

PC11

PC10

PA12

OSC32_IN

C

PC15-

VBAT

PF0

PF1

PB8

PB6

PG14

PG11

PD4

PC12

NC

PA11

OSC32_OUT

D

OSC_IN

VSS_5

VDD_5

PF2

BOOT0

PB7

PG13

PG10

PD3

PD1

PA10

PA9

E

OSC_OUT

PF3

PF4

PF5

VSS_3

VSS_11

VSS_10

PG9

PD2

PD0

PC9

PA8

F

NRST

PF7

PF6

VDD_4

VDD_3

VDD_11

VDD_10

VDD_8

VDD_2

VDD_9

PC8

PC7

G

PF10

PF9

PF8

VSS_4

VDD_6

VDD_7

VDD_1

VSS_8

VSS_2

VSS_9

PG8

PC6

H

PC0

PC1

PC2

PC3

VSS_6

VSS_7

VSS_1

PE11

PD11

PG7

PG6

PG5

J

VSSA

PA0-WKUP

PA4

PC4

PB2/

PG1

PE10

PE12

PD10

PG4

PG3

PG2

BOOT1

K

VREF–

PA1

PA5

PC5

PF13

PG0

PE9

PE13

PD9

PD13

PD14

PD15

L

VREF+

PA2

PA6

PB0

PF12

PF15

PE8

PE14

PD8

PD12

PB14

PB15

M

VDDA

PA3

PA7

PB1

PF11

PF14

PE7

PE15

PB10

PB11

PB12

PB13

AI14798b

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	STM32F103xC, STM32F103xD, STM32F103xE								Pinouts and pin descriptions
	Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout
		1	2	3	4	5	6	7	8	9	10
	A	PC14-	PC13-	PE2	PB9	PB7	PB4	PB3	PA15	PA14	PA13
		OSC32_INTAMPER-RTC
		PC15-					PD5
	B	OSC32_OUT VBAT		PE3	PB8	PB6		PD2	PC11	PC10	PA12
	C	OSC_IN	VSS_5	PE4	PE1	PB5	PD6	PD3	PC12	PA9	PA11
	D	OSC_OUT VDD_5		PE5	PE0	BOOT0	PD7	PD4	PD0	PA8	PA10
	E	NRST	PC2	PE6	VSS_4	VSS_3	VSS_2	VSS_1	PD1	PC9	PC7
	F	PC0	PC1	PC3	VDD_4	VDD_3	VDD_2	VDD_1	NC	PC8	PC6
	G	VSSA	PA0-WKUP	PA4	PC4	PB2	PE10	PE14	PB15	PD11	PD15
	H	VREF–	PA1	PA5	PC5	PE7	PE11	PE15	PB14	PD10	PD14
	J	VREF+	PA2	PA6	PB0	PE8	PE12	PB10	PB13	PD9	PD13
	K	VDDA	PA3	PA7	PB1	PE9	PE13	PB11	PB12	PD8	PD12
											AI14601c

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Pinouts and pin descriptions	STM32F103xC, STM32F103xD, STM32F103xE

Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout

PE2	1
PE3	2
PE4	3
PE5	4
PE6	5
VBAT	6
PC13-TAMPER-RTC	7
PC14-OSC32_IN	8
PC15-OSC32_OUT	9
PF0	10
PF1	11
PF2	12
PF3	13
PF4	14
PF5	15
VSS_5	16
VDD_5	17
PF6	18
PF7	19
PF8	20
PF9	21
PF10	22
OSC_IN	23
OSC_OUT	24
NRST	25
PC0	26
PC1	27
PC2	28
PC3	29
VSSA	30
VREF-	31
VREF+	32
VDDA	33
PA0-WKUP	34
PA1	35
PA2	36

DD 3		SS 3			PE1			PE0
V		V
144		143			142			141

	37			38			39			40
PA3				SS 4			DD 4 PA4
			V			V

PB9		PB8			BOOT0			PB7		PB6			PB5			PB4			PB3			PG15			V				V				PG14		PG13			PG12			PG11			PG10
																										DD11				SS11
140		139			138			137			136			135			134			133			132			131				130			129			128			127			126			125

LQFP144

	41			42				43				44				45				46				47				48				49				50				51				52				53				54			55			56
PA5			PA6				PA7				PC4				PC5				PB0				PB1				PB2				PF11				PF12					VSS6			V				PF13			PF14				PF15			PG0
																																												DD6

PG9			PD7			PD6				DD 10				SS 10		PD5		PD4
									V				V
	124			123			122			121
														120			119		118

	57			58			59			60				61		62		63
PG1			PE7			PE8			PE9					SS 7		DD 7 PE10
													V			V

PD3				PD2				PD1				PD0				PC12				PC11				PC10				PA15 PA14
																																	109
	117				116				115				114				113					112				111				110
																																	108						VDD_2
																																	107
																																							VSS_2
																																	106
																																							NC
																																	105
																																							PA13
																																	104
																																							PA12
																																	103
																																							PA11
																																	102
																																							PA10
																																	101
																																							PA9
																																	100
																																							PA8
																																	99
																																							PC9
																																	98
																																							PC8
																																	97
																																							PC7
																																	96
																																							PC6
																																	95
																																							VDD_9
																																	94
																																							VSS_9
																																	93
																																							PG8
																																	92
																																							PG7
																																	91
																																							PG6
																																	90
																																							PG5
																																	89
																																							PG4
																																	88
																																							PG3
																																	87
																																							PG2
																																	86
																																							PD15
																																	85
																																							PD14
																																	84
																																							VDD_8
																																	83						VSS_8
																																							PD13
																																	82
																																							PD12
																																	81
																																							PD11
																																	80
																																							PD10
																																	79
																																	78						PD9
																																	77						PD8
																																	76						PB15
																																	75						PB14
																																	74						PB13
																																							PB12
																																	73
		64				65				66				67				68			69				70				71					72
	PE11				PE12				PE13				PE14				PE15					PB10				PB11				SS_1				DD_1
																														V			V

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STM32F103xC, STM32F103xD, STM32F103xE																			Pinouts and pin descriptions
	Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout
		VDD 3	VSS 3	PE1	PE0	PB9	PB8	BOOT0	PB7	PB6	PB5	PB4	PB3	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0	PC12	PC11	PC10	PA15	PA14
	PE2	100	99	98	97	96	95	94	93	92	91	90	89	88	87	86	85	84	83	82	81	80	79	78	77	76
		1																								75	VDD_2
	PE3	2																								74	VSS_2
	PE4	3																								73	NC
	PE5	4																								72	PA 13
	PE6	5																								71	PA 12
	VBAT	6																								70	PA 11
	PC13-TAMPER-RTC 7																									69	PA 10
	PC14-OSC32_IN	8																								68	PA 9
	PC15-OSC32_OUT	9																								67	PA 8
	VSS_5	10																								66	PC9
	VDD_5	11																								65	PC8
	OSC_IN	12										LQFP100														64	PC7
	OSC_OUT	13																								63	PC6
	NRST	14																								62	PD15
	PC0	15																								61	PD14
	PC1	16																								60	PD13
	PC2	17																								59	PD12
	PC3	18																								58	PD11
	VSSA	19																								57	PD10
	VREF-	20																								56	PD9
	VREF+	21																								55	PD8
	VDDA	22																								54	PB15
	PA0-WKUP	23																								53	PB14
	PA1	24																								52	PB13
	PA2	25																								51	PB12
		26	27	28	29	30	31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50
		PA3	VSS 4	VDD 4	PA4	PA5	PA6	PA7	PC4	PC5	PB0	PB1	PB2	PE7	PE8	PE9	PE10	PE11	PE12	PE13	PE14	PE15	PB10	PB11	VSS 1	VDD 1
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Pinouts and pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Figure 7. STM32F103xC and STM32F103xE performance line

LQFP64 pinout

VDD 3

VSS 3

PB9

PB8

BOOT0

PB7

PB6 PB5 PB4 PB3

PD2

PC12

PC11

PC10

PA15

PA14

VBAT

VDD_2

PC13-TAMPER-RTC

VSS_2

PC14-OSC32_IN

PA13

PC15-OSC32_OUT

PA12

PD0 OSC_IN

PA11

PD1 OSC_OUT

PA10

NRST

PA9

PC0

LQFP64

PA8

PC1

PC9

PC2

PC8

PC3

PC7

VSSA

PC6

VDDA

PB15

PA0-WKUP

PB14

PA1

PB13

PA2

PB12

PA3

VSS 4

VDD 4

PA4

PA5

PA6

PA7 PC4 PC5 PB0

PB1

PB2

PB10

PB11

VSS 1

VDD 1

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STM32F103xC, STM32F103xD, STM32F103xE	Pinouts and pin descriptions

Figure 8. STM32F103xC and STM32F103xE performance line

WLCSP64 ballout, ball side

		8	7	6	5	4	3	2	1
	A	VDD_3	VSS_3	BOOT0	PB5	PB3	PD2	PC10	VDD_2
	B	PC14	PC15	PB9	PB6	PB4	PC11	PA14	BYPASS/
									VSS_2
	C	PC13	NRST	VBAT	PB7	PC12	PA15	PA12	PA11
	D	OSC_IN	OSC_OUT	PC2	PB8	PA13	PA10	PA9	PC9
	E	PC0	VSSA	PA1	PA5	PA8	PC8	PC7	PC6
	F	PC1	VREF+	PA0-	VSS_4	PB1	PB11	PB14	PB15
				WKUP
	G	VDDA	PA3	VDD_4	PA6	PA7	PB10	PB12	PB13
	H	PA2	PA4	PC4	PC5	PB0	PB2	VSS_1	VDD_1
									ai15460b

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Pinouts and pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Table 5.

High-density STM32F103xx pin definitions

Pins

(2)

Alternate functions(4)

(1)

LevelO/I

Main

LFBGA144

LFBGA100

WLCSP64

LQFP64

LQFP100

LQFP144

Pin name

Type

function(3)

Default

Remap

(after reset)

A3

A3

-

-

1

1

PE2

I/O

FT

PE2

TRACECK/ FSMC_A23

A2

B3

-

-

2

2

PE3

I/O

FT

PE3

TRACED0/FSMC_A19

B2

C3

-

-

3

3

PE4

I/O

FT

PE4

TRACED1/FSMC_A20

B3

D3

-

-

4

4

PE5

I/O

FT

PE5

TRACED2/FSMC_A21

B4

E3

-

-

5

5

PE6

I/O

FT

PE6

TRACED3/FSMC_A22

C2

B2

C6

1

6

6

VBAT

S

VBAT

A1

A2

C8

2

7

7

PC13-TAMPER-

I/O

PC13(6)

TAMPER-RTC

RTC(5)

B1

A1

B8

3

8

8

PC14-

I/O

PC14(6)

OSC32_IN

OSC32_IN(5)

C1

B1

B7

4

9

9

PC15-

I/O

PC15(6)

OSC32_OUT

OSC32_OUT(5)

C3

-

-

-

-

10

PF0

I/O

FT

PF0

FSMC_A0

C4

-

-

-

-

11

PF1

I/O

FT

PF1

FSMC_A1

D4

-

-

-

-

12

PF2

I/O

FT

PF2

FSMC_A2

E2

-

-

-

-

13

PF3

I/O

FT

PF3

FSMC_A3

E3

-

-

-

-

14

PF4

I/O

FT

PF4

FSMC_A4

E4

-

-

-

-

15

PF5

I/O

FT

PF5

FSMC_A5

D2

C2

-

-

10

16

VSS_5

S

VSS_5

D3

D2

-

-

11

17

VDD_5

S

VDD_5

F3

-

-

-

-

18

PF6

I/O

PF6

ADC3_IN4/FSMC_NIORD

F2

-

-

-

-

19

PF7

I/O

PF7

ADC3_IN5/FSMC_NREG

G3

-

-

-

-

20

PF8

I/O

PF8

ADC3_IN6/FSMC_NIOWR

G2

-

-

-

-

21

PF9

I/O

PF9

ADC3_IN7/FSMC_CD

G1

-

-

-

-

22

PF10

I/O

PF10

ADC3_IN8/FSMC_INTR

D1

C1

D8

5

12

23

OSC_IN

I

OSC_IN

E1

D1

D7

6

13

24

OSC_OUT

O

OSC_OUT

F1

E1

C7

7

14

25

NRST

I/O

NRST

H1

F1

E8

8

15

26

PC0

I/O

PC0

ADC123_IN10

H2

F2

F8

9

16

27

PC1

I/O

PC1

ADC123_IN11

H3

E2

D6

10

17

28

PC2

I/O

PC2

ADC123_IN12

H4

F3

-

11

18

29

PC3

I/O

PC3

ADC123_IN13

J1

G1

E7

12

19

30

VSSA

S

VSSA

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