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UC2842A/3A/4A/5A |
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UC3842A/3A/4A/5A |
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
.TRIMMED OSCILLATOR DISCHARGE CUR-
.RENT
.CURRENT MODE OPERATION TO 500kHz
AUTOMATIC FEED FORWARD COMPENSA-
.TION
LATCHING PWM FOR CYCLE-BY-CYCLE
.CURRENT LIMITING
INTERNALLY TRIMMED REFERENCE WITH
.UNDERVOLTAGE LOCKOUT
.HIGH CURRENT TOTEM POLE OUTPUT UNDERVOLTAGE LOCKOUT WITH HYSTER-
.ESIS
.LOW START-UP CURRENT (< 0.5mA) DOUBLE PULSE SUPPRESSION
DESCRIPTION
TheUC384xA family ofcontrolICsprovidesthenecessary features to implement off-line or DC to DC fixed frequencycurrent mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lock- outfeaturingstart-up current less than0.5mA,a precision reference trimmed for accuracy at the error amp input, logicto insure latched operation,a PWM
Mini dip |
SO8 |
comparatorwhich alsoprovidescurrent limit control, and a totem pole output stage designed to source or sink high peakcurrent. The outputstage, suitable for driving N-Channel MOSFETs, is low in the offstate.
Differences between members of this family are the under-voltagelockout thresholdsand maximum duty cycle ranges. The UC3842A and UC3844A have UVLO thresholds of 16V (on) and 10V (off), ideally suitedoff-lineapplicationsThecorrespondingthresh- olds for the UC3843A and UC3845A are 8.5 V and 7.9V. The UC3842A and UC3843A can operate to dutycycles approaching100%.A range of the zeroto < 50 % is obtainedby theUC3844Aand UC3845Aby theaddition of an internal toggle flip flopwhich blanks the output off every otherclock cycle.
BLOCK DIAGRAM (toggle flip flop used only in UC3844A and UC3845A)
7
Vi |
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34V |
UVLO |
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5V |
8 VREF |
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5 |
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S/R |
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GROUND |
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REF |
5V 50mA |
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INTERNAL |
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2.50V |
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BIAS |
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VREF GOOD |
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LOGIC |
6 |
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4 |
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OUTPUT |
RT/CT |
OSC |
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T |
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+ |
ERROR AMP. |
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2R |
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VFB |
2 |
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R |
PWM |
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R |
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1 |
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1V |
LATCH |
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COMP |
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CURRENT |
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3 |
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SENSE |
UC3842A |
CURRENT |
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COMPARATOR |
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SENSE
D95IN331
March 1999 |
1/15 |
UC2842A/3A/4A/5A - UC3842A/3A/4A/5A
ABSOLUTE MAXIMUM RATINGS
Symbol |
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Parameter |
Valu e |
Un it |
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Vi |
Supply Voltage (low impedance source) |
30 |
V |
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Vi |
Supply Voltage (Ii < 30mA) |
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Self Limiting |
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IO |
Output Current |
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±1 |
A |
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EO |
Output Energy (capacitive load) |
5 |
μJ |
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Analog Inputs (pins 2, 3) |
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± 0.3 to 5.5 |
V |
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Error Amplifier Output Sink Current |
10 |
mA |
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P |
tot |
Power Dissipation at Tamb |
≤ |
25 |
° |
1.25 |
W |
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C (Minidip) |
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Ptot |
Power Dissipation at Tamb ≤ 25 °C (SO8) |
800 |
mW |
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Tstg |
Storage Temperature Range |
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± 65 to 150 |
°C |
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TJ |
Junction Operating Temperature |
± 40 to 150 |
°C |
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TL |
Lead Temperature (soldering 10s) |
300 |
°C |
* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
PIN CONNECTION (top view)
Minidip/SO8
COMP |
1 |
8 |
VREF |
VFB |
2 |
7 |
Vi |
ISENSE |
3 |
6 |
OUTPUT |
RT/CT |
4 |
5 |
GROUND |
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D95IN332 |
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PIN FUNCTIONS
No |
Function |
Description |
1 |
COMP |
This pin is the Error Amplifier output and is made available for loop compensation. |
2 |
VFB |
This is the inverting input of the Error Amplifier. It is normally connected to the switching |
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power supply output through a resistor divider. |
3ISENSE
4RT/CT
A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction.
The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible.
5 |
GROUND |
This pin is the combined control circuitry and power ground. |
6 |
OUTPUT |
This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced |
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and sunk by this pin. |
7 |
VCC |
This pin is the positive supply of the control IC. |
8 |
Vref |
This is the reference output. It provides charging current for capacitor CT through resistor RT. |
ORDERING NUMBERS
SO8 |
Minidip |
UC2842AD1; UC3842AD1 |
UC2842AN; UC3842AN |
UC2843AD1; UC3843AD1 |
UC2843AN; UC3843AN |
UC2844AD1; UC3844AD1 |
UC2844AN; UC3844AN |
UC2845AD1; UC3845AD1 |
UC2845AN; UC3845AN |
2/15
UC2842A/3A/4A/5A - UC3842A/3A/4A/5A
THERMAL DATA
Symbo l |
Descri ption |
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Minid ip |
SO 8 |
Unit |
Rth j-amb |
Thermal Resistance Junction-ambient. |
max. |
100 |
150 |
°C/W |
ELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA; 0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbo l |
Parameter |
T est Cond it ion s |
UC284XA |
UC384XA |
Uni t |
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Mi n. T yp. Max. Min. Typ . Max. |
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REFERENCE SECTION |
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VREF |
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Output Voltage |
Tj = 25°C Io = 1mA |
4.95 |
5.00 |
5.05 |
4.90 |
5.00 |
5.10 |
V |
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VREF |
Line Regulation |
12V ≤ Vi ≤ 25V |
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2 |
20 |
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2 |
20 |
mV |
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VREF |
Load Regulation |
1 ≤ Io ≤ 20mA |
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3 |
25 |
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3 |
25 |
mV |
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VREF/ |
T |
Temperature Stability |
(Note 2) |
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0.2 |
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0.2 |
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mV/°C |
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Total Output Variation |
Line, Load, Temperature |
4.9 |
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5.1 |
4.82 |
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5.18 |
V |
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eN |
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Output Noise Voltage |
10Hz ≤ f ≤ 10KHz Tj = 25°C |
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50 |
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50 |
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μV |
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(note 2) |
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Long Term Stability |
Tamb = 125°C, 1000Hrs |
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5 |
25 |
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5 |
25 |
mV |
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(note 2) |
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ISC |
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Output Short Circuit |
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-30 |
-100 |
-180 |
-30 |
-100 |
-180 |
mA |
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OSCILLATOR SECTION |
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f |
OSC |
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Frequency |
° |
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47 |
52 |
57 |
47 |
52 |
57 |
KHz |
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Tj = 25 C |
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fOSC/ |
V |
Frequency Change with Volt. |
VCC = 12V to 25V |
± |
0.2 |
1 |
± |
0.2 |
1 |
% |
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fOSC/ |
T |
Frequency Change with Temp. |
TA = Tlow to Thigh |
± |
5 |
± |
± |
5 |
± |
% |
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VOSC |
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Oscillator Voltage Swing |
(peak to peak) |
± |
1.6 |
± |
± |
1.6 |
± |
V |
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Idischg |
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Discharge Current (VOSC =2V) |
TJ = 25°C |
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7.8 |
8.3 |
8.8 |
7.8 |
8.3 |
8.8 |
mA |
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ERROR AMP SECTION |
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V2 |
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Input Voltage |
VPIN1 = 2.5V |
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2.45 |
2.50 |
2.55 |
2.42 |
2.50 |
2.58 |
V |
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Ib |
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Input Bias Current |
VFB = 5V |
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-0.1 |
-1 |
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-0.1 |
-2 |
μA |
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AVOL |
2V ≤ Vo ≤ 4V |
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65 |
90 |
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65 |
90 |
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dB |
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BW |
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Unity Gain Bandwidth |
TJ = 25°C |
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0.7 |
1 |
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0.7 |
1 |
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MHz |
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PSRR |
Power Supply Rejec. Ratio |
12V ≤ Vi ≤ 25V |
60 |
70 |
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60 |
70 |
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dB |
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Io |
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Output Sink Current |
VPIN2 = 2.7V |
VPIN1 = 1.1V |
2 |
12 |
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2 |
12 |
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mA |
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Io |
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Output Source Current |
VPIN2 = 2.3V |
VPIN1 = 5V |
-0.5 |
-1 |
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-0.5 |
-1 |
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mA |
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VOUT High |
VPIN2 = 2.3V; |
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5 |
6.2 |
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5 |
6.2 |
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V |
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RL = 15KΩ to Ground |
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VOUT Low |
VPIN2 = 2.7V; |
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0.8 |
1.1 |
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0.8 |
1.1 |
V |
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RL = 15KΩ to Pin 8 |
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CURRENT SENSE SECTION |
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GV |
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Gain |
(note 3 & 4) |
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2.85 |
3 |
3.15 |
2.85 |
3 |
3.15 |
V/V |
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V3 |
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Maximum Input Signal |
VPIN1 = 5V (note 3) |
0.9 |
1 |
1.1 |
0.9 |
1 |
1.1 |
V |
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SVR |
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Supply Voltage Rejection |
12 ≤ Vi ≤ 25V (note 3) |
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70 |
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70 |
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dB |
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Ib |
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Input Bias Current |
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-2 |
-10 |
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-2 |
-10 |
μA |
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Delay to Output |
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150 |
300 |
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150 |
300 |
ns |
3/15
UC2842A/3A/4A/5A - UC3842A/3A/4A/5A
ELECTRICAL CHARACTERISTICS (continued)
Symbo l |
Parameter |
T est Cond iti ons |
UC284XA |
UC384XA |
Un it |
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Min . Typ . Max. Mi n. T yp. Max. |
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OUTPUT SECTION |
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VOL |
Output Low Level |
ISINK = 20mA |
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0.1 |
0.4 |
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0.1 |
0.4 |
V |
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ISINK = 200mA |
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1.6 |
2.2 |
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1.6 |
2.2 |
V |
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VOH |
Output High Level |
ISOURCE = 20mA |
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13 |
13.5 |
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13 |
13.5 |
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V |
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ISOURCE = 200mA |
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12 |
13.5 |
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12 |
13.5 |
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V |
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VOLS |
UVLO Saturation |
VCC = 6V; ISINK = 1mA |
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0.7 |
1.2 |
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0.7 |
1.2 |
V |
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t |
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Rise Time |
° |
CL |
= 1nF |
(2) |
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50 |
150 |
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50 |
150 |
ns |
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r |
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Tj = 25 C |
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t |
f |
Fall Time |
° |
CL |
= 1nF |
(2) |
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50 |
150 |
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50 |
150 |
ns |
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Tj = 25 C |
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UNDER-VOLTAGE LOCKOUT SECTION |
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Start Threshold |
X842A/4A |
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15 |
16 |
17 |
14.5 |
16 |
17.5 |
V |
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X843A/5A |
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7.8 |
8.4 |
9.0 |
7.8 |
8.4 |
9.0 |
V |
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Min Operating Voltage |
X842A/4A |
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9 |
10 |
11 |
8.5 |
10 |
11.5 |
V |
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After Turn-on |
X843A/5A |
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7.0 |
7.6 |
8.2 |
7.0 |
7.6 |
8.2 |
V |
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PWM SECTION |
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Maximum Duty Cycle |
X842A/3A |
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94 |
96 |
100 |
94 |
96 |
100 |
% |
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X844A/5A |
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47 |
48 |
50 |
47 |
48 |
50 |
% |
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Minimum Duty Cycle |
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0 |
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0 |
% |
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TOTAL STANDBY CURRENT |
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Ist |
Start-up Current |
Vi = 6.5V for UCX843A/45A |
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0.3 |
0.5 |
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0.3 |
0.5 |
mA |
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Vi = 14V for UCX842A/44A |
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0.3 |
0.5 |
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0.3 |
0.5 |
mA |
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Ii |
Operating Supply Current |
VPIN2 = VPIN3 = 0V |
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12 |
17 |
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12 |
17 |
mA |
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Viz |
Zener Voltage |
Ii = 25mA |
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30 |
36 |
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30 |
36 |
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V |
Notes : 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to Tamb as possible.
2.These parameters, although guaranteed, are not 100% tested in production.
3.Parameter measured at trip point of latch with V PIN2 = 0.
4.Gain defined as :
VPIN1
A =
VPIN3
5. Adjust Vi above the start threshold before setting at 15 V.
4/15
UC2842A/3A/4A/5A - UC3842A/3A/4A/5A
Figure 1: Open Loop Test Circuit.
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VREF |
4.7KΩ |
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RT |
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2N2222 |
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VREF |
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A |
Vi |
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0.1μF |
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100KΩ |
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COMP |
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8 |
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1 |
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VFB |
7 |
Vi |
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ERROR AMP. |
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2 |
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1W |
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ADJUST |
Ω |
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0.1 |
μ |
F |
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1K |
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ISENSE |
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UC3842A |
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1KΩ |
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4.7KΩ |
ISENSE |
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3 |
OUTPUT |
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ADJUST |
Ω |
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6 |
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OUTPUT |
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5K |
RT/CT |
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4 |
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GROUND |
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5 |
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CT |
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D95IN343 |
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GROUND |
High peak currentsassociatedwith capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close
Figure 2: Oscillator Frequency vs Timing Resistance
fo |
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D96IN362 |
(Hz) |
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1M |
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CT=470pF |
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1nF |
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100K |
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2. |
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2nF |
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4. |
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7nF |
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10K |
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1K |
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RT(Ω) |
300 |
1K |
3K |
10K |
30K |
to pin 5 in a single point ground. The transistor and 5 KΩ potentiometerareusedto samplethe oscillator waveform and apply an adjustable ramp to pin 3.
Figure 3: Maximum Duty Cycle vs Timing Resistor
fo |
D96IN363 |
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(Hz) |
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80
60
40
20
0
300 |
1K |
3K |
10K |
30K |
RT(Ω) |
5/15