ST M24C16-W, M24C16-R, M24C16-F, M24C08-W, M24C08-R User Manual

M24C16-x M24C08-x

M24C04-x M24C02-x M24C01-x

16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit serial I²C bus EEPROM

Features

■Supports both the 100 kHz I2C Standard-mode and the 400 kHz I2C Fast-mode

■Single supply voltage:

–2.5 V to 5.5 V for M24Cxx-W

–1.8 V to 5.5 V for M24Cxx

–1.7 V to 5.5 V for M24Cxx-F

■Write Control input

■Byte and Page Write (up to 16 bytes)

■Random and Sequential Read modes

■Self-timed programming cycle

■Automatic address incrementing

■Enhanced ESD/latch-up protection

■More than 1 million write cycles

■More than 40-year data retention

■Packages:

–SO8, TSSOP8, UFDFPN8: ECOPACK2® (RoHS-compliant and Halogen-free)

–PDIP8: ECOPACK1® (RoHS-compliant)

	Table 1.	Device summary
	Reference		Part number
			M24C16-W
	M24C16-x		M24C16-R
			M24C16-F
			M24C08-W
	M24C08-x		M24C08-R
			M24C08-F
			M24C04-W
	M24C04-x		M24C04-R
			M24C04-F
	M24C02-x		M24C02-W
			M24C02-R
	M24C01-x		M24C01-W
			M24C01-R

PDIP8 (BN)

SO8 (MN) 150 mils width

TSSOP8 (DW) 169 mils width

UFDFPN8 (MB, MC) 2 × 3 mm (MLP)

WLCSP (CS)(1)

Thin WLCSP (CT)(2)

1.Only M24C08-F and M24C16-F devices are offered in the WLCSP package.

2.Only M24C08-F devices are offered in the Thin WLCSP package.

April 2011

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www.st.com

Contents	M24C16, M24C08, M24C04, M24C02, M24C01

Contents

1	Description .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
2	Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			8
	2.1	Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	2.2	Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	2.3	Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
		2.3.1	Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 8
	2.4	Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
		2.4.1	Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
		2.4.2	Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
		2.4.3	Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
		2.4.4	Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
3	Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			11
	3.1	Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	3.2	Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	3.3	Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	3.4	Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	3.5	Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	3.6	Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13

3.6.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.3 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 16

3.7 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.4 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4	Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
5	Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
6	DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

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M24C16, M24C08, M24C04, M24C02, M24C01		Contents
7	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 27
8	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 33
9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 34

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List of tables	M24C16, M24C08, M24C04, M24C02, M24C01

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Operating conditions (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Operating conditions (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Operating conditions (M24Cxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9. DC characteristics (M24Cxx-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. DC characteristics (M24Cxx-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 11. DC characteristics (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 12. DC characteristics (M24Cxx-F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 13. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 14. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 15. AC characteristics at 400 kHz (I2C Fast-mode) (M24Cxx-W, M24Cxx-R,

M24Cxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 16. AC characteristics at 100 kHz (I2C Standard-mode) (M24Cxx-W,

M24Cxx-R, M24Cxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 17. M24C08: WLCSP (0.5 mm height) 0.4 mm pitch, 5 bumps, package data . . . . . . . . . . . . 27 Table 18. M24C08: Thin WLCSP (0.3 mm height), 0.4 mm pitch, 5 bumps, package data . . . . . . . . 28 Table 19. M24C16: WLCSP (0.5 mm height) 0.4 mm pitch, 5 bumps, package data . . . . . . . . . . . . 28 Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 22. TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 31 Table 23. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 32 Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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M24C16, M24C08, M24C04, M24C02, M24C01	List of figures

List of figures

Figure 1.	Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 2.	8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
Figure 3.	WLCSP and thin WLCSP connections
	(top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
Figure 4.	Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 8
Figure 5.	Maximum RP value versus bus parasitic capacitance (C) for an I²C bus . . . . . . . . . . . . . .	9
Figure 6.	I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Figure 7.	Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . .	13
Figure 8.	Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . .	15
Figure 9.	Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 10.	Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 11.	AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 12.	AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 13. WLCSP (0.5 mm) and Thin WLCSP (0.3 mm) 0.4 mm pitch 5 bumps,
	package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 14.	SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . .	29
Figure 15.	UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
	2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Figure 16.	TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 17.	PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . .	32

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Description	M24C16, M24C08, M24C04, M24C02, M24C01

1 Description

These I²C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 2048/1024/512/256/128 x 8 (M24C16, M24C08, M24C04, M24C02 and M24C01).

Figure 1. Logic diagram

	VCC
	3
E0-E2	SDA
SCL	M24Cxx
WC
	VSS
	AI02033

I²C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C bus definition.

The device behaves as a slave in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in Table 3), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Table 2.			Signal names
		Signal name		Function	Direction
	E0, E1, E2			Chip Enable	Input
	SDA			Serial Data	Input/output
	SCL			Serial Clock	Input
				Write Control	Input
	WC
	VCC			Supply voltage
	VSS			Ground

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M24C16, M24C08, M24C04, M24C02, M24C01	Description

Figure 2. 8-pin package connections (top view)

M24Cxx

16Kb / 8Kb / 4Kb / 2Kb / 1Kb

NC / NC / NC

/

E0

/

E0

1

8

VCC

NC / NC

/ E1

/

E1

/

E1

2

7

WC

NC / E2

/ E2

/

E2

/

E2

3

6

SCL

VSS

4

5

SDA

AI02034F

1.NC = Not connected

2.See Section 7: Package mechanical data for package dimensions, and how to identify pin-1.

3.The Ei inputs are not decoded, and are therefore decoded as “0” (See Section 2.3: Chip Enable (E0, E1, E2) for more information).

Figure 3. WLCSP and thin WLCSP connections

(top view, marking side, with balls on the underside)

WC VCC

SDA

SCL VSS

ai14908

1.For devices of less than 16Kb (see Figure 2: 8-pin package connections (top view)), the Ei inputs are not connected to a ball, therefore the Ei input is decoded as "0" (see also Section 2.3: Chip Enable (E0, E1, E2))

Caution: EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to ultra violet (UV) light, since EEPROM cells loose their charge (and so their binary value) when exposed to UV light.

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Signal description	M24C16, M24C08, M24C04, M24C02, M24C01

2 Signal description

2.1Serial Clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.

2.2Serial Data (SDA)

This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-ORed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated).

2.3Chip Enable (E0, E1, E2)

These input signals are used to set the value that is to be looked for on the least significant bits of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the device select code as shown in Figure 4. When not connected (left floating), Ei inputs are read as low (0).

Figure 4. Device select code

VCC

VCC

M24Cxx M24Cxx

Ei							Ei
VSS							VSS

Ai11650

2.3.1Write Control (WC)

This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed.

When Write Control (WC) is driven High, device select and address bytes are acknowledged, data bytes are not acknowledged.

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M24C16, M24C08, M24C04, M24C02, M24C01	Signal description

2.4Supply voltage (VCC)

2.4.1Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 6, Table 7 and Table 8). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).

2.4.2Power-up conditions

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 6, Table 7 and Table 8 and the rise time must not vary faster than 1 V/µs.

2.4.3Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any instruction until VCC reaches the power-on-reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 6, Table 7 and Table 8). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode. The device, however, must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range.

In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it.

2.4.4Power-down conditions

During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).

Figure 5. Maximum RP value versus bus parasitic capacitance (C) for an I²C bus

resistor	100
						When tLOW = 1.3 µs (min value for
p						fC = 400 kHz), the Rbus × Cbus		VCC
upll-u (k )						time constant must be below the
						represented on the left.
		R				400 ns time constant line
	10
		bus
line		×	C					Rbus
	Here Rbus × Cbus	= 120 ns	bus =	400
Bus	4 kΩ				n
					s	I²C bus	SCL
								M24xxx
						master
	1						SDA
	30 pF							Cbus
	10		100			1000
		Bus line capacitor (pF)

ai14796b

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Signal description	M24C16, M24C08, M24C04, M24C02, M24C01

Figure 6. I²C bus protocol

SCL
SDA
	Start		SDA	SDA		Stop
			Input	Change
	condition					condition
SCL	1	2	3	7	8	9
SDA	MSB					ACK
	Start
	condition
SCL	1	2	3	7	8	9
SDA	MSB					ACK
						Stop
						condition
						AI00792c

Table 3.

Device select code

Device type identifier(1)

Chip Enable(2),(3)

RW

b7

b6

b5

b4

b3

b2

b1

b0

M24C01 select code

1

0

1

0

E2

E1

E0

RW

M24C02 select code

1

0

1

0

E2

E1

E0

RW

M24C04 select code

1

0

1

0

E2

E1

A8

RW

M24C08 select code

1

0

1

0

E2

A9

A8

RW

M24C16 select code

1

0

1

0

A10

A9

A8

RW

1.The most significant bit, b7, is sent first.

2.E0, E1 and E2 are compared against the respective external pins on the memory device.

3.A10, A9 and A8 represent most significant bits of the address.

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M24C16, M24C08, M24C04, M24C02, M24C01	Device operation

3 Device operation

The device supports the I²C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communication.

3.1Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition.

3.2Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal Write cycle.

3.3Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.

3.4Data input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low.

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Device operation	M24C16, M24C08, M24C04, M24C02, M24C01

3.5Memory addressing

To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 3 (on Serial Data (SDA), most significant bit first).

The device select code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b.

Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. However, those devices with larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0 is not available for use on devices that need to use address line A8; E1 is not available for devices that need to use address line A9, and E2 is not available for devices that need to use address line A10 (see Figure 2 and Table 3 for details). Using the E0, E1 and E2 inputs, up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can be connected to one I²C bus. In each case, and in the hybrid cases, this gives a total memory capacity of 16 Kbits, 2 KBytes (except where M24C01 devices are used).

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode.

Table 4.

Operating modes

Mode

bit

(1)

Bytes

Initial sequence

RW

WC

Current Address Read

1

X

1

= 1

Start, Device Select, RW

0

X

= 0, Address

Random Address Read

1

Start, Device Select, RW

1

X

= 1

reStart, Device Select, RW

Sequential Read

1

X

≥ 1

Similar to Current or Random Address

Read

Byte Write

0

VIL

1

= 0

Start, Device Select, RW

Page Write

0

VIL

≤ 16

= 0

Start, Device Select, RW

1. X = VIH or VIL.

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