ST STM32L151CB, STM32L151C8, STM32L151C6, STM32L151RB, STM32L151R8 User Manual

STM32L151xx

STM32L152xx

Ultralow power ARM-based 32-bit MCU with up to 128 KB Flash, RTC, LCD, USB, USART, I2C, SPI, timers, ADC, DAC, comparators

Features

■Operating conditions

–Operating power supply range: 1.65 V to

3.6V (without BOR) or 1.8 V to 3.6 V (with BOR option)

–Temperature range: –40 to 85 °C

■Low power features

–4 modes: Sleep, Low-power run (9 µA at 32 kHz), Low-power sleep (4.4 µA), Stop with RTC (1.45 µA), Stop (570 nA), Standby (300 nA)

–Dynamic core voltage scaling down to 233 µA/MHz

–Ultralow leakage per I/O: 50 nA

–Fast wakeup from Stop: 8 µs

–Three wakeup pins

■Core: ARM 32-bit Cortex™-M3 CPU

–32 MHz maximum frequency,

33.3DMIPS peak (Dhrystone 2.1)

–Memory protection unit

■Reset and supply management

–Low power, ultrasafe BOR (brownout reset) with 5 selectable thresholds

–Ultralow power POR/PDR

–Programmable voltage detector (PVD)

■Clock management

–1 to 24 MHz crystal oscillator

–32 kHz oscillator for RTC with calibration

–Internal 16 MHz factory-trimmed RC

–Internal 37 kHz low consumption RC

–Internal multispeed low power RC, 65 kHz to 4.2 MHz with consumption down to

1.5µA

–PLL for CPU clock and USB (48 MHz)

■Low power calendar RTC

–Alarm, periodic wakeup from Stop/Standby

■Memories

–Up to 128 Kbyte of Flash memory with ECC

–4 Kbyte of data EEPROM with ECC

LQFP100 14 × 14 mm		BGA100 7 × 7 mm					UFQFPN48
LQFP64 10	× 10 mm	BGA64 5 × 5 mm					7 × 7 mm
LQFP48 7	× 7 mm

–Up to 16 Kbyte of RAM

■Up to 83 fast I/Os (73 of which are 5 V-tolerant) all mappable on 16 external interrupt vectors

■Development support

–Serial wire debug, JTAG and trace

■DMA: 7-channel DMA controller, supporting timers, ADC, SPIs, I2Cs and USARTs

■LCD 8 × 40 or 4 × 44 with step-up converter

■12-bit ADC up to 1 Msps/24 channels

–Temperature sensor and internal voltage reference

–Operates down to 1.8 V

■2 × 12-bit DACs with output buffers

■2 ultralow power comparators

–Window mode and wakeup capability

■10 timers:

–6 × 16-bit general-purpose timers, each with up to 4 IC/OC/PWM channels

–2 × 16-bit basic timers

–2 × watchdog timers (independent and window)

■Up to 8 communication interfaces

–Up to 2 × I2C interfaces (SMBus/PMBus)

–Up to 3 × USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)

–Up to 2 × SPIs (16 Mbit/s)

–USB 2.0 full speed interface

■CRC calculation unit, 96-bit unique ID

Table 1. Device summary

Reference

Part number

STM32L151CB, STM32L151C8, STM32L151C6, STM32L151xx STM32L151RB, STM32L151R8, STM32L151R6,

STM32L151VB, STM32L151V8

STM32L152CB, STM32L152C8, STM32L152C6, STM32L152xx STM32L152RB, STM32L152R8, STM32L152R6,

STM32L152VB, STM32L152V8

January 2012

Doc ID 17659 Rev 6

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Contents	STM32L151xx, STM32L152xx

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 9
	2.1	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.2	Ultralow power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11

2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3	Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	3.1	Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.2	ARM® Cortex™-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	3.3	Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15

3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4	Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
3.5	Low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . .		18
3.6	GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . .		18
3.7	Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
3.8	DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
3.9	LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
3.10	ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
3.11	DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
3.12	Ultralow power comparators and reference voltage . . . . . . . . . . . . . . . . .		21
3.13	Routing interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
3.14	Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	3.14.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11)		22
	3.14.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
	3.14.3	SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	3.14.4	Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22

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3.14.5	Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 23
3.15 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 23
3.15.1	I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 23

3.15.2Universal synchronous/asynchronous receiver transmitter (USART) . . 23

3.15.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.4 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

	3.16	CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . .	24
	3.17	Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
4	Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
5	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		40
6	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
	6.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
6.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		44
	6.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
	6.3.2	Embedded reset and power control block characteristics . . . . . . . . . . .	46
	6.3.3	Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . .	48
	6.3.4	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
	6.3.5	External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	59
	6.3.6	Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
	6.3.7	PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
	6.3.8	Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
	6.3.9	EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
	6.3.10	Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . .	71
	6.3.11	I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
	6.3.12	I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	73
	6.3.13	NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	76

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6.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.19 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.20 LCD controller (STM32L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 96
	7.1	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		96
	7.2	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		104
		7.2.1	Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	104
8	Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			105
9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			106

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STM32L151xx, STM32L152xx	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Ultralow power STM32L15xxx device features and peripheral counts . . . . . . . . . . . . . . . . 10 Table 3. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 4. STM32L15xxx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5. Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 6. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 7. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 8. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 9. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 10. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 45 Table 11. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 12. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 13. Current consumption in Run mode, code with data processing running from Flash. . . . . . 49 Table 14. Current consumption in Run mode, code with data processing running from RAM . . . . . . 50 Table 15. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 16. Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 17. Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 18. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 19. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 55 Table 20. Typical and maximum timings in Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 21. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 22. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 23. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 24. HSE 1-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 25. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 26. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 27. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 28. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 29. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 30. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 31. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 32. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 33. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 34. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 36. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 37. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 38. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 39. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 40. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 41. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 42. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 43. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 44. SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 45. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 46. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 47. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 48. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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Table 49. ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 50. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 51. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 52. RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 53. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 54. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 55. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 56. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 57. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 58. UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm, 0.5 mm

pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 59. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 98 Table 60. UFBGA100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 61. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 101 Table 62. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 102 Table 63. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 103 Table 64. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 65. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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STM32L151xx, STM32L152xx	List of figures

List of figures

Figure 1.	Ultralow power STM32L15xxx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 12
Figure 2.	Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 17
Figure 3.	STM32L15xxx UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 25
Figure 4.	STM32L15xxx TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 5.	STM32L15xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 6.	STM32L15xxx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 7.	STM32L15xxx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 8.	STM32L15xxx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Figure 9.	Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 10.	Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
Figure 11.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
Figure 12.	Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
Figure 13.	Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
Figure 14.	Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
Figure 15.	High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
Figure 16.	HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	63
Figure 17.	Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	64
Figure 18.	I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	76
Figure 19.	Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
Figure 20.	I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
Figure 21.	SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
Figure 22.	SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
Figure 23.	SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82
Figure 24.	USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
Figure 25.	ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	87
Figure 26.	Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	87
Figure 27.	Maximum dynamic current consumption on VREF+ supply pin during ADC
	conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	88
Figure 28.	Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . .	89
Figure 29.	Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . .	89
Figure 30.	12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	92
Figure 31.	UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
Figure 32.	Recommended footprint (dimensions in mm)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
Figure 33.	TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . .	98
Figure 34.	Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . .	99
Figure 35.	UFBGA100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch,
	package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	100
Figure 36.	LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . .	101
Figure 37.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	101
Figure 38.	LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . .	102
Figure 39.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	102
Figure 40.	LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . .	103
Figure 41.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	103

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Introduction	STM32L151xx, STM32L152xx

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32L151xx and STM32L152xx ultralow power ARM Cortex™-based microcontrollers product line.

The ultralow power STM32L15xxx family includes devices in 3 different package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

These features make the ultralow power STM32L15xxx microcontroller family suitable for a wide range of applications:

●Medical and handheld equipment

●Application control and user interface

●PC peripherals, gaming, GPS and sport equipment

●Alarm systems, Wired and wireless sensors, Video intercom

●Utility metering

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337g.

Figure 1 shows the general block diagram of the device family.

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2 Description

The ultralow power STM32L15xxx incorporates the connectivity power of the universal serial bus (USB) with the high-performance ARM Cortex™-M3 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (Flash memory up to 128 Kbytes and RAM up to 16 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer a 12-bit ADC, 2 DACs and 2 ultralow power comparators, six general-purpose 16-bit timers and two basic timers, which can be used as time bases. Moreover, the STM32L15xxx devices contain standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs and a USB. They also include a real-time clock and a set of backup registers that remain powered in Standby mode. Finally, the integrated LCD controller has a built-in LCD voltage generator that allows you to drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.

The ultralow power STM32L15xxx operates from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. It is available in the -40 to +85 °C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications.

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Description	STM32L151xx, STM32L152xx

2.1Device overview

Table 2. Ultralow power STM32L15xxx device features and peripheral counts

Peripheral		STM32L15xCx						STM32L15xRx				STM32L15xVx
Flash - Kbytes		32		64		128	32		64		128	64		128
RAM - Kbytes		10		10		16	10		10		16	10		16
	General-		6					6					6
Timers	purpose
	Basic		2					2					2
	SPI		2					2					2
Communication	I2C		2					2					2
interfaces	USART		3					3					3
	USB		1					1					1
GPIOs			37					51					83
12-bit synchronized ADC			1					1					1
Number of channels			16 channels					20 channels				24 channels
12-bit DAC			2					2					2
Number of channels			2					2					2
LCD (STM32L152xx Only)				4x16					4x32				4x44
COM x SEG									8x28				8x40
Comparator			2					2					2
CPU frequency									32 MHz
					1.8 V to 3.6 V (down to 1.65 V at power-down)
Operating voltage							with BOR option
						1.65 V to 3.6 V without BOR option
Operating temperatures		Ambient temperatures: –40 to +85 °C
		Junction temperature: –40 to + 105 °C
Packages		LQFP48, UFQFPN48					LQFP64, BGA64					LQFP100, BGA100

.

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2.2Ultralow power device continuum

	The ultralow power STM32L151xx and STM32L152xx are fully pin-to-pin, software and
	feature compatible. Besides the full compatibility within the family, the devices are part of
	STMicroelectronics microcontrollers ultralow power strategy which also includes
	STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a
	continuum of performance, peripherals, system architecture and features.
	They are all based on STMicroelectronics 0.13 µm ultralow leakage process.
Note:	The ultralow power STM32L and general-purpose STM32Fxxxx families are pin-to-pin
	compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx
	devices. Please refer to the STM32F and STM8L documentation for more information on
	these devices.

2.2.1	Performance
	All families incorporate highly energy-efficient cores with both Harvard architecture and
	pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
	for STM32L family. In addition specific care for the design architecture has been taken to
	optimize the mA/DMIPS and mA/MHz ratios.
	This allows the ultralow power performance to range from 5 up to 33.3 DMIPs.

2.2.2 Shared peripherals

STM8L15xxx and STM32L15xxx share identical peripherals which ensure a very easy migration from one family to another:

●Analog peripherals: ADC, DAC, and comparators

●Digital peripherals: RTC and some communication interfaces

2.2.3Common system strategy

To offer flexibility and optimize performance, the STM8L15xx and STM32L15xx families use a common architecture:

●Same power supply range from 1.65 V to 3.6 V, (1.65 V at power down only for STM8L15xx devices)

●Architecture optimized to reach ultralow consumption both in low power modes and Run mode

●Fast startup strategy from low power modes

●Flexible system clock

●Ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector.

2.2.4Features

ST ultralow power continuum also lies in feature compatibility:

●More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm

●Memory density ranging from 4 to 128 Kbytes

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Functional overview	STM32L151xx, STM32L152xx

3 Functional overview

Figure 1 shows the block diagrams.

Figure 1. Ultralow power STM32L15xxx block diagram

				42!#%#+ #42!#%$
				42!#%$ $42!#%$
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									6$$
	*4!' 37		PBUS	4RACECCONTROLLER			6#/2%		0/7%2	6$$ 6 TO 6
					%4-				6/,4 2%'
.*4234	#ORTEX - #05									633
					&LASH OBL )NTERFACE
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*4#+ 37#+						+" &LASH
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*4-3 37$			$BUS			+" DATA %%02/-
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					+"
							6$$!
	'0 $-!
					!("0#,+		0,,		84!, /3#	/3#?).
										/3#?/54
	CHANNELS				!0"0#,+
					(#,+		CLOCK		-(Z
	6$$!						MANAGEMENT
					,+
.234	3UPPLY					2# (3
	MONITORINGN
			0OWER RESET			2# -3
62%& /54054	"/2 62%&).4								)7$'
						2# ,3
6$$!	06$		)NT	-(Z		6$$!			3TANDBYYINTERFACE
633!										/3# ?).
	#OMP								84!, K(Z
										/3# ?/54
#/-0 ?). ).	#OMP								24#	3YNC (Z
	0OWER UP			MAX
									!75	24#?!&
	0OWER DOWN			&!("				"ACKUPU
								REGISTER
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									"ACKUPUINTERFACE
0"; =	'0)/"						,#$
0#; =	'0)/#								,#$#STEP UP	6,#$# 6 T OO 6
							6		CONVERTER
0$; =	'0)/$								4)-	#HANNELS
0%; =	'0)/%								4)-	#HANNELS
0(; =	'0)/(								4)-	#HANNELS
				!("	!("				53!24	28 48 #43 243
										3MART#ARD AS !&
				!0"	!0"
!&	%84 )4								53!24	28 48 #43 243
	7+50									3MART#ARD AS !&
							-(Z
-/3) -)3/									30)	-/3) -)3/ 3#+ .33
	30)
3#+ .33 AS !&
										AS !&
28 48 #43 243	53!24						MAX		) #	3#, 3$!
3MART#ARD AS !&							&
			-(Z							AS !&
							!0"
!&	6$$!								) #	3#, 3$! 3-"US 0-"US
										AS !&
	BIT !$#	)&
6$$2%&?!$#
			MAX	53""2!- "				53"3 &3 DEVICE		53"$0
6332%&?!$#										53"$-
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	4EMP SENSOR		!0"	77$'
										3%'X
								,#$ X X
										#/-X
	'ENERAL PURPOSE
	TIMERS			"!3)##4)-%23					6$$!
#HANNELS
	4)-
				4)-					BIT $!#	$!# AS !&
#HANNEL	4)-							))&
				4)-					BIT $!#	$!# AS !&
#HANNEL	4)-
										AI E

1. AF = alternate function on I/O port pin.

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STM32L151xx, STM32L152xx	Functional overview

3.1Low power modes

The ultralow power STM32L15xxx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply:

●In range 1 (VDD range limited to 2.0-3.6 V), the CPU runs at up to 32 MHz (refer to Table 13 for consumption).

●In range 2 (full VDD range), the CPU runs at up to 16 MHz (refer to Table 13 for consumption)

●In range 3 (full VDD range), the CPU runs at up to 4 MHz (generated only with the multispeed internal RC oscillator clock source). Refer to Table 13 for consumption.

Seven low power modes are provided to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

Sleep mode power consumption: refer to Table 15.

●Low power run mode

This mode is achieved with the multispeed internal (MSI) RC oscillator set to the minimum clock (65 kHz), execution from SRAM or Flash memory, and internal regulator in low power mode to minimize the regulator's operating current. In the Low power run mode, the clock frequency and the number of enabled peripherals are both limited.

Low power run mode consumption: refer to Table 16.

●Low power sleep mode

This mode is achieved by entering the Sleep mode with the internal voltage regulator in Low power mode to minimize the regulator’s operating current. In the Low power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz.

When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on.

Low power sleep mode consumption: refer to Table 17.

●Stop mode (with or without RTC)

The Stop mode achieves the lowest power consumption while retaining the RAM and

register contents. All clocks in the VCORE domain are stopped, the PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The voltage regulator is in the low power mode.

The device can be woken up from the Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm(s), the USB wakeup, the RTC tamper event, the RTC timestamp event, the RTC Wakeup, the Comparator 1 event or Comparator 2 event.

Stop mode consumption: refer to Table 18.

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Functional overview		STM32L151xx, STM32L152xx
	● Standby mode (with or without RTC)
	The Standby mode is used to achieve the lowest power consumption. The internal
	voltage regulator is switched off so that the entire VCORE domain is powered off. The
	PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. After entering
	Standby mode, the RAM and register contents are lost except for registers in the
	Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC CSR).
	The device exits the Standby mode in 60 µs when an external reset (NRST pin), an
	IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or
	Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event.
	Standby mode consumption: refer to Table 19.
Note:	The RTC, the IWDG, and the corresponding clock sources are not stopped by entering the
	Stop or Standby mode.

3.2 ARM® Cortex™-M3 core with MPU

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region.

Owing to its embedded ARM core, the STM32L15xxx is compatible with all ARM tools and software.

Nested vectored interrupt controller (NVIC)

The ultralow power STM32L15xxx embeds a nested vectored interrupt controller able to handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

●Closely coupled NVIC gives low-latency interrupt processing

●Interrupt entry vector table address passed directly to the core

●Closely coupled NVIC core interface

●Allows early processing of interrupts

●Processing of late arriving, higher-priority interrupts

●Support for tail-chaining

●Processor state automatically saved

●Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

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3.3Reset and supply management

3.3.1Power supply schemes

●VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins.

●VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively.

3.3.2Power supply supervisor

	The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
	(PDR) that can be coupled with a brownout reset (BOR) circuitry.
	For devices operating between 1.8 and 3.6 V, the BOR is always active at power-on and
	ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the
	option byte loading process starts, either to confirm or modify default thresholds, or to
	disable BOR permanently (in which case, the VDD min value at power down is 1.65 V). Five
	BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the
	power consumption in Stop mode, it is possible to automatically switch off the internal
	reference voltage (VREFINT) in Stop mode. The device remains in reset mode when VDD is
	below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset
	circuit.
Note:	For devices operating between 1.65 V and 3.6 V, the BOR is permanently disabled.
	Consequently, the start-up time at power-on can be decreased down to 1ms typically.
	The device features an embedded programmable voltage detector (PVD) that monitors the
	VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
	levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
	interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
	VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
	a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in Run mode (nominal regulation)

● LPR is used in the Low-power run, Low-power sleep and Stop modes

● Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost are lost except for the standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR).

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3.3.4Boot modes

At startup, boot pins are used to select one of three boot options:

●Boot from Flash memory

●Boot from System Memory

●Boot from embedded RAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1 or USART2. For further details please refer to AN2606.

3.4Clock management

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. It features:

●Clock prescaler: to get the best tradeoff between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

●Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.

●Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

●Master clock source: three different clock sources can be used to drive the master clock:

–1-24 MHz high-speed external crystal (HSE), that can supply a PLL

–16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL

–Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz) with a consumption proportional to speed, down to 750 nA typical. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a ±0.5% accuracy.

●Auxiliary clock source: two ultralow power clock sources that can be used to drive the LCD controller and the real-time clock:

–32.768 kHz low-speed external crystal (LSE)

–37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision.

●RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock.

●USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface.

●Startup clock: after reset, the microcontroller restarts by default with an internal 2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

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●Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled.

●Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See Figure 2 for details on the clock tree.

Figure 2.	Clock tree
	-3) 2#	-3)
				!$##,+	TO !$#
		0ERIPHERAL CLOCK
	-(Z	ENABLE
		(3)
	(3) 2#
				-(Z
			0,,6#/	53"#,+
		0,,32# 0,,-5,		TO 53" INTERFACE		37
			0,,$)6
		X X X X				(3)	393#,+	-(Z MAX
		X X X
/3#?/54					0,,#,+
	-(Z	X X
/3#?).	(3%%/3#					(3%
						#33
				-(Z MAX		(#,+
						TO !(" BUS CORE
				#LOCK		MEMORY AND $-!
				%NABLE		TO #ORTEXX3YSTEM TIMER
						,+ #ORTEX

FREE RUNNING CLOCK

!("

!0"

-(ZZMAX

0#,+

0RESCALER

0RESCALER

TO !0"

0ERIPHERAL

#LOCK PERIPHERALS

%NABLE

)F !0" PRESCALER X

TO 4)- AND

ELSE SX

4)-X#,+

0ERIPHERAL #LOCK

%NABLE

!0"

-(ZZMAX

0#,+

0RESCALER

PERIPHERALSLTO !0"

0ERIPHERAL

#LOCK

%NABLE

)F !0" PRESCALER X

TO 4)- AND

ELSE X

4)-X#,+

		TO	0ERIPHERAL #LOCK
			%NABLE
		4IMERM %42
/3# ?).	,3%	TO 24#
,3% /3#		24##,+
K(Z
/3# ?/54		TO ,#$
		24#3%,; ==

,3) 2#	,3)	TO )NDEPENDENT 7ATCHDOGG )7$'
K(Z		)7$'#,+

,EGEND

										393#,+
												(3)
-#//												-3)
												(3%
											0,,#,+
												,3)
												,3%
						-		#/3%,%

(3% (IGH SPEED EXTERNAL CLOCK SIGNAL

(3) (IGH SPEED INTERNAL CLOCKKSIGNAL ,3) ,OW SPEED INTERNAL CLOCKKSIGNAL ,3%% ,OWWSPEED EXTERNAL CLOCK SIGNAL -3) -ULTISPEEDLINTERNALACLOCKKSIGNAL

AI C

2.For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 24 MHz or 32 MHz.

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Functional overview	STM32L151xx, STM32L152xx

3.5Low power real-time clock and backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes.

●The programmable wakeup time ranges from 120 µs to 36 hours

●Stop mode consumption with LSI and Auto-wakeup: 1.2 µA (at 1.8 V) and 1.4 µA (at 3.0 V)

●Stop mode consumption with LSE, calendar and Auto-wakeup: 1.3 µA (at 1.8V), 1.6 µA (at 3.0 V)

The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation.

There are twenty 32-bit backup registers provided to store 80 bytes of user application data. They are cleared in case of tamper detection.

3.6GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high-current-capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected to the 16 external interrupt lines.

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3.7Memories

The STM32L15xxx devices have the following features:

●Up to 16 Kbyte of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses).

●The non-volatile memory is divided into three arrays:

–32, 64 or 128 Kbyte of embedded Flash program memory

–4 Kbyte of data EEPROM

–Options bytes

The options bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options:

–Level 0: no readout protection

–Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected

–Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse)

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.8DMA (direct memory access)

The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers and ADC.

3.9LCD (liquid crystal display)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels.

●Internal step-up converter to guarantee functionality and contrast control irrespective of

VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD

●Supports static, 1/2, 1/3, 1/4 and 1/8 duty

●Supports static, 1/2, 1/3 and 1/4 bias

●Phase inversion to reduce power consumption and EMI

●Up to 8 pixels can be programmed to blink

●Unneeded segments and common pins can be used as general I/O pins

●LCD RAM can be updated at any time owing to a double-buffer

●The LCD controller can operate in Stop mode

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3.10ADC (analog-to-digital converter)

A 12-bit analog-to-digital converters is embedded into STM32L15xxx devices with up to 24 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, to allow the application to synchronize A/D conversions and timers.

The ADC includes a specific low power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC’s runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode.

Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel.

3.11DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration.

This dual digital Interface supports the following features:

●two DAC converters: one for each output channel

●left or right data alignment in 12-bit mode

●synchronized update capability

●noise-wave generation

●triangular-wave generation

●dual DAC channels’ independent or simultaneous conversions

●DMA capability for each channel (including the underrun interrupt)

●external triggers for conversion

●input reference voltage VREF+

Eight DAC trigger inputs are used in the STM32L15xxx. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

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3.12Ultralow power comparators and reference voltage

The STM32L15xxx embeds two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O).

●one comparator with fixed threshold

●one comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following:

–DAC output

–External I/O

–Internal reference voltage (VREFINT) or VREFINT submultiple (1/4, 1/2, 3/4)

Both comparators can wake up from Stop mode, and be combined into a window comparator.

The internal reference voltage is available externally via a low power / low current output buffer (driving current capability of 1 µA typical).

3.13Routing interface

This interface controls the internal routing of I/Os to TIM2, TIM3, TIM4 and to the comparator and reference voltage output.

3.14Timers and watchdogs

The ultralow power STM32L15xxx devices include six general-purpose timers, two basic timers and two watchdog timers.

Table 3 compares the features of the general-purpose and basic timers.

Table 3.		Timer feature comparison
Timer		Counter	Counter	Prescaler	DMA request	Capture/compare	Complementary
		resolution	type	factor	generation	channels	outputs
TIM2,			Up,	Any integer
TIM3,		16-bit	down,	between 1	Yes	4	No
TIM4			up/down	and 65536
				Any integer
TIM9		16-bit	Up	between 1	No	2	No
				and 65536
TIM10,				Any integer
		16-bit	Up	between 1	No	1	No
TIM11
				and 65536
TIM6,				Any integer
		16-bit	Up	between 1	Yes	0	No
TIM7
				and 65536

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Functional overview	STM32L151xx, STM32L152xx

3.14.1General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11)

There are six synchronizable general-purpose timers embedded in the STM32L15xxx devices (see Table 3 for differences).

TIM2, TIM3, TIM4

These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.

The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM10, TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4 all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

TIM10, TIM11 and TIM9

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4 full-featured general-purpose timers.

They can also be used as simple time bases and be clocked by the LSE clock source (32.768 kHz) to provide time bases independent from the main CPU clock.

3.14.2Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit time bases.

3.14.3SysTick timer

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0.

3.14.4Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardwareor software-configurable through the option bytes. The counter can be frozen in debug mode.

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3.14.5Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.15Communication interfaces

3.15.1I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

3.15.2Universal synchronous/asynchronous receiver transmitter (USART)

All USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They provide hardware management of the CTS and RTS signals. They support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability.

All USART interfaces can be served by the DMA controller.

3.15.3Serial peripheral interface (SPI)

Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

Both SPIs can be served by the DMA controller.

3.15.4Universal serial bus (USB)

The STM32L15xxx embeds a USB device peripheral compatible with the USB full speed 12 Mbit/s. The USB interface implements a full speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated

48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

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Functional overview	STM32L151xx, STM32L152xx

3.16CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.17Development support

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

The JTAG port can be permanently disabled with a JTAG fuse.

Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L15xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

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STM32L151xx, STM32L152xx	Pin descriptions

4 Pin descriptions

Figure 3.

STM32L15xxx UFBGA100 ballout

1

2

3

4

5

6

7

8

9

10

11

12

A

PE3

PE1

PB8

BOOT0

PD7

PD5

PB4

PB3

PA15

PA14

PA13

PA12

B

PE4

PE2

PB9

PB7

PB6

PD6

PD4

PD3

PD1

PC12

PC10

PA11

C

PC13

PE5

PE0

VDD_3

PB5

PD2

PD0

PC11

PH2

PA10

RTC_AF1

D

WKUP2

PC14

PE6

VSS_3

PA9

PA8

PC9

OSC32_IN

WUKP3

E

PC15

VLCD

VSS_4

PC8

PC7

PC6

OSC32_OUT

F

PH0

VSS_5

VSS_2

VSS_1

OSC_IN

G

PH1

VDD_2

VDD_1

OSC_OUTVDD_5

H

PC0

NRST VDD_4

PD15

PD14

PD13

J

VSSA

PC1

PC2

PD12

PD11

PD10

K

VREF-

PC3

PA2

PA5

PC4

PD9

PD8

PB15

PB14

PB13

L

VREF+

PA0

PA3

PA6

PC5

PB2

PE8

PE10

PE12

PB10

PB11

PB12

WKUP1

M

VDDA

PA1

PA4

PA7

PB0

PB1

PE7

PE9

PE11

PE13

PE14

PE15

ai17096d

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	Pin descriptions							STM32L151xx, STM32L152xx
	Figure 4. STM32L15xxx TFBGA64 ballout
		1		2	3	4	5	6	7	8
	A	PC14-		PC13-	PB9	PB4	PB3	PA15	PA14	PA13
		OSC32_IN
				RTC_AF1 -
				WKUP2
	B	PC15-		VLCD	PB8	BOOT0	PD2	PC11	PC10	PA12
		OSC32_OUT
		PH0-
	C	OSC_IN		VSS_4	PB7	PB5	PC12	PA10	PA9	PA11
		PH1-		VDD_4		VSS_3	VSS_2	VSS_1		PC9
	D	OSC_OUT			PB6				PA8
	E	NRST		PC1	PC0	VDD_3	VDD_2	VDD_1	PC7	PC8
	F	VSSA		PC2	PA2	PA5	PB0	PC6	PB15	PB14
	G	VREF+	PA0-WKUP1		PA3	PA6	PB1	PB2	PB10	PB13
	H	VDDA		PA1	PA4	PA7	PC4	PC5	PB11	PB12
										AI16090b

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STM32L151xx, STM32L152xx																									Pin descriptions
	Figure 5. STM32L15xxx LQFP100 pinout
		VDD 3	VSS 3	PE1	PE0	PB9	PB8	BOOT0	PB7	PB6	PB5	PB4	PB3	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0	PC12	PC11	PC10	PA15	PA14
	PE2	100	99	98	97	96	95	94	93	92	91	90	89	88	87	86	85	84	83	82	81	80	79	78	77	76
		1																								75	VDD_2
	PE3	2																								74	VSS_2
	PE4	3																								73	PH2
	PE5	4																								72	PA 13
	PE6-WKUP3	5																								71	PA 12
	VLCD	6																								70	PA 11
	PC13-RTC_AF1-WKUP2	7																								69	PA 10
	PC14-OSC32_IN	8																								68	PA 9
	PC15-OSC32_OUT	9																								67	PA 8
	VSS_5	10																								66	PC9
	VDD_5	11																								65	PC8
	PH0-OSC_IN	12										LQFP100														64	PC7
	PH1-OSC_OUT	13																								63	PC6
	NRST	14																								62	PD15
	PC0	15																								61	PD14
	PC1	16																								60	PD13
	PC2	17																								59	PD12
	PC3	18																								58	PD11
	VSSA	19																								57	PD10
	VREF-	20																								56	PD9
	VREF+	21																								55	PD8
	VDDA	22																								54	PB15
	PA0-WKUP1	23																								53	PB14
	PA1	24																								52	PB13
	PA2	25																								51	PB12
		26	27	28	29	30	31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50
		PA3	VSS 4	VDD 4	PA4	PA5	PA6	PA7	PC4	PC5	PB0	PB1	PB2	PE7	PE8	PE9	PE10	PE11	PE12	PE13	PE14	PE15	PB10	PB11	VSS 1	VDD 1
																											ai15692b

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Pin descriptions

STM32L151xx, STM32L152xx

Figure 6. STM32L15xxx LQFP64 pinout

VDD 3

VSS 3 PB9 PB8 BOOT0 PB7

PB6 PB5 PB4 PB3 PD2

PC12

PC11

PC10

PA15

PA14

VLCD

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VDD_2

1

48

PC13-RTC_AF1-WKUP2

2

47

VSS_2

PC14-OSC32_IN

3

46

PA13

PC15-OSC32_OUT

4

45

PA12

PH0 -OSC_IN

5

44

PA11

PH1-OSC_OUT

6

43

PA10

NRST

7

42

PA9

PC0

8

LQFP64

41

PA8

PC1

9

40

PC9

PC2

10

39

PC8

PC3

11

38

PC7

VSSA

12

37

PC6

VDDA

13

36

PB15

PA0-WKUP1

14

35

PB14

PA1

15

34

PB13

PA2

16

33

PB12

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PA3

VSS 4 VDD 4 PA4 PA5 PA6 PA7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

VSS 1

VDD 1

ai15693b

Figure 7. STM32L15xxx LQFP48 pinout

VDD 3 VSS 3 PB9 PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PA15

PA14

VLCD

48 47 46 45

44 43 42 41 40 39 38 37

VDD_2

1

36

PC13- RTC_AF1-WKUP2

2

35

VSS_2

PC14-OSC32_IN

3

34

PA13

PC15-OSC32_OUT

4

33

PA12

PH0-OSC_IN

5

32

PA11

PH1-OSC_OUT

6

LQFP48

31

PA10

NRST

7

30

PA9

VSSA

8

29

PA8

VDDA

9

28

PB15

PA0-WKUP1

10

27

PB14

PA1

11

26

PB13

PA2

12

25

PB12

13 14 15 16 17 18 19 20 21 22 23 24

PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS 1 VDD 1

ai15694b

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Pin descriptions

Figure 8. STM32L15xxx UFQFPN48 pinout

0!

0!

6

6

0""

0""

"//4

0"

0"

0"

0"

0"

$$?

33?

6,#$

6$$?

0# 24#?!&

633?

0# /3# ?).

0!

0# /3# ?/54

0!

0( /3#?).

0!

0( /3#?/54

5&1&0.

0!

.234

0!

633!

0!

6$$!

0"

0! 7+50

0"

0!

0"

0!

0"

0!

0!

0!

0!

0!

0"

0"

0"

0"

0"

33?

$$?

6

6

AI C

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Pin descriptions									STM32L151xx, STM32L152xx
Table 4.			STM32L15xxx pin definitions
		Pins
							I/OLevel
LQFP100	LQFP64	TFBGA64	UFBGA100	orLQFP48UFQFPN48		Type
					Pin name	(1)	(2)	Main	Alternate functions
								function(3)
								(after reset)
1	-		B2	-	PE2	I/O	FT	PE2	TRACECK/LCD_SEG38/TIM3_ETR
2	-		A1	-	PE3	I/O	FT	PE3	TRACED0/LCD_SEG39/TIM3_CH1
3	-		B1	-	PE4	I/O	FT	PE4	TRACED1/TIM3_CH2
4	-		C2	-	PE5	I/O	FT	PE5	TRACED2/TIM9_CH1
5	-		D2	-	PE6	I/O	FT	PE6	TRACED3/WKUP3/TIM9_CH2
6	1	B2	E2	1	(4)	S		VLCD
					VLCD
7	2	A2	C1	2	PC13-	I/O	FT	PC13	RTC_AF1/WKUP2
					RTC_AF1
8	3	A1	D1	3	PC14-	I/O		PC14	OSC32_IN
					OSC32_IN(5)
					PC15-
9	4	B1	E1	4	OSC32_OUT	I/O		PC15	OSC32_OUT
					(5)
10	-	-	F2	-	VSS_5	S		VSS_5
11	-	-	G2	-	VDD_5	S		VDD_5
12	5	C1	F1	5	PH0-	I		PH0	OSC_IN
					OSC_IN(6)
13	6	D1	G1	6	PH1-	O		PH1	OSC_OUT
					OSC_OUT
14	7	E1	H2	7	NRST	I/O		NRST
15	8	E3	H1	-	PC0	I/O	FT	PC0	ADC_IN10/LCD_SEG18/ COMP1_INP
16	9	E2	J2	-	PC1	I/O	FT	PC1	ADC_IN11/LCD_SEG19/ COMP1_INP
17	10	F2	J3	-	PC2	I/O	FT	PC2	ADC_IN12/LCD_SEG20/ COMP1_INP
18	11	-(7)	K2	-	PC3	I/O		PC3	ADC_IN13/LCD_SEG21/ COMP1_INP
19	12	F1	J1	8	VSSA	S		VSSA
20	-	-	K1	-	VREF-	S		VREF-
21	-	G1(7)	L1	-	VREF+	S		VREF+
22	13	H1	M1	9	VDDA	S		VDDA
23	14	G2	L2	10	PA0-WKUP1	I/O	FT	PA0	WKUP1/USART2_CTS/ADC_IN0/TIM2_CH1_ETR/
									COMP1_INP

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Doc ID 17659 Rev 6