ST STM32F101C6, STM32F101R6, STM32F101C8, STM32F101R8, STM32F101V8 User Manual

STM32F101x6 www.DataSheet4U.com

STM32F101x6

STM32F101x8 STM32F101xB

Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces

Preliminary Data

Features

■Core: ARM 32-bit Cortex™-M3 CPU

–36 MHz, 45 DMIPS with 1.25 DMIPS/MHz

–Single-cycle multiplication and hardware division

–Nested interrupt controller with 43 maskable interrupt channels

–Interrupt processing (down to 6 CPU cycles) with tail chaining

■Memories

–32-to-128 Kbytes of Flash memory

–6-to-16 Kbytes of SRAM

■Clock, reset and supply management

–2.0 to 3.6 V application supply and I/Os

–POR, PDR and programmable voltage detector (PVD)

–4-to-16 MHz high-speed quartz oscillator

–Internal 8 MHz factory-trimmed RC

–Internal 32 kHz RC

–PLL for CPU clock

–Dedicated 32 kHz oscillator for RTC with calibration

■Low power

–Sleep, Stop and Standby modes

–VBAT supply for RTC and backup registers

■Debug mode

–Serial wire debug (SWD) and JTAG interfaces

■DMA

–7-channel DMA controller

–Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs

■12-bit, 1 µs A/D converter (16-channel)

–Conversion range: 0 to 3.6 V

LQFP48	LQFP64	LQFP100
7 x 7 mm	10 x 10 mm	14 x 14 mm

–Temperature sensor

■Up to 80 fast I/O ports

–32/49/80 5 V-tolerant I/Os

–All mappable on 16 external interrupt vectors

–Atomic read/modify/write operations

■Up to 6 timers

–Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter

–2 x 16-bit watchdog timers (Independent and Window)

–SysTick timer: 24-bit downcounter

■Up to 7 communication interfaces

–Up to 2 x I2C interfaces (SMBus/PMBus)

–Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)

–Up to 2 SPIs (18 Mbit/s)

	Table 1.	Device summary
	Reference		Root part number
	STM32F101x6		STM32F101C6, STM32F101R6
	STM32F101x8		STM32F101C8, STM32F101R8
			STM32F101V8
	STM32F101xB		STM32F101RB, STM32F101VB

July 2007

Rev 2

1/64

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to	www.st.com
change without notice.

Contents	STM32F101xx

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
	2.1	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.2	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
3	Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
4	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	5.1	Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24
5.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26
	5.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	5.3.2	Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . .	26
	5.3.3	Embedded reset and power control block characteristics . . . . . . . . . . .	27
	5.3.4	Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	5.3.5	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	5.3.6	External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	5.3.7	Internal Clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
	5.3.8	PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
	5.3.9	Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
	5.3.10	EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
	5.3.11	Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . .	40
	5.3.12	I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
	5.3.13	NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47

2/64

STM32F101xx	Contents

5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		58
	6.1	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
7	Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		62
	7.1	Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		63

3/64

List of tables	STM32F101xx

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Device features and peripheral counts (STM32F101xx access line) . . . . . . . . . . . . . . . . . . 7 Table 3. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 5. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 8. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. Maximum current consumption in Run and Sleep modes (TA = 85 °C) . . . . . . . . . . . . . . . 28 Table 12. Maximum current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . 29 Table 13. Typical current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 14. Typical current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 15. High-speed user external (HSE) clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 16. Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 17. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 18. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 19. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 20. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 21. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 22. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 23. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 24. Flash endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 25. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 26. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 27. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 28. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 29. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 30. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 31. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 32. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 33. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 34. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 35. SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 36. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 37. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 38. ADC accuracy (fPCLK2 = 10 MHz, fADC = 10 MHz, RAIN < 10 kΩ, VDDA = 3.3 V) . . . . . . . . 55 Table 39. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 40. LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 58 Table 41. LQFP64 – 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 59 Table 42. LQFP48 – 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 60 Table 43. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 44. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 45. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4/64

STM32F101xx	List of figures

List of figures

Figure 1.	STM32F101xx access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Figure 2.	STM32F101xx access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
Figure 3.	STM32F101xx access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Figure 4.	STM32F101xx access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Figure 5.	Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 6.	Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 7.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 8.	Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 9.	Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 10.	High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 11.	Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 12.	Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 13.	Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
Figure 14.	Unused I/O pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
Figure 15.	I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
Figure 16.	Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
Figure 17.	I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
Figure 18.	SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
Figure 19.	SPI timing diagram - slave mode and CPHA=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
Figure 20.	SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
Figure 21.	ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
Figure 22.	Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
Figure 23.	Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . .	56
Figure 24.	Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . .	56
Figure 25.	LQPF100 – 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . .	58
Figure 26.	LQFP64 – 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . .	59
Figure 27.	LQFP48 – 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . .	60

5/64

Introduction	STM32F101xx

1 Introduction

This datasheet contains the description of the STM32F101xx access line family features, pinout, Electrical Characteristics, Mechanical Data and Ordering information.

For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10x Flash Programming Reference Manual

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual.

2 Description

The STM32F101xx access line family incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash memory up to 128Kbytes and SRAM up to 16 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (two I2Cs, two SPIs, and up to three USARTs), one 12-bit ADC and three general purpose 16-bit timers.

The STM32F101 family operates in the −40 to +85°C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows to design low-power applications.

The complete STM32F101xx access line family includes devices in 3 different package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

These features make the STM32F101xx access line microcontroller family suitable for a wide range of applications:

●Application control and user interface

●Medical and handheld equipment

●PC peripherals, gaming and GPS platforms

●Industrial applications: PLC, inverters, printers, and scanners

●Alarm systems, Video intercom, and HVAC

Figure 1 shows the general block diagram of the device family.

6/64

STM32F101xx	Description

2.1Device overview

Table 2.		Device features and peripheral counts (STM32F101xx access line)
	Peripheral		STM32F101Cx				STM32F101Rx					STM32F101Vx
Flash - Kbytes			32		64	32		64		128		64		128
SRAM - Kbytes			6		10	6		10		16		10		16
Timers		General purpose	2		3		3					3
Communication		SPI	1		2	1		2				2
		I2C	1		2	1		2				2
		USART	2		3	2		3				3
12-bit synchronized ADC				1						1
number of channels			10 channels					16 channels
GPIOs				32			49					80
CPU frequency								36 MHz
Operating voltage							2.0 to 3.6 V
Operating temperature							-40 to +85 °C
Packages			LQFP48					LQFP64				LQFP100

7/64

Description	STM32F101xx

2.2Overview

ARM® CortexTM-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The STM32F101xx access line family having an embedded ARM core, is therefore compatible with all ARM tools and software.

Embedded Flash memory

Up to 128 Kbytes of embedded Flash is available for storing programs and data.

Embedded SRAM

Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

Nested vectored interrupt controller (NVIC)

The STM32F101xx access line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

●Closely coupled NVIC gives low latency interrupt processing

●Interrupt entry vector table address passed directly to the core

●Closely coupled NVIC core interface

●Allows early processing of interrupts

●Processing of late arriving higher priority interrupts

●Support for tail-chaining

●Processor state automatically saved

●Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

8/64

STM32F101xx	Description

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16 external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is monitored for failure. During such a scenario, it is disabled and software interrupt management follows. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the High Speed APB (APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 36 MHz.

Boot modes

At startup, boot pins are used to select one of five boot options:

●Boot from User Flash

●Boot from System Memory

●Boot from SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using the USART.

Power supply schemes

●VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins.

●VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs and PLL. In VDD range (ADC is limited at 2.4 V).

●VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.

The device features an embedded Programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to Table 9: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.

9/64

Description	STM32F101xx

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●MR is used in the nominal regulation mode (Run)

●LPR is used in the Stop modes

●Power down is used in Standby Mode: the regulator output is in high impedance: the kernel circuitry is powered-down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after RESET. It is disabled in Standby Mode, providing high impedance output.

Low-power modes

The STM32F101xx access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

●Stop mode

Stop mode allows to achieve the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.

●Standby mode

The Standby mode allows to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

Note:	The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
	or Standby mode.

DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers TIMx and ADC.

10/64

STM32F101xx	Description

RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers (ten 16-bit registers) can be used to store data when VDD power is not present.

The Real-Time Clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by an external 32.768 kHz oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application time out management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It features:

●A 24-bit down counter

●Autoreload capability

●Maskable system interrupt generation when the counter reaches 0.

●Programmable clock source

General purpose timers (TIMx)

There are up to 3 synchronizable standard timers embedded in the STM32F101xx access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture, output compare, PWM or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on the largest packages. They can work together via the Timer Link feature for synchronization or event chaining.

The counter can be frozen in debug mode.

Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations.

11/64

Description	STM32F101xx

I²C bus

Up to two I²C bus interfaces can operate in multi-master and slave modes. They can support standard and fast modes.

They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

Universal synchronous/asynchronous receiver transmitter (USART)

The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability.

The USART interfaces can be served by the DMA controller.

Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 8-bit to 16-bit. The hardware CRC generation/verification supports basic SD Card/MMC modes.

Both SPIs can be served by the DMA controller.

GPIOs (general purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as Peripheral Alternate Function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

ADC (analog to digital converter)

The 12-bit Analog to Digital Converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

Temperature sensor

The temperature sensor has to generate a linear voltage with any variation in temperature. The conversion range is between 2V < VDDA < 3.6V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

12/64

STM32F101xx	Description

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

Figure 1. STM32F101xx access line block diagram

			JTAG & SWD		pbus
JNTRST			Cortex M3 CPU		Ibus
JTDI

JTCK/SWCLK

JTMS/SWDIO

JTDO		Fmax: 36 MHz
				Dbus
as AF		NVIC

Trace

Controller

Interface

Flash obl

		POWER
		VOLT. REG.		VDD = 2 to 3.6V
FLASH 128 KB		3.3V TO 1.8V		VSS
64 bit		@VDD

					BusMatrix
NVIC
		System

GP DMA

7 channels

	@VDDA		=36 MHz
			max
	SUPPLY
			AHB:F
NRST	SUPERVISION
VDDA	POR / PDR	Rst
VSSA	PVD	Int
			AHB2
			APB2
80AF	EXTI
	WAKEUP
PA[15:0]	GPIOA
PB[15:0]	GPIOB
PC[15:0]	GPIOC
PD[15:0]	GPIOD		MHz
PE[15:0]	GPIOE
			= 36
			max
MOSI,MISO,			: F
	SPI1		APB2
SCK,NSS as AF
RX,TX, CTS, RTS,	USART1
SmartCard as AF
16AF	@VDDA
VREF+	12bit ADC1 IF
VREF-
	Temp sensor

SRAM

16 KB

@VDD

PCLK1

OSC_IN

PLL &

XTAL OSC

OSC_OUT

PCLK2

CLOCK

4-16 MHz

HCLK

MANAGT

FCLK

	RC 8 MHz	IWDG
	RC 32 kHz
		Standby
	@VDDA
		interface			VBAT
		@VBAT
		XTAL 32 kHz			OSC32_IN
					OSC32_OUT
	AHB2	RTC	Backup		ANTI_TAMP
				reg
	APB1	AWU
		Backup interface
		TIM2			4 Channels
		TIM3			4 Channels

APB1 : Fmax=24 / 36 MHz

	TIM4								4 Channels
									RX,TX, CTS, RTS,
	USART2								SmartCard as AF
									RX,TX, CTS, RTS,
	USART3								SmartCard as AF
									MOSI,MISO,SCK,NSS
	2x(8x16bit)SPI2
									as AF
	I2C1								SCL,SDA,SMBAL
									as AF

I2C2				SCL,SDA
				as AF
W W D G

ai14385

1.AF = alternate function on I/O port pin.

2.TA = –40 °C to +85 °C (junction temperature up to 125 °C).

13/64

Pin descriptions	STM32F101xx

3 Pin descriptions

Figure 2. STM32F101xx access line LQFP100 pinout

	VDD_3	VSS_3	PE1	PE0	PB9	PB8	BOOT0	PB7	PB6	PB5	PB4	PB3	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0	PC12	PC11	PC10	PA15	PA14
PE2	100	99	98	97	96	95	94	93	92	91	90	89	88	87	86	85	84	83	82	81	80	79	78	77	76
	1																								75	VDD_2
PE3	2																								74	VSS_2
PE4	3																								73	NC
PE5	4																								72	PA 13
PE6	5																								71	PA 12
VBAT	6																								70	PA 11
PC13-ANTI_TAMP	7																								69	PA 10
PC14-OSC32_IN	8																								68	PA 9
PC15-OSC32_OUT	9																								67	PA 8
VSS_5	10																								66	PC9
VDD_5	11										LQFP100														65	PC8
OSC_IN	12																								64	PC7
OSC_OUT	13																								63	PC6
NRST	14																								62	PD15
PC0	15																								61	PD14
PC1	16																								60	PD13
PC2	17																								59	PD12
PC3	18																								58	PD11
VSSA	19																								57	PD10
VREF-	20																								56	PD9
VREF+	21																								55	PD8
VDDA	22																								54	PB15
PA0-WKUP	23																								53	PB14
PA1	24																								52	PB13
PA2	25																								51	PB12
	26	27	28	29	30	31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50
	PA3	VSS_4	VDD_4	PA4	PA5	PA6	PA7	PC4	PC5	PB0	PB1	PB2	PE7	PE8	PE9	PE10	PE11	PE12	PE13	PE14	PE15	PB10	PB11	VSS_1	VDD_1
																										ai14386

14/64

STM32F101xx									Pin descriptions
	Figure 3. STM32F101xx access line LQFP64 pinout
			VDD 3	VSS 3	PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12	PC11 PC10	PA15	PA14
	VBAT	64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49							VDD_2
		1						48
	PC13-ANTI_TAMP	2						47	VSS_2
	PC14-OSC32_IN	3						46	PA13
	PC15-OSC32_OUT	4						45	PA12
	PD0 OSC_IN	5						44	PA11
	PD1 OSC_OUT	6						43	PA10
	NRST	7						42	PA9
	PC0		8		LQFP64			41	PA8
	PC1	9						40	PC9
	PC2	10						39	PC8
	PC3	11						38	PC7
	VSSA	12						37	PC6
	VDDA	13						36	PB15
	PA0-WKUP	14						35	PB14
	PA1	15						34	PB13
	PA2	16						33	PB12
		17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
			PA3	VSS 4	VDD 4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2	PB10 PB11	VSS 1	VDD 1
									ai14387

Figure 4. STM32F101xx access line LQFP48 pinout

	VDD 3	VSS 3	PB9 PB8	BOOT0 PB7 PB6 PB5	PB4 PB3 PA15		PA14
	48 47 46 45
VBAT				44 43 42 41 40 39 38 37					VDD_2
	1					36
PC13-ANTI_TAMP	2					35			VSS_2
PC14-OSC32_IN	3					34			PA13
PC15-OSC32_OUT	4					33			PA12
PD0 OSC_IN	5					32			PA11
PD1 OSC_OUT	6			LQFP48		31			PA10
NRST	7					30			PA9
VSSA	8					29			PA8
VDDA	9					28			PB15
PA0-WKUP	10					27			PB14
PA1	11					26			PB13
PA2	12					25			PB12
	13 14 15 16 17 18 19 20 21 22 23 24
	PA3	PA4	PA5 PA6	PA7 PB0 PB1 PB2	PB10 PB11 VSS 1	VDD 1

ai14378

15/64

Pin descriptions								STM32F101xx
Table 3.			Pin definitions
	Pins					(2)
LQFP48	LQFP64		LQFP100		Type
						O/Ilevel	Main
				Pin name	(1)			Default alternate functions(3)
							function(3)
							(after reset)
-	-		1	PE2/TRACECK	I/O	FT	PE2	TRACECK
-	-		2	PE3/TRACED0	I/O	FT	PE3	TRACED0
-	-		3	PE4/TRACED1	I/O	FT	PE4	TRACED1
-	-		4	PE5/TRACED2	I/O	FT	PE5	TRACED2
-	-		5	PE6/TRACED3	I/O	FT	PE6	TRACED3
1	1		6	VBAT	S		VBAT
2	2		7	PC13-ANTI_TAMP(4)	I/O		PC13	ANTI_TAMP
3	3		8	PC14-OSC32_IN(4)	I/O		PC14-
							OSC32_IN
4	4		9	PC15-OSC32_OUT(4)	I/O		PC15-
							OSC32_OUT
-	-		10	VSS_5	S		VSS_5
-	-		11	VDD_5	S		VDD_5
5	5		12	OSC_IN	I		OSC_IN
6	6		13	OSC_OUT	O		OSC_OUT
7	7		14	NRST	I/O		NRST
-	8		15	PC0/ADC_IN10	I/O		PC0	ADC_IN10
-	9		16	PC1/ADC_IN11	I/O		PC1	ADC_IN11
-	10		17	PC2/ADC_IN12	I/O		PC2	ADC_IN12
-	11		18	PC3/ADC_IN13	I/O		PC3	ADC_IN13
8	12		19	VSSA	S		VSSA
-	-		20	VREF-	S		VREF-
-	-		21	VREF+	S		VREF+
9	13		22	VDDA	S		VDDA
10	14		23	PA0-WKUP/USART2_CTS/	I/O		PA0	WKUP/USART2_CTS(7)/ ADC_IN0/
				ADC_IN0/TIM2_CH1_ETR				TIM2_CH1_ETR(7)
11	15		24	PA1/USART2_RTS/ADC_	I/O		PA1	USART2_RTS(7)/ADC_IN1/
				IN1/TIM2_CH2				TIM2_CH2(7)
12	16		25	PA2/USART2_TX/ADC_IN2/	I/O		PA2	USART2_TX(7)/ADC_IN2/
				TIM2_CH3				TIM2_CH3(7)
13	17		26	PA3/USART2_RX/ADC_IN3/	I/O		PA3	USART2_RX(7)/ADC_IN3/
				TIM2_CH4				TIM2_CH4(7)
-	18		27	VSS_4	S		VSS_4
-	19		28	VDD_4	S		VDD_4
16/64

STM32F101xx								Pin descriptions
Table 3.			Pin definitions (continued)
	Pins					(2)
LQFP48	LQFP64		LQFP100		Type
						O/Ilevel	Main
				Pin name	(1)			Default alternate functions(3)
							function(3)
							(after reset)
14	20		29	PA4/SPI1_NSS/	I/O		PA4	SPI1_NSS/USART2_CK(7)/
				USART2_CK/ADC_IN4				ADC_IN4
15	21		30	PA5/SPI1_SCK/ADC_IN5	I/O		PA5	SPI1_SCK/ADC_IN5
16	22		31	PA6/SPI1_MISO/ADC_IN6/	I/O		PA6	SPI1_MISO/ADC_IN6/
				TIM3_CH1				TIM3_CH1(7)
17	23		32	PA7/SPI1_MOSI/ADC_IN7/	I/O		PA7	SPI1_MOSI/ADC_IN7/
				TIM3_CH2				TIM3_CH2(7)
-	24		33	PC4/ADC_IN14	I/O		PC4	ADC_IN14
-	25		34	PC5/ADC_IN15	I/O		PC5	ADC_IN15
18	26		35	PB0/ADC_IN8/TIM3_CH3	I/O		PB0	ADC_IN8/TIM3_CH3(7)
19	27		36	PB1/ADC_IN9/TIM3_CH4	I/O		PB1	ADC_IN9/TIM3_CH4(7)
20	28		37	PB2/BOOT1	I/O	FT	PB2/BOOT1
-	-		38	PE7	I/O	FT	PE7
-	-		39	PE8	I/O	FT	PE8
-	-		40	PE9	I/O	FT	PE9
-	-		41	PE10	I/O	FT	PE10
-	-		42	PE11	I/O	FT	PE11
-	-		43	PE12	I/O	FT	PE12
-	-		44	PE13	I/O	FT	PE13
-	-		45	PE14	I/O	FT	PE14
-	-		46	PE15	I/O	FT	PE15
21	29		47	PB10/I2C2_SCL	I/O	FT	PB10	I2C2_SCL(5)/USART3_TX(5) (7)
				USART3_TX
22	30		48	PB11/I2C2_SDA	I/O	FT	PB11	I2C2_SDA(5)/USART3_RX(5) (7)
				USART3_RX
23	31		49	VSS_1	S		VSS_1
24	32		50	VDD_1	S		VDD_1
25	33		51	PB12/SPI2_NSS/	I/O	FT	PB12	SPI2_NSS(5) (7)/I2C2_SMBAl(5)/
				I2C2_SMBAl/USART3_CK				USART3_CK(5) (7)
26	34		52	PB13/SPI2_SCK/	I/O	FT	PB13	SPI2_SCK(5)(7)/USART3_CTS(5)(7)
				USART3_CTS
27	35		53	PB14/SPI2_MISO/	I/O	FT	PB14	SPI2_MISO(5)(7)/USART3_RTS(5)(7)
				USART3_RTS
28	36		54	PB15/SPI2_MOSI	I/O	FT	PB15	SPI2_MOSI(5) (7)
-	-		55	PD8	I/O	FT	PD8
								17/64

Pin descriptions									STM32F101xx
Table 3.			Pin definitions (continued)
	Pins						(2)
LQFP48	LQFP64		LQFP100			Type
							O/Ilevel	Main
					Pin name	(1)			Default alternate functions(3)
								function(3)
								(after reset)
-	-		56		PD9	I/O	FT	PD9
-	-		57		PD10	I/O	FT	PD10
-	-		58		PD11	I/O	FT	PD11
-	-		59		PD12	I/O	FT	PD12
-	-		60		PD13	I/O	FT	PD13
-	-		61		PD14	I/O	FT	PD14
-	-		62		PD15	I/O	FT	PD15
-	37		63		PC6	I/O	FT	PC6
	38		64		PC7	I/O	FT	PC7
	39		65		PC8	I/O	FT	PC8
-	40		66		PC9	I/O	FT	PC9
29	41		67		PA8/USART1_CK/MCO	I/O	FT	PA8	USART1_CK/MCO
30	42		68		PA9/USART1_TX	I/O	FT	PA9	USART1_TX(7)
31	43		69		PA10/USART1_RX	I/O	FT	PA10	USART1_RX(7)
32	44		70		PA11/USART1_CTS	I/O	FT	PA11	USART1_CTS
33	45		71		PA12/USART1_RTS	I/O	FT	PA12	USART1_RTS
34	46		72		PA13/JTMS/SWDIO	I/O	FT	JTMS-SWDIO	PA13
-	-		73				Not connected
35	47		74		VSS_2	S		VSS_2
36	48		75		VDD_2	S		VDD_2
37	49		76		PA14/JTCK/SWCLK	I/O	FT	JTCK/SWCLK	PA14
38	50		77		PA15/JTDI	I/O	FT	JTDI	PA15
-	51		78		PC10	I/O	FT	PC10
-	52		79		PC11	I/O	FT	PC11
-	53		80		PC12	I/O	FT	PC12
5	5		81		PD0	I/O	FT	OSC_IN(6)
6	6		82		PD1	I/O	FT	OSC_OUT(6)
	54		83		PD2/TIM3_ETR	I/O	FT	PD2	TIM3_ETR
-	-		84		PD3	I/O	FT	PD3
-	-		85		PD4	I/O	FT	PD4
-	-		86		PD5	I/O	FT	PD5
-	-		87		PD6	I/O	FT	PD6
18/64

STM32F101xx								Pin descriptions
Table 3.			Pin definitions (continued)
	Pins					(2)
LQFP48	LQFP64		LQFP100		Type
						O/Ilevel	Main
				Pin name	(1)			Default alternate functions(3)
							function(3)
							(after reset)
-	-		88	PD7	I/O	FT	PD7
39	55		89	PB3/JTDO/TRACESWO	I/O	FT	JTDO	PB3/TRACESWO
40	56		90	PB4/JNTRST	I/O	FT	JNTRST	PB4
41	57		91	PB5/I2C1_SMBAl	I/O		PB5	I2C1_SMBAl
42	58		92	PB6/I2C1_SCL/TIM4_CH1	I/O	FT	PB6	I2C1_SCL(7)/TIM4_CH1(5) (7)
43	59		93	PB7/I2C1_SDA/TIM4_CH2	I/O	FT	PB7	I2C1_SDA(7)/TIM4_CH2(5) (7)
44	60		94	BOOT0	I		BOOT0
45	61		95	PB8/TIM4_CH3	I/O	FT	PB8	TIM4_CH3(5) (7)
46	62		96	PB9/TIM4_CH4	I/O	FT	PB9	TIM4_CH4(5) (7)
-	-		97	PE0/TIM4_ETR	I/O	FT	PE0	TIM4_ETR(5)
-	-		98	PE1	I/O	FT	PE1
47	63		99	VSS_3	S		VSS_3
48	64		100	VDD_3	S		VDD_3

1.I = input, O = output, S = supply, HiZ= high impedance.

2.FT= 5 V tolerant.

3.Function availability depends on the chosen device. Refer to Table 2 on page 7.

4.PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.

5.Available only on devices with a Flash memory density equal or higher than 64 Kbytes.

6.For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins.

7.This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, UM0306, available from the STMicroelectronics website: www.st.com.

19/64

Memory mapping	STM32F101xx

4 Memory mapping

The memory map is shown in Figure 5.

Figure 5. Memory map

0xFFFF FFFF

0xFFFF F000

7

0xE010 0000

0xE000 0000

6

0xC000 0000

5

0xA000 0000

4

0x8000 0000

3

0x6000 0000

2

0x4000 0000

1

0x2000 0000

0

0x0000 0000

ai14379

Cortex-M3 internal peripherals

Peripherals

SRAM

Code

Reserved

0x1FFF FFFF

reserved

0x1FFF F9FF

Option bytes

0x1FFF F800

System memory

0x1FFF F000

reserved

0x0801 FFFF

Flash memory

0x0800 0000

	APB memory space
0xFFFF FFFF
0xE010 0000			reserved
0x6000	0000		reserved
0x4002	3400		reserved	4K
0x4002	3000		reserved	1K
0x4002	2400		reserved	3K
0x4002	2000		Flash interface	1K
0x4002	1400		reserved	3K
0x4002	1000		RCC	1K
0x4002	0400		reserved	3K
0x4002	0000		DMA	1K
			reserved	1K
0x4001	3C00			1K
0x4001	3800		USART1
				1K
0x4001	3400		reserved
0x4001	3000		SPI1	1K
0x4001	2C00		reserved	1K
0x4001	2800		reserved	1K
0x4001	2400		ADC1	1K
			reserved	2K
0x4001	1C00
0x4001	1800		Port E	1K
0x4001	1400		Port D	1K
0x4001	1000		Port C	1K
0x4001	0C00		Port B	1K
0x4001	0800		Port A	1K
0x4001	0400		EXTI	1K
0x4001	0000		AFIO	1K
			reserved	35K
0x4000	7400
0x4000	7000		PWR	1K
0x4000	6C00		BKP	1K
0x4000	6800		reserved	1K
0x4000	6400		reserved	1K
0x4000	6000		reserved	1K
0x4000	5C00		reserved	1K
0x4000	5800		I2C2	1K
0x4000	5400		I2C1	1K
			reserved	2K
0x4000	4C00
0x4000	4800		USART3	1K
0x4000	4400		USART2	1K
			reserved	2K
0x4000	3C00
0x4000	3800		SPI2	1K
				1K
0x4000	3400		reserved
0x4000	3000		IWDG	1K
0x4000	2C00		WWDG	1K
0x4000	2800		RTC	1K
			reserved	7K
0x4000	0C00
0x4000	0800		TIM4	1K
0x4000	0400		TIM3	1K
0x4000	0000		TIM2	1K

20/64