ST STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE User Manual

STM32F405xx

STM32F407xx

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

Features

■Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/

1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

■Memories

– Up to 1 Mbyte of Flash memory

– Up to 192+4 Kbytes of SRAM including 64Kbyte of CCM (core coupled memory) data RAM

– Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories

■LCD parallel interface, 8080/6800 modes

■Clock, reset and supply management

– 1.8 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC (1% accuracy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

●Low power

–Sleep, Stop and Standby modes

–VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM

■3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode

■2×12-bit D/A converters

■General-purpose DMA: 16-stream DMA controller with FIFOs and burst support

■Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

■Debug mode

–Serial wire debug (SWD) & JTAG interfaces

–Cortex-M4 Embedded Trace Macrocell™

Datasheet − production data

						FBGA
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)	WLCSP90				UFBGA176
LQFP144 (20 × 20 mm)					(10 × 10 mm)

LQFP176 (24 × 24 mm)

■Up to 140 I/O ports with interrupt capability

–Up to 136 fast I/Os up to 84 MHz

–Up to 138 5 V-tolerant I/Os

■Up to 15 communication interfaces

–Up to 3 × I2C interfaces (SMBus/PMBus)

–Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)

–Up to 3 SPIs (37.5 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock

–2 × CAN interfaces (2.0B Active)

–SDIO interface

■Advanced connectivity

–USB 2.0 full-speed device/host/OTG controller with on-chip PHY

–USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI

–10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII

■8- to 14-bit parallel camera interface up to 54 Mbytes/s

■True random number generator

■CRC calculation unit

■96-bit unique ID

■RTC: subsecond accuracy, hardware calendar

Table 1. Device summary

Reference

Part number

STM32F405xx

STM32F405RG, STM32F405VG, STM32F405ZG,

STM32F405OG, STM32F405OE

STM32F407xx

STM32F407VG, STM32F407IG, STM32F407ZG,

STM32F407VE, STM32F407ZE, STM32F407IE

May 2012

Doc ID 022152 Rev 3

1/180

This is information on a product in full production.

www.st.com

Contents	STM32F405xx, STM32F407xx

Contents

1	Introduction		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
2	Description . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	2.1	Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	2.2	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
		2.2.1	ARM® Cortex™-M4F core with embedded Flash and SRAM . . . . . . . .	19
		2.2.2	Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . .	19
		2.2.3	Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
		2.2.4	Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
		2.2.5	CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . .	20
		2.2.6	Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
		2.2.7	Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
		2.2.8	DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
		2.2.9	Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . .	22
		2.2.10	Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . .	22
		2.2.11	External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . .	22
		2.2.12	Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
		2.2.13	Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
		2.2.14	Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
		2.2.15	Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
		2.2.16	Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
		2.2.17	Real-time clock (RTC), backup SRAM and backup registers . . . . . . . .	27
		2.2.18	Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
		2.2.19	VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
		2.2.20	Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
		2.2.21	Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . .	31

2.2.22Universal synchronous/asynchronous receiver transmitters (USART) . 31

2.2.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
2.2.24	Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
2.2.25	Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
2.2.26 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . .		33

2.2.27Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 33

2.2.28 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.29 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 34

2/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	Contents

2.2.30 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 34 2.2.31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.32 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.33 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.34 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.35 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.36 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.38 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3	Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
4	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	63
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
	5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		70
5.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		71
	5.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
	5.3.2	VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	74
	5.3.3	Operating conditions at power-up / power-down (regulator ON) . . . . . .	74

5.3.4Operating conditions at power-up / power-down (regulator OFF) . . . . . 74

5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 75 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 98 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Doc ID 022152 Rev 3

3/180

Contents	STM32F405xx, STM32F407xx

5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 103 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 150 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 150 5.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

6	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		152
	6.1	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	152
	6.2	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	163
7	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		164
Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			165
	A.1	Main applications versus package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	165
	A.2	Application example with regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . .	166
	A.3	USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . .	167
	A.4	USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . .	169
	A.5	Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	170
	A.6	Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	173
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		175

4/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 13 Table 3. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 4. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 5. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 6. STM32F40x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 7. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 8. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 9. STM32F40x register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 10. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 11. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 12. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 13. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 14. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 73 Table 15. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 16. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 74 Table 17. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 74 Table 18. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 19. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 20. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 78 Table 21. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 22. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 23. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 82

Table 24. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 83 Table 25. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 26. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 28. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 29. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 30. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 31. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 32. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 33. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 34. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 35. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 36. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 37. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 38. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 39. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 40. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Doc ID 022152 Rev 3

5/180

List of tables	STM32F405xx, STM32F407xx

Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 50. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 51. Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 52. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 53. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 54. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 55. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 56. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 57. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 58. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 59. USB FS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 60. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 61. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 62. ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 63. Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 64. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 65. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 66. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 67. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 68. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 69. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 70. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 71. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 72. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 133 Table 74. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 134 Table 75. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 76. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 77. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 78. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 79. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 80. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 81. Switching characteristics for PC Card/CF read and write cycles

in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 82. Switching characteristics for PC Card/CF read and write cycles

in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 83. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 84. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 85. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 86. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 87. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 88. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . 153 Table 89. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 154 Table 90. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 156 Table 91. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 158 Table 92. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 93. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . 161 Table 94. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 95. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	List of tables

Table 96. Main applications versus package for STM32F407xx microcontrollers . . . . . . . . . . . . . . 165 Table 97. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Doc ID 022152 Rev 3

7/180

List of figures	STM32F405xx, STM32F407xx

List of figures

Figure 1.	Compatible board design between STM32F10xx/STM32F4xx for LQFP64 . . . . . . . . . . .	. 15
Figure 2.	Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
	for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 16
Figure 3.	Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx
	for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 4.	Compatible board design between STM32F2xx and STM32F4xx
	for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 5.	STM32F40x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
Figure 6.	Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 7.	Regulator ON/internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 8.	Startup in regulator OFF mode: slow VDD slope
	- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 9.	Startup in regulator OFF mode: fast VDD slope
	- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . .	26
Figure 10.	STM32F40x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Figure 11.	STM32F40x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
Figure 12.	STM32F40x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 13.	STM32F40x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
Figure 14.	STM32F40x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
Figure 15.	STM32F40x WLCSP90 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
Figure 16.	STM32F40x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	63
Figure 17.	Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
Figure 18.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
Figure 19.	Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
Figure 20.	Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
Figure 21.	External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	74
Figure 22.	Typical current consumption vs temperature, Run mode, code with data
	processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . .	79
Figure 23.	Typical current consumption vs temperature, Run mode, code with data
	processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . .	79
Figure 24.	Typical current consumption vs temperature, Run mode, code with data
	processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . .	80
Figure 25.	Typical current consumption vs temperature, Run mode, code with data
	processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . .	80
Figure 26.	Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . .	83
Figure 27.	Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . .	84
Figure 28.	High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
Figure 29.	Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
Figure 30.	Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	92
Figure 31.	Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	93
Figure 32.	ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	95
Figure 33.	PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	99
Figure 34.	PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	99
Figure 35.	I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	108
Figure 36.	Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	109
Figure 37.	I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	113
Figure 38.	SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	115
Figure 39.	SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	115

8/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	List of figures
Figure 40. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . .	116
Figure 41. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	118
Figure 42. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	118
Figure 43. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . .	. . . . . . . .	120
Figure 44. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	121
Figure 45. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	122
Figure 46. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	123
Figure 47. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	123
Figure 48. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	127
Figure 49. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	127
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . .	. . . . . . . .	128
Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . .	. . . . . . . .	128
Figure 52. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	132
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . .	. . . . . . . .	133
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . .	. . . . . . . .	134
Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . .	. . . . . . . .	135
Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . .	. . . . . . . .	136
Figure 57. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . .	. . . . . . . .	137
Figure 58. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	139
Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . .	. . . . . . . .	140
Figure 60. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	141
Figure 61. PC Card/CompactFlash controller waveforms for common memory read access . . . . . .		142
Figure 62. PC Card/CompactFlash controller waveforms for common memory write access . . . . . .		143
Figure 63. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	144
Figure 64. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	145
Figure 65. PC Card/CompactFlash controller waveforms for I/O space read access . . . .	. . . . . . . .	145
Figure 66. PC Card/CompactFlash controller waveforms for I/O space write access . . . .	. . . . . . . .	146
Figure 67. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	148
Figure 68. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	148
Figure 69. NAND controller waveforms for common memory read access . . . . . . . . . . . .	. . . . . . . .	149
Figure 70. NAND controller waveforms for common memory write access. . . . . . . . . . . .	. . . . . . . .	149
Figure 71. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	150
Figure 72. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	151
Figure 73. WLCSP90 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . .	. . . . . . . .	153
Figure 74. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . .	. . . . . . . .	154
Figure 75. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	155
Figure 76. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . .	. . . . . . . .	156
Figure 77. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	157
Figure 78. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . .	. . . . . . . .	158
Figure 79. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	159
Figure 80. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	160
Figure 81. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . .	. . . . . . . .	161
Figure 82. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	162
Figure 83. Regulator OFF/internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	166
Figure 84. Regulator OFF/internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	166
Figure 85. USB controller configured as peripheral-only and used
in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	167
Figure 86. USB controller configured as host-only and used in full speed mode. . . . . . . .	. . . . . . . .	167
Figure 87. USB controller configured in dual mode and used in full speed mode . . . . . . .	. . . . . . . .	168

Doc ID 022152 Rev 3

9/180

List of figures		STM32F405xx, STM32F407xx
Figure 88. USB controller configured as peripheral, host, or dual-mode
	and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . .	169
Figure 89. Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . .	170
Figure 90. Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . .	170
Figure 91. Audio player solution using PLL, PLLI2S, USB and 1 crystal .		. . . . . . . . . . . . . . . . . . . . .	171
Figure 92. Audio PLL (PLLI2S) providing accurate I2S clock . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . .	171
Figure 93. Master clock (MCK) used to drive the external audio DAC. . .		. . . . . . . . . . . . . . . . . . . . .	172
Figure 94.	Master clock (MCK) not used to drive the external audio DAC. . . . . . . . . . . . . . . . . . . . .		172
Figure 95.	MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . .	173
Figure 96.	RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . .	173
Figure 97.	RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . .	174

10/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	Introduction

1 Introduction

This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family.

The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual.

For information on programming, erasing and protection of the internal Flash memory, please refer to the STM32F4xx Flash programming manual (PM0081).

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M4 core please refer to the Cortex™-M4 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/.

Doc ID 022152 Rev 3

11/180

Description	STM32F405xx, STM32F407xx

2 Description

The STM32F405xx and STM32F407xx family is based on the high-performance ARM® Cortex™-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this document.

The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces.

●Up to three I2Cs

●Three SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.

●Four USARTs plus two UARTs

●An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI),

●Two CANs

●An SDIO/MMC interface

●Ethernet and the camera interface available on STM32F407xx devices only.

New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features and peripheral counts for the list of peripherals available on each part number.

The STM32F405xx and STM32F407xx family operates in the –40 to +105 °C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range and an inverted reset signal is applied to PDR_ON. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.

These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications:

●Motor drive and application control

●Medical equipment

●Industrial applications: PLC, inverters, circuit breakers

●Printers, and scanners

●Alarm systems, video intercom, and HVAC

●Home audio appliances

12/180

Doc ID 022152 Rev 3

Figure 5 shows the general block diagram of the device family.

Table 2.

STM32F405xx and STM32F407xx: features and peripheral counts

Peripherals

STM32F405RG

STM32F405OG

STM32F405VG

STM32F405ZG

STM32F405OE

STM32F407Vx

STM32F407Zx

STM32F407Ix

Flash memory in Kbytes

1024

512

512

1024

512

1024

512

1024

SRAM in Kbytes

System

192(112+16+64)

Backup

4

FSMC memory controller

No

Yes(1)

Ethernet

No

Yes

General-purpose

10

Advanced-control

2

Timers

Basic

2

Doc

IWDG

Yes

ID

WWDG

Yes

022152

RTC

Yes

Random number generator

Yes

3 Rev

SPI / I2S

3/2 (full duplex)(2)

I2C

3

USART/UART

4/2

Communication

USB OTG FS

Yes

interfaces

USB OTG HS

Yes

CAN

2

SDIO

Yes

Camera interface

No

Yes

GPIOs

51

72

82

114

72

82

114

140

12-bit ADC

3

Number of channels

16

13

16

24

13

16

24

24

12-bit DAC

Yes

13/180

Number of channels

2

Maximum CPU frequency

168 MHz

STM32F407xx STM32F405xx,

Description

14/180

3 Rev 022152 ID Doc

Table 2.	STM32F405xx and STM32F407xx: features and peripheral counts (continued)
	Peripherals	STM32F405RG	STM32F405OG	STM32F405VG	STM32F405ZG	STM32F405OE		STM32F407Vx	STM32F407Zx	STM32F407Ix
Operating voltage					1.8 to 3.6	V(3)
Operating temperatures				Ambient temperatures: –40 to +85 °C /–40 to +105 °C
				Junction temperature: –40 to + 125			°C
Package		LQFP64	WLCSP90	LQFP100	LQFP144	WLCSP90		LQFP100	LQFP144	UFBGA176
										LQFP176

1.For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.

2.The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.

3.VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C temperature range and an inverted reset signal is applied to PDR_ON.

Description

STM32F407xx STM32F405xx,

STM32F405xx, STM32F407xx	Description

2.1Full compatibility throughout the family

The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pin- to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle.

The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F405xx and STM32F407xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40x family remains simple as only a few pins are impacted.

Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the STM32F40x, STM32F2xxx, and STM32F10xxx families.

Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64

																	633
			633
																	633
									633
													Ω RESISTORIOR SOLDERINGNBRIDGE
													PRESENTSFOR THE 34- & XX
													CONFIGURATION NOT PRESENT IN THE
													34- & XX CONFIGURATIONI

AI

Doc ID 022152 Rev 3

15/180

Description	STM32F405xx, STM32F407xx

Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package

													633
																																			633
																													633
																																ªΩ RESISTOR ORTSOLDERINGNBRIDGE
											633																					PRESENTSFOR THE 34- & XXX
																																CONFIGURATION NOT PRESENT IN THE
																																34- & XX CONFIGURATIONI
																						633
6$$ 633
																											633 FOR 34- & XX
							4WOO Ω RESISTORSSCONNECTED TO
6									33	FOR THE 34- & XX			6$$633														6$$ FOR 34- & XX
							633 FOR THE 34- & XX
						633 6$$ ORO.# FOR THE 34- & XX																																			AI C

Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package

633

633

633

Ω

RESISTORIOR SOLDERINGNBRIDGE

PRESENTSFOR THE 34- & XX

)NVERTEDE

0$2?/.

CONFIGURATION NOT PRESENT IN THE

34- & XX CONFIGURATIONI

RESETSSIGNAL

633

6$$ 633

6 33 FOR 34- & XX

4WOO Ω RESISTORS CONNECTED TO

633 FOR THE 34- & XX

6$$ 633

6

$$ FOR 34- & XX

633 6$$ ORO.# FOR THE 34- & XX

6$$ OROINVERTEDERESETRSIGNAL FOR THE 34- & XX

AI C

16/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	Description

Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 package

)NVERTEDE RESETSSIGNAL

0$2?/.

6$$ 633

4WOO Ω RESISTORS CONNECTED TO633 6$$ ORO.# FOR THE 34- & XX

6$$ OROINVERTEDERESETRSIGNAL FOR THE 34- & XX

-3 6

Doc ID 022152 Rev 3

17/180

Description	STM32F405xx, STM32F407xx

2.2Device overview

Figure 5. STM32F40x block diagram

##-#DATA 2!- A+"

%XTERNALAMEMORY

#,+ .% ; = !; =

.*4234 *4$)

CONTROLLER &3-#

$; = /%. =7%.

*4#+ 37#,+

*4!'' 37

-05

!("

32!- !032!- ./2 &LASH

.",; = ., .2%'

*4$/ 37$ *4$/

%4-

.6)#

0# #ARD# !4! .!.$ &LASH

.7!)4 )/2$9 #$

.)/2$ )/72 2).4; =

42!#%#,+

42!#%$; =

$ "53

).4. 4.))3 AS)!&

!2-2#ORTEX -

-(Z

) "53

-

&LASH

&05

3 "53

3

-)))OR 2-))RAS !&

%THERNETE-!# $-!

MATRIX!("(BUS

2.'

&)&/ &)&/

(39.# 639.#

-$)/ AS/!&

&)&/

#AMERA

53"

INTERFACE

05)8#,+ $; =

0(9

$-!

$0 $-

5,0) #+ $; = $)2 ;340 .84

/4' (3

&)&/

53"

$0

3#, 3$! ).4. .)$ 6"53 3/&

$-

/4' &3 0(9

$-!

3TREAMS

!(" -(Z

3#, 3$! ).4. )$ 6"53 3/&

&)&/

$-!

3TREAMS

6$$

0OWER MANAGMT

&)&/

6OLTAGE

6$$$ $ TO 6

REGULATOR

633

TO 6

6$$

6#!0 6#0!

6$$!

0/2/

2# (3

3UPPLY

0!; =

'0)/ 0/244!

RESET

SUPERVISION

0"; =

2# ,3

)NT

0/2 0$2

6$$! 633!

'0)/ 0/244"

"/2

0,,

.234

06$

0#; =

'0)/ 0/244#

6$$! 6$$

0$; =

'0)/ 0/244$

84!, /3#

/3#?).

0%; =

-(Z

/3#?/54

'0)/ 0/244%

)7$'

!'4

0&; =

'0)/ 0/244&

3TANDBY

6"!44 TO 6

0'; =

INTERFACE

'0)/ 0/244'

(#,+X 0#,+X

6"!4

/3# ?).

0(; =

'0)/ 0/244(

,3

84!, K(Z

/3# ?/54

24#

0); =

'0)/ 0/244)

24#?!&

!75

24#?!&

,3

"ACKUPUREGISTER

+" "+032!-

4)-

B

CHANNELS %42%AS !&

4)-

B

CHANNELS %42%AS !&

$-!

4)-

B

CHANNELS %42%AS !&

!&!

%848)4 7+50

!(" !0" !(" !0"

4)-

B

CHANNELS

$; =

&)&/

4)-

B

CHANNELS ASN!&

#-$ #+ AS+!&

3$)/ --#

4)-

B

CHANNELAAS !&

MPL CHANNELSN 4)- ?#( ; =.

CHANNELS 4)- ?#( ; =%42

4)- 07- B

4)-

B

CHANNELAAS !&

"+). AS.!&

MPL CHANNELSN 4)- ?#( ; =.

4)- 07- B

SMCARD

28 848 AS !&

CHANNELS 4)- ?#( ; =%42

77$'

53!24

IR$!

#43 243 AS !&

"+). AS.!&

SMCARD

28 848 AS !&

CHANNELS ASN!&

4)-

B

53!24

IR$!

#43 243 AS !&

CHANNELAAS !&

4)-

B

-(Z

5!24

28 848 AS !&

5!24

28 848 AS !&

CHANNELAAS !&

4)-

B

!0"

MAX(Z-

28 848 8#+

SMCARD

53!24

30 ) 3

-/3) 3$ -)3/ 3$?EXT T3#+ #+

4)-

B

.33 73 -#+-AS !&

#43 243 AS !&

IR$!

-

-/3) 3$ -)3/ 3$?EXT T3#+ #+

28 848 8#+

SMCARD

53!24

!0"

30 ) 3

.33 73 -#+-AS !&

#43 243 AS !&

IR$!

!0"(Z-

4)-

B

!0"

) # 3-"53

3#, 3$! 3-"!3AS !&

-/3) 3-)3/

30)

3#+ .33 AS.!&

) # 3-"53

3#, 3$! 3-"!3AS !&

6$$!

6$$2%&?!$#

4EMPERATUREUSENSOR53!24-"PS

) # 3-"53

3#, 3$! 3-"!3AS !&

ANALOG INPUTSGCOMMON

6$$!

!$#

TO THE !$#S

$!#

ANALOG INPUTSGCOMMON

!$#

)&

)4&

BX#!.

&)&/

48 828

TO THE !$# E

$!#

!$#

ANALOG INPUTSGFOR !$#

BX#!.

48 828

$!# ?/54 $!# ?/54

AS !&

AS !&

-3 6

1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked

18/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	Description

from TIMxCLK up to 84 MHz.

2. The camera interface and ethernet are available only on STM32F407xx devices.

2.2.1ARM® Cortex™-M4F core with embedded Flash and SRAM

	The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded
	systems. It was developed to provide a low-cost platform that meets the needs of MCU
	implementation, with a reduced pin count and low-power consumption, while delivering
	outstanding computational performance and an advanced response to interrupts.
	The ARM Cortex-M4F 32-bit RISC processor features exceptional code-efficiency,
	delivering the high-performance expected from an ARM core in the memory size usually
	associated with 8- and 16-bit devices.
	The processor supports a set of DSP instructions which allow efficient signal processing
	and complex algorithm execution.
	Its single precision FPU (floating point unit) speeds up software development by using
	metalanguage development tools, while avoiding saturation.
	The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software.
	Figure 5 shows the general block diagram of the STM32F40x family.
Note:	Cortex-M4F is binary compatible with Cortex-M3.

2.2.2Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex™-M4F processors. It balances the inherent performance advantage of the ARM Cortex-M4F over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies.

To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 168 MHz.

2.2.3Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

Doc ID 022152 Rev 3

19/180

Description	STM32F405xx, STM32F407xx

2.2.4Embedded Flash memory

The STM32F40x devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data.

2.2.5CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

2.2.6Embedded SRAM

All STM32F40x products embed:

●Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM

RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.

●4 Kbytes of backup SRAM

This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode.

2.2.7Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

20/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	Description

Figure 6. Multi-AHB matrix

+BYTE	!2-			'0		'0	-!#	53"3/4'
##-#DATA 2!-	#ORTEX -		$-!			$-!	%THERNET	(3
)BUS	$BUS	3BUS	$-!?0)	$-!?-%-	$-!?-%-	$-!?0	%4(%2.%4?-	53"?(3?-
3	3	3		3	3		3 3	3
								- )#/$%
								- $#/$%
								-
								-
								-
								-

-

"USUMATRIX 3

!##%,

&LASH MEMORY

32!-+BYTE

32!-+BYTE

!("

PERIPHERALS !0"

!("

PERIPHERALS

!0"

&3-# 3TATIC -EM#TL

AI B

2.2.8DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals:

●SPI and I2S

●I2C

●USART

●General-purpose, basic and advanced-control timers TIMx

●DAC

●SDIO

●Camera interface (DCMI)

●ADC.

Doc ID 022152 Rev 3

21/180

Description	STM32F405xx, STM32F407xx

2.2.9Flexible static memory controller (FSMC)

The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash.

Functionality overview:

●Write FIFO

●Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz.

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.

2.2.10Nested vectored interrupt controller (NVIC)

The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M4F.

●Closely coupled NVIC gives low-latency interrupt processing

●Interrupt entry vector table address passed directly to the core

●Allows early processing of interrupts

●Processing of late arriving, higher-priority interrupts

●Support tail chaining

●Processor state automatically saved

●Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

2.2.11External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines.

2.2.12Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full

temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL

22/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	Description

clock entry is available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

2.2.13Boot modes

At startup, boot pins are used to select one out of three boot options:

●Boot from user Flash

●Boot from system memory

●Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).

2.2.14Power supply schemes

●VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins.

●VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

●VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

	Refer to Figure 19: Power supply scheme for more details.
Note:	VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C
	temperature range and an inverted reset signal is applied to PDR_ON.

2.2.15 Power supply supervisor

The power supply supervisor is enabled by holding PDR_ON high.

The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold level is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes.

The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit.

The device also features an embedded programmable voltage detector (PVD) that monitors

the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher

than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

Doc ID 022152 Rev 3

23/180

Description	STM32F405xx, STM32F407xx

All packages, except for the LQFP64 and LQFP100, have an internal reset controlled through the PDR_ON signal.

2.2.16Voltage regulator

The regulator has eight operating modes:

●Regulator ON/internal reset ON

–Main regulator mode (MR)

–Low power regulator (LPR)

–Power-down

●Regulator ON/internal reset OFF

–Main regulator mode (MR)

–Low power regulator (LPR)

–Power-down

●Regulator OFF/internal reset ON

●Regulator OFF/internal reset OFF

Regulator ON

●Regulator ON/internal reset ON

The regulator ON/internal reset ON mode is always enabled on LQFP64 and LQFP100 package.

On LQFP144 package, this mode is activated by setting PDR_ON to VDD.

On UFBGA176 package, the internal regulator must be activated by connecting BYPASS_REG to VSS, and PDR_ON to VDD.

On LQFP176 packages, the internal reset must be activated by connecting PDR_ON to VDD.

There are three low-power modes:

–MR is used in the nominal regulation mode (Run)

–LPR is used in the Stop modes

–Power-down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost).

●Regulator ON/internal reset OFF

The regulator ON with internal reset OFF mode is not available on LQFP64 and LQFP100 packages.

On LQFP144, and LQFP176 packages, the internal reset is controlled by applying an inverted reset signal to PDR_ON pin.

On UFBGA176 package, the internal regulator must be activated by connecting BYPASS_REG to VSS.

On LQFP176 packages, the internal reset must be activated by applying an inverted reset signal to PDR_ON pin.

VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C temperature range and an inverted reset signal is applied to PDR_ON.

The NRST pin should be controlled by an external reset controller to keep the device under reset when VDD is below 1.8 V (see Figure 7).

24/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	Description

Figure 7. Regulator ON/internal reset OFF

	6$$
0$2 6
	TIME
.234	0$2?/.
	.EXT RESET
	ASSERTED
0$2?/.
	TIME

-3 6

Regulator OFF

This mode allows to power the device as soon as VDD reaches 1.8 V.

●Regulator OFF/internal reset ON

This mode is available only on UFBGA and WLCSP90 packages. It is activated by setting BYPASS_REG and PDR_ON pins to VDD.

The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD.

The following conditions must be respected:

–VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.

–If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to reach 1.8 V, then PA0 should be connected to the NRST pin (see Figure 8).

Otherwise, PA0 should be asserted low externally during POR until VDD reaches 1.8 V (see Figure 9).

–If VCAP_1 and VCAP_2 go below 1.08 V and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin.

In regulator OFF/internal reset ON mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in off.

●Regulator OFF/internal reset OFF

This mode is available only on UFBGA and WLCSP packages. It is activated by setting BYPASS_REG pin to VDD and by applying an inverted reset signal to PDR_ON, and

Doc ID 022152 Rev 3

25/180

Description	STM32F405xx, STM32F407xx

allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD.

The following conditions must be respected:

–VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.

–PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V and until VDD reaches 1.8 V (see Figure 8).

–NRST should be controlled by an external reset controller to keep the device under reset when VDD is below 1.8 V (see Figure 9).

Figure 8. Startup in regulator OFF mode: slow VDD slope

- power-down reset risen after VCAP_1/VCAP_2 stabilization

6$$
0$2 6
6#!0? 6#!0?
6
6
TIME
0! TIEDTTO .234
.234
TIME

AI C

1. This figure is valid both whatever the internal reset mode (on or off).

Figure 9. Startup in regulator OFF mode: fast VDD slope

- power-down reset risen before VCAP_1/VCAP_2 stabilization

6$$
0$2 6
6#!0? 6#!0?
6
6
TIME
.234
0! ASSERTEDEEXTERNALLYL
TIME

AI C

1. This figure is valid both whatever the internal reset mode (on or off).

26/180

Doc ID 022152 Rev 3

STM32F405xx, STM32F407xx	Description

2.2.17Real-time clock (RTC), backup SRAM and backup registers

The backup domain of the STM32F405xx and STM32F407xx includes:

●The real-time clock (RTC)

●4 Kbytes of backup SRAM

●20 backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format.

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.

Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.

A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 2.2.18: Low-power modes). It can be enabled by software.

The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 2.2.18: Low-power modes).

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin.

2.2.18Low-power modes

The STM32F405xx and STM32F407xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

●Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC

Doc ID 022152 Rev 3

27/180

Description	STM32F405xx, STM32F407xx

and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).

●Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected.

The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs.

The standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power.

Note:	When in Standby mode, only an RTC alarm/event or an external reset can wake up the
	device provided VDD is supplied by an external battery.

2.2.19	VBAT operation
	The VBAT pin allows to power the device VBAT domain from an external battery, an external
	supercapacitor, or from VDD when no external battery and an external supercapacitor are
	present.
	VBAT operation is activated when VDD is not present.
	The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note:	When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
	do not exit it from VBAT operation.

2.2.20Timers and watchdogs

The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers.

All timer counters can be frozen in debug mode.

Table 3 compares the features of the advanced-control, general-purpose and basic timers.

28/180

Doc ID 022152 Rev 3

	STM32F405xx, STM32F407xx								Description
	Table 3.	Timer feature comparison
						DMA	Capture/		Max	Max
	Timer type	Timer	Counter	Counter	Prescaler			Complementary	interface	timer
			resolution	type	factor	request	compare	output	clock	clock
						generation	channels
									(MHz)	(MHz)
	Advanced-	TIM1,		Up,	Any integer
			16-bit	Down,	between 1	Yes	4	Yes	84	168
	control	TIM8
				Up/down	and 65536
		TIM2,		Up,	Any integer
			32-bit	Down,	between 1	Yes	4	No	42	84
		TIM5
				Up/down	and 65536
		TIM3,		Up,	Any integer
			16-bit	Down,	between 1	Yes	4	No	42	84
		TIM4
				Up/down	and 65536
					Any integer
		TIM9	16-bit	Up	between 1	No	2	No	84	168
	General				and 65536
	purpose	TIM10,			Any integer
			16-bit	Up	between 1	No	1	No	84	168
		TIM11
					and 65536
					Any integer
		TIM12	16-bit	Up	between 1	No	2	No	42	84
					and 65536
		TIM13,			Any integer
			16-bit	Up	between 1	No	1	No	42	84
		TIM14
					and 65536
		TIM6,			Any integer
	Basic		16-bit	Up	between 1	Yes	0	No	42	84
		TIM7
					and 65536

Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.

Their 4 independent channels can be used for:

●Input capture

●Output compare

●PWM generation (edgeor center-aligned modes)

●One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0- 100%).

The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

TIM1 and TIM8 support independent DMA request generation.

Doc ID 022152 Rev 3

29/180

Description	STM32F405xx, STM32F407xx

General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 3 for differences).

●TIM2, TIM3, TIM4, TIM5

The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages.

The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.

●TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base.

TIM6 and TIM7 support independent DMA request generation.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardwareor software-configurable through the option bytes.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

30/180

Doc ID 022152 Rev 3