ST SPC560B40L5, SPC560B50L5, SPC560B40L3, SPC560C40L3, SPC560B50L3 User Manual

SPC560B40x, SPC560B50x

SPC560C40x, SPC560C50x

32-bit MCU family built on the Power Architecture® for automotive body electronics applications

Features

■High-performance 64 MHz e200z0h CPU

–32-bit Power Architecture® technology

–Up to 60 DMIPs operation

–Variable length encoding (VLE)

■Memory

–Up to 512 Kbytes Code Flash, with ECC

–64 Kbytes Data Flash, with ECC

–Up to 48 Kbytes SRAM, with ECC

–8-entry memory protection unit (MPU)

■Interrupts

–16 priority levels

–Non-maskable interrupt (NMI)

–Up to 34 ext. int. including 18 wakeup lines

■GPIO: LQFP64/45, LQFP100/75, LQFP144/123

■Timer units

–6-channel 32-bit periodic interrupt timers

–4-channel 32-bit system timer module

–System watchdog timer

–Real-time clock timer

■16-bit counter time-triggered I/Os

–Up to 56 channels with PWM/MC/IC/OC

–ADC diagnostic via CTU

■Communications interface

–Up to 6 FlexCAN interfaces (2.0B active) with 64-message objects each

–Up to 4 LINFlex/UART

–3 DSPI / I2C

Table 1. Device summary

LQFP100 (14 x 14 x 1.4 mm)

LQFP64 (10 x 10 x 1.4 mm)

LQFP144 (20 x 20 x 1.4 mm)

■10-bit A/D converter with up to 36 channels

–Up to 64 channels via external multiplexing

–Individual conversion registers

–Cross triggering unit

■Dedicated diagnostic module for lighting

–Advanced PWM generation

–Time-triggered diagnostic

–PWM-synchronized ADC measurements

■Clock generation

–4 to 16 MHz fast external crystal oscillator

–32 KHz slow external crystal oscillator

–16 MHz fast internal RC oscillator

–128 kHz slow internal RC oscillator

–Software-controlled FMPLL

–Clock monitoring unit

■Exhaustive debugging capability

–Nexus1 on all devices

–Nexus2+ available on emulation package

■Low power capabilities

–Ultra-low power standby with RTC, SRAM and CAN monitoring

–Fast wakeup schemes

■Operating temp. range up to -40 to 125 °C

■Single 5 V or 3.3 V supply

	Package		Part number
		256 KB code Flash memory		512 KB code Flash memory
	LQFP144	SPC560B40L5	—	SPC560B50L5	—
	LQFP100	SPC560B40L3	SPC560C40L3	SPC560B50L3	SPC560C50L3
	LQFP64(1)	SPC560B40L1	SPC560C40L1	SPC560B50L1	SPC560C50L1

1. All LQFP64 information is indicative and must be confirmed during silicon validation.

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Contents	SPC560B40x/50x, SPC560C40x/50x

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
	1.1	Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	1.2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
2	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
3	Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . .		14
	3.1	Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	3.2	Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.3	Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	3.4	Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	3.5	System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	3.6	Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.7	Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
	4.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
	4.2	Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
	4.3	NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44

4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 44 4.3.3 NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 44

4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.5 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.6.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.7	I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		50
	4.7.1	I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
	4.7.2	I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
	4.7.3	I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
	4.7.4	Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	54
	4.7.5	I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	54

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4.8 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.9 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 63

4.9.1	Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . .	63
4.9.2	Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . .	68

4.10 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.11 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.11.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.11.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.12 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . .		73
4.12.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . .		73
4.12.2	Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .	74
4.12.3	Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . .	74

4.13Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 75

4.14	Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . .		78
4.15	FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		80
4.16	Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . .		81
4.17	Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . .		82
4.18	ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		83
	4.18.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
	4.18.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . .		83
	4.18.3	ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	88

4.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.19.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.19.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.19.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.19.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		101
	5.1	ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 101
	5.2	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	101

5.2.1 LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.2.2 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.2.3 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.2.4 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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6	Ordering information . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . 108
Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . 109
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . 110

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SPC560B40x/50x, SPC560C40x/50x	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. SPC560B40x/50x and SPC560C40x/50x device comparison . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary . . . . . . . . . . . . . . . . . . . . 12 Table 4. Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5. System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 9. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 10. OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 11. WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 13. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 14. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 15. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 16. I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 17. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 18. SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 19. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 52 Table 20. FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 21. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 22. I/O supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 23. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 24. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 25. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 26. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 27. Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 28. Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 29. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 30. Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 31. Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 32. Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 33. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 34. EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 36. Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 37. Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 77 Table 39. Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 80 Table 41. FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 81 Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 82 Table 44. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 45. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 46. On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 47. DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 48. Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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List of tables	SPC560B40x/50x, SPC560C40x/50x

Table 49. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 50. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 51. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 52. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 53. LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 54. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 55. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

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SPC560B40x/50x, SPC560C40x/50x	List of figures

List of figures

Figure 1. SPC560B40x/50x and SPC560C40x/50x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2. LQFP 64-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. LQFP 100-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 4. LQFP 144-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. LBGA208 confguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 7. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 8. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 9. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 10. VDD and VDD_BV maximum slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 11. VDD and VDD_BV supply constraints during STANDBY mode exit. . . . . . . . . . . . . . . . . . 65 Figure 12. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 13. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 14. Fast external crystal oscillator (4 to 16 MHz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 15. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 16. Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 17. Slow external crystal oscillator (32 kHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 18. ADC characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 19. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 20. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 21. Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 22. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 23. DSPI classic SPI timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 24. DSPI classic SPI timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 25. DSPI classic SPI timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 26. DSPI classic SPI timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 27. DSPI modified transfer format timing – master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 28. DSPI modified transfer format timing – master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 29. DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 30. DSPI modified transfer format timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 31. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 32. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 33. Timing diagram – JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 34. LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 35. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 36. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 37. LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 38. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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Introduction	SPC560B40x/50x, SPC560C40x/50x

1 Introduction

1.1Document overview

This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet.

1.2Description

The SPC560B40x/50x and SPC560C40x/50x is a family of next generation microcontrollers built on the Power Architecture embedded category.

The SPC560B40x/50x and SPC560C40x/50x family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.

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Table 2.

SPC560B40x/50x and SPC560C40x/50x device comparison(1)

Device

Feature

SPC560B

SPC560B

SPC560B

SPC560C

SPC560C

SPC560B

SPC560B

SPC560B

SPC560C

SPC560C

SPC560B

40L1

40L3

40L5

40L1

40L3

50L1

50L3

50L5

50L1

50L3

50B2

CPU

e200z0h

Execution

Static – up to 64 MHz

speed(2)

Code Flash

256 KB

512 KB

Data Flash

64 KB (4 × 16 KB)

RAM

24 KB

32 KB

32 KB

48 KB

MPU

8-entry

IDDoc

ADC (10-bit)

12 ch

28 ch

36 ch

8 ch

28 ch

12 ch

28 ch

36 ch

8 ch

28 ch

36 ch

14619

CTU

Yes

Total timer I/O(3)

12 ch,

28 ch,

56 ch,

12 ch,

28 ch,

12 ch,

28 ch,

56 ch,

12 ch,

28 ch,

56 ch,

9Rev

eMIOS

16-bit

16-bit

16-bit

16-bit

16-bit

16-bit

16-bit

16-bit

16-bit

16-bit

16-bit

– PWM + MC +

2 ch

5 ch

10 ch

2 ch

5 ch

2 ch

5 ch

10 ch

2 ch

5 ch

10 ch

IC/OC(4)

– PWM +

10 ch

20 ch

40 ch

10 ch

20 ch

10 ch

20 ch

40 ch

10 ch

20 ch

40 ch

IC/OC(4)

– IC/OC(4)

—

3 ch

6 ch

—

3 ch

—

3 ch

6 ch

—

3 ch

6 ch

SCI (LINFlex)

3(5)

4

SPI (DSPI)

2

3

2

3

2

3

2

3

CAN (FlexCAN)

2(6)

5

6

3(7)

5

6

I2C

1

32 kHz oscillator

Yes

GPIO(8)

45

79

123

45

79

45

79

123

45

79

123

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SPC560C40x/50x SPC560B40x/50x,

Introduction

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Table 2.

SPC560B40x/50x and SPC560C40x/50x device comparison(1) (continued)

Device

Feature

SPC560B

SPC560B

SPC560B

SPC560C

SPC560C

SPC560B

SPC560B

SPC560B

SPC560C

SPC560C

SPC560B

40L1

40L3

40L5

40L1

40L3

50L1

50L3

50L5

50L1

50L3

50B2

Debug

JTAG

Nexus2+

Package

LQFP64(9)

LQFP100

LQFP144

LQFP64(9)

LQFP100

LQFP64(9)

LQFP100

LQFP144

LQFP64(9)

LQFP100

LBGA208

(10)

1.Feature set dependent on selected peripheral multiplexing—table shows example implementation

2.Based on 125 °C ambient operating temperature

3.See the eMIOS section of the device reference manual for information on the channel configuration and functions.

4.IC – Input Capture; OC – Output Compare; PWM – Pulse Width Modulation; MC – Modulus counter

5.SCI0, SCI1 and SCI2 are available. SCI3 is not available.

6.CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available.

7.CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available.

8.I/O count based on multiplexing with peripherals

9.All LQFP64 information is indicative and must be confirmed during silicon validation.

10.LBGA208 available only as development package for Nexus2+

Introduction

SPC560C40x/50x SPC560B40x/50x,

SPC560B40x/50x, SPC560C40x/50x	Block diagram

2 Block diagram

Figure 1 shows a top-level block diagram of the SPC560B40x/50x and SPC560C40x/50x device series.

Figure 1. SPC560B40x/50x and SPC560C40x/50x block diagram

		JTAG
JTAG port
Nexus port			e200z0h
	Nexus
		NMI	Nexus 2+
		SIUL
	Voltage
	regulator
NMI		Interrupt requests
		from peripheral
		blocks

INTC

Clocks

CMU

FMPLL

RTC

STM

SWT

ECSM

PIT

SRAM 48 KB

	Instructions			Switch
							SRAM
	(Master)
							controller
				Crossbar
	(Master)				MPU
								(Slave)
	Data			64-bit 2 x 3

MPU registers

MC_RGM MC_CGM MC_ME MC_PCU

Peripheral bridge

Code Flash	Data Flash
512 KB	64 KB

Flash controller

(Slave)

(Slave)

BAM SSCM

	SIUL	36 Ch.	CTU	2 x	4 x		3 x	I2C		6 x
	Reset control	ADC		eMIOS	LINFlex		DSPI			FlexCAN
Interrupt
	External
request
	interrupt
	request
	IMUX									WKPU
	GPIO and
	pad control
										Interrupt
										request with
	I/O		. . .		. . .	. . .		. . .	. . .	wakeup
										functionality
	Legend:				MC_CGM	Clock Generation Module

ADC	Analog-to-Digital Converter
BAM	Boot Assist Module	MC_ME	Mode Entry Module
FlexCAN	Controller Area Network	MC_PCU	Power Control Unit
CMU	Clock Monitor Unit	MC_RGM	Reset Generation Module
CTU	Cross Triggering Unit	MPU	Memory Protection Unit
DSPI	Deserial Serial Peripheral Interface	Nexus	Nexus Development Interface (NDI) Level
eMIOS	Enhanced Modular Input Output System	NMI	Non-Maskable Interrupt
FMPLL	Frequency-Modulated Phase-Locked Loop	PIT	Periodic Interrupt Timer
I2C	Inter-integrated Circuit Bus	RTC	Real-Time Clock
IMUX	Internal Multiplexer	SIUL	System Integration Unit Lite
INTC	Interrupt Controller	SRAM	Static Random-Access Memory
JTAG	JTAG controller	SSCM	System Status Configuration Module
LINFlex	Serial Communication Interface (LIN support)	STM	System Timer Module
ECSM	Error Correction Status Module	SWT	Software Watchdog Timer
		WKPU	Wakeup Unit

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Block diagram	SPC560B40x/50x, SPC560C40x/50x
Table 3 summarizes the functions of all blocks present in the SPC560B40x/50x and
SPC560C40x/50x series of microcontrollers. Please note that the presence and number of
blocks vary by device and package.

	Table 3.	SPC560B40x/50x and SPC560C40x/50x series block summary
		Block	Function
	Analog-to-digital converter (ADC)		Multi-channel, 10-bit analog-to-digital converter
	Boot assist module (BAM)		A block of read-only memory containing VLE code which is executed according
			to the boot mode of the device
	Clock monitor unit (CMU)		Monitors clock source (internal and external) integrity
	Cross triggering unit (CTU)		Enables synchronization of ADC conversions with a timer event from the eMIOS
			or from the PIT
	Deserial serial peripheral		Provides a synchronous serial interface for communication with external
	interface (DSPI)		devices
			Provides a myriad of miscellaneous control functions for the device including
	Error Correction Status Module		program-visible information about configuration and revision levels, a reset
	(ECSM)		status register, wakeup control for exiting sleep modes, and optional features
			such as information on memory errors reported by error-correcting codes
	Enhanced Direct Memory Access		Performs complex data transfers with minimal intervention from a host
	(eDMA)		processor via “n” programmable channels.
	Enhanced modular input output		Provides the functionality to generate or measure events
	system (eMIOS)
	Flash memory		Provides non-volatile storage for program code, constants and variables
	FlexCAN (controller area		Supports the standard CAN communications protocol
	network)
	Frequency-modulated phase-		Generates high-speed system clocks and supports programmable frequency
	locked loop (FMPLL)		modulation
	Internal multiplexer (IMUX) SIU		Allows flexible mapping of peripheral interface on the different pins of the device
	subblock
	Inter-integrated circuit (I2C™) bus		A two wire bidirectional serial bus that provides a simple and efficient method of
			data exchange between devices
	Interrupt controller (INTC)		Provides priority-based preemptive scheduling of interrupt requests
	JTAG controller		Provides the means to test chip functionality and connectivity while remaining
			transparent to system logic when not in test mode
	LINFlex controller		Manages a high number of LIN (Local Interconnect Network protocol)
			messages efficiently with a minimum of CPU load
	Clock generation module		Provides logic and control required for the generation of system and peripheral
	(MC_CGM)		clocks
			Provides a mechanism for controlling the device operational mode and mode
	Mode entry module (MC_ME)		transition sequences in all functional states; also manages the power control
			unit, reset generation module and clock generation module, and holds the
			configuration, control and status registers accessible for applications

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	SPC560B40x/50x, SPC560C40x/50x			Block diagram
	Table 3.	SPC560B40x/50x and SPC560C40x/50x series block summary (continued)
		Block	Function
			Reduces the overall power consumption by disconnecting parts of the device
	Power control unit (MC_PCU)		from the power supply via a power switching device; device components are
			grouped into sections called “power domains” which are controlled by the PCU
	Reset generation module		Centralizes reset sources and manages the device reset sequence of the
	(MC_RGM)		device
	Memory protection unit (MPU)		Provides hardware access control for all memory references generated in a
			device
	Nexus development interface		Provides real-time development support capabilities in compliance with the
	(NDI)		IEEE-ISTO 5001-2003 standard
	Periodic interrupt timer (PIT)		Produces periodic interrupts and triggers
			A free running counter used for time keeping applications, the RTC can be
	Real-time counter (RTC)		configured to generate an interrupt at a predefined interval independent of the
			mode of operation (run mode or low-power mode)
			Provides control over all the electrical pad controls and up 32 ports with 16 bits
	System integration unit (SIU)		of bidirectional, general-purpose input and output signals and supports up to 32
			external interrupts with trigger event configuration
	Static random-access memory		Provides storage for program code, constants, and variables
	(SRAM)
	System status configuration		Provides system configuration and status data (such as memory size and
			status, device mode and security status), device identification data, debug
	module (SSCM)
			status port enable and selection, and bus and peripheral abort enable/disable
	System timer module (STM)		Provides a set of output compare events to support AUTOSAR and operating
			system tasks
	System watchdog timer (SWT)		Provides protection from runaway code
			The wakeup unit supports up to 18 external sources that can generate
	Wakeup unit (WKPU)		interrupts or wakeup events, of which 1 can cause non-maskable interrupt
			requests or wakeup events.
			Supports simultaneous connections between two master ports and three slave
	Crossbar (XBAR) switch		ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
			width.

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Package pinouts and signal descriptions	SPC560B40x/50x, SPC560C40x/50x

3 Package pinouts and signal descriptions

3.1Package pinouts

The available LQFP pinouts and the LBGA208 ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual (RM0017).

Figure 2. LQFP 64-pin configuration(a)

		PB[2]					PC[8]				PC[4] PC[5] PH[9] PC[0] VSS LV VDD LV VDD HV VSS HV PC[1] PH[10] PA[6] PA[5] PC[2]																																																			PC[3]
		64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PB[3]		1																																																												48							PA[11]
PC[9]		2																																																												47							PA[10]
PA[2]		3																																																												46							PA[9]
PA[1]		4																																																												45							PA[8]
PA[0]		5																																																												44							PA[7]
VSS_HV		6																																																												43							PA[3]
VDD_HV		7																																																												42							PB[15]
VSS_HV		8									LQFP64 Top view																																																			41							PB[14]
RESET		9																																																												40							PB[13]
VSS_LV		10																																																												39							PB[12]
VDD_LV		11																																																												38							PB[11]
VDD_BV		12																																																												37							PB[7]
PC[10]		13																																																												36							PB[6]
PB[0]		14																																																												35							PB[5]
PB[1]		15																																																												34							VDD_HV_ADC
PC[6]		16																																																												33							VSS_HV_ADC
		17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
		PC[7]					PA[15]				PA[14] PA[4] PA[13] PA[12] VDD LV VSS LV XTAL VSS HV EXTAL VDD HV PB[9] PB[8] PB[10]																																																			PB[4]

a. All LQFP64 information is indicative and must be confirmed during silicon validation.

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SPC560B40x/50x, SPC560C40x/50x	Package pinouts and signal descriptions

Figure 3. LQFP 100-pin configuration

						PB[2]			PC[8]				PC[13]				PC[12]				PE[7]				PE[6]				PE[5]				PE[4]				PC[4]				PC[5]				PE[3]				PE[2]				PH[9]				PC[0]				VSS LV					VDD LV			VDD HV				VSS HV				PC[1]				PH[10]				PA[6]				PA[5]				PC[2]				PC[3]				PE[12]
					100				99				98				97				96				95				94				93				92				91				90				89				88				87				86					85			84				83				82				81				80				79				78				77				76
	PB[3]				1																																																																																																75							PA[11]
	PC[9]				2																																																																																																74							PA[10]
	PC[14]				3																																																																																																73							PA[9]
	PC[15]				4																																																																																																72							PA[8]
	PA[2]				5																																																																																																71							PA[7]
	PE[0]				6																																																																																																70							VDD_HV
	PA[1]				7																																																																																																69							VSS_HV
	PE[1]				8																																																																																																68							PA[3]
	PE[8]				9																																																																																																67							PB[15]
	PE[9]				10																																																																																																66							PD[15]
	PE[10]				11																																																																																																65							PB[14]
	PA[0]				12																												LQFP100																																																																				64							PD[14]
	PE[11]				13																																																																																																63							PB[13]
VSS_HV					14																																																																																																62							PD[13]
VDD_HV					15																																						Top view																																																										61							PB[12]
VSS_HV					16																																																																																																60							PD[12]
	RESET				17																																																																																																59							PB[11]
VSS_LV					18																																																																																																58							PD[11]
VDD_LV					19																																																																																																57							PD[10]
VDD_BV					20																																																																																																56							PD[9]
	PC[11]				21																																																																																																55							PB[7]
	PC[10]				22																																																																																																54							PB[6]
	PB[0]				23																																																																																																53							PB[5]
	PB[1]				24																																																																																																52							VDD_HV_ADC
	PC[6]				25																																																																																																51							VSS_HV_ADC
					26				27				28				29				30				31				32				33				34				35				36				37				38				39				40					41			42				43				44				45				46				47				48				49				50
						PC[7]			PA[15]				PA[14]				PA[4]				PA[13]				PA[12]				VDD LV				VSS LV				XTAL				VSS HV				EXTAL				VDD HV				PB[9]				PB[8]				PB[10]					PD[0]			PD[1]				PD[2]				PD[3]				PD[4]				PD[5]				PD[6]				PD[7]				PD[8]				PB[4]

Note:

Availability of port pin alternate functions depends on product selection.

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Package pinouts and signal descriptions	SPC560B40x/50x, SPC560C40x/50x

Figure 4. LQFP 144-pin configuration

PB[3] 1

PC[9] 2

PC[14] 3 PC[15] 4 PG[5] 5 PG[4] 6 PG[3] 7 PG[2] 8 PA[2] 9

PE[0] 10 PA[1] 11 PE[1] 12 PE[8] 13 PE[9] 14

PE[10] 15 PA[0] 16 PE[11] 17 VSS_HV 18 VDD_HV 19 VSS_HV 20 RESET 21 VSS_LV 22 VDD_LV 23 VDD_BV 24 PG[9] 25 PG[8] 26 PC[11] 27 PC[10] 28 PG[7] 29 PG[6] 30 PB[0] 31 PB[1] 32 PF[9] 33 PF[8] 34 PF[12] 35 PC[6] 36

PB[2]			PC[8]				PC[13]				PC[12]				PE[7]				PE[6]				PH[8]				PH[7]				PH[6]				PH[5]				PH[4]				PE[5]				PE[4]				PC[4]				PC[5]				PE[3]				PE[2]				PH[9]				PC[0]				VSS LV				VDD LV				VDD HV				VSS HV				PC[1]				PH[10]				PA[6]				PA[5]				PC[2]				PC[3]
144			143				142				141				140				139				138				137				136				135				134				133				132				131				130				129				128				127				126				125				124				123				122				121				120				119				118				117				116

LQFP144

Top view

37		38		39		40		41		42		43		44		45		46		47		48		49		50		51		52		53		54		55		56		57		58		59		60		61		62		63		64		65
PC[7]			PF[10]		PF[11]		PA[15]		PF[13]		PA[14]		PA[4]		PA[13]		PA[12]		VDD LV		VSS LV		XTAL		VSS HV		EXTAL		VDD HV		PB[9]		PB[8]		PB[10]		PF[0]		PF[1]		PF[2]		PF[3]		PF[4]		PF[5]		PF[6]		PF[7]		PD[0]		PD[1]	PD[2]

PG[11]			PG[10]				PE[15]
115			114				113

66		67		68
PD[3]			PD[4]	PD[5]

PE[14]			PG[15]				PG[14]				PE[12]
112			111				110				109

69		70	71	72
PD[6]		PD[7]	PD[8]	PB[4]

108 PA[11]

107 PA[10]

106 PA[9]

105 PA[8]

104 PA[7]

103 PE[13]

102 PF[14]

101 PF[15]

100 VDD_HV

99 VSS_HV

98 PG[0]

97 PG[1]

96 PH[3]

95 PH[2]

94 PH[1]

93 PH[0]

92 PG[12]

91 PG[13]

90 PA[3]

89 PB[15]

88 PD[15]

87 PB[14]

86 PD[14]

85 PB[13]

84 PD[13]

83 PB[12]

82 PD[12]

81 PB[11]

80 PD[11]

79 PD[10]

78 PD[9]

77 PB[7]

76 PB[6]

75 PB[5]

74 VDD_HV_ADC

73 VSS_HV_ADC

Note:

Availability of port pin alternate functions depends on product selection.

16/117

Doc ID 14619 Rev 9

SPC560B40x/50x, SPC560C40x/50x

Package pinouts and signal descriptions

Figure 5.

LBGA208 confguration

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

PC[8]

PC[13]

NC

NC

PH[8]

PH[4]

PC[5]

PC[0]

NC

NC

PC[2]

NC

PE[15]

NC

NC

NC

A

B

PC[9]

PB[2]

NC

PC[12]

PE[6]

PH[5]

PC[4]

PH[9]

PH[10]

NC

PC[3]

PG[11]

PG[15]

PG[14]

PA[11]

PA[10]

B

C

PC[14]

VDD_H

PB[3]

PE[7]

PH[7]

PE[5]

PE[3]

VSS_L

PC[1]

NC

PA[5]

NC

PE[14]

PE[12]

PA[9]

PA[8]

C

V

V

D

NC

NC

PC[15]

NC

PH[6]

PE[4]

PE[2]

VDD_L

VDD_H

NC

PA[6]

NC

PG[10]

PF[14]

PE[13]

PA[7]

D

V

V

E

PG[4]

PG[5]

PG[3]

PG[2]

PG[1]

PG[0]

PF[15]

VDD_H

E

V

F

PE[0]

PA[2]

PA[1]

PE[1]

PH[0]

PH[1]

PH[3]

PH[2]

F

G

PE[9]

PE[8]

PE[10]

PA[0]

VSS_H

VSS_H

VSS_H

VSS_H

VDD_H

NC

NC

MSEO

G

V

V

V

V

V

H

VSS_H

PE[11]

VDD_H

NC

VSS_H

VSS_H

VSS_H

VSS_H

MDO3

MDO2

MDO0

MDO1

H

V

V

V

V

V

V

J

RESET

VSS_L

NC

NC

VSS_H

VSS_H

VSS_H

VSS_H

NC

NC

NC

NC

J

V

V

V

V

V

K

EVTI

NC

VDD_B

VDD_L

VSS_H

VSS_H

VSS_H

VSS_H

NC

PG[12]

PA[3]

PG[13]

K

V

V

V

V

V

V

L

PG[9]

PG[8]

NC

EVTO

PB[15]

PD[15]

PD[14]

PB[14]

L

M

PG[7]

PG[6]

PC[10]

PC[11]

PB[13]

PD[13]

PD[12]

PB[12]

M

N

PB[1]

PF[9]

PB[0]

NC

NC

PA[4]

VSS_L

EXTAL

VDD_H

PF[0]

PF[4]

NC

PB[11]

PD[10]

PD[9]

PD[11]

N

V

V

P

PF[8]

NC

PC[7]

NC

NC

PA[14]

VDD_L

XTAL

PB[10]

PF[1]

PF[5]

PD[0]

PD[3]

VDD_H

PB[6]

PB[7]

P

V

V_ADC

VDD_H

OSC32

VSS_H

R

PF[12]

PC[6]

PF[10]

PF[11]

PA[15]

PA[13]

NC

K_XTA

PF[3]

PF[7]

PD[2]

PD[4]

PD[7]

PB[5]

R

V

V_ADC

L

OSC32

T

NC

NC

NC

MCKO

NC

PF[13]

PA[12]

NC

K_EXT

PF[2]

PF[6]

PD[1]

PD[5]

PD[6]

PD[8]

PB[4]

T

AL

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

= Not connected

Note: LBGA208 available only as development package for Nexus 2+.

NC

3.2Pad configuration during reset phases

All pads have a fixed configuration under reset.

During the power-up phase, all pads are forced to tristate.

Doc ID 14619 Rev 9

17/117

Package pinouts and signal descriptions	SPC560B40x/50x, SPC560C40x/50x

After power-up phase, all pads are forced to tristate with the following exceptions:

●PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.

●PA[8] (ABS[0]) is pull-up.

●RESET pad is driven low. This is pull-up only after PHASE2 reset completion.

●JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate.

●Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).

●Main oscillator pads (EXTAL, XTAL) are tristate.

●Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.

3.3Voltage supply pins

Voltage supply pins are used to provide power to the device. Three dedicated

VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization.

	Table 4.	Voltage supply pin descriptions
	Port pin		Function		Pin number
				LQFP64	LQFP100	LQFP144	LBGA208(1)
	VDD_HV		Digital supply voltage	7, 28, 56	15, 37, 70,	19, 51, 100,	C2, D9, E16,
					84	123	G13, H3,
							N9, R5
							G7, G8, G9,
							G10, H1,
	VSS_HV		Digital ground	6, 8, 26, 55	14, 16, 35,	18, 20, 49,	H7, H8, H9,
					69, 83	99, 122	H10, J7, J8,
							J9, J10, K7,
							K8, K9, K10
			1.2V decoupling pins. Decoupling
	VDD_LV		capacitor must be connected between	11, 23, 57	19, 32, 85	23, 46, 124	D8, K4, P7
			these pins and the nearest VSS_LV
			pin.(2)
			1.2V decoupling pins. Decoupling
	VSS_LV		capacitor must be connected between	10, 24, 58	18, 33, 86	22, 47, 125	C8, J2, N7
			these pins and the nearest VDD_LV
			pin.(2)
	VDD_BV		Internal regulator supply voltage	12	20	24	K3
	VSS_HV_ADC		Reference ground and analog ground	33	51	73	R15
			for the ADC
	VDD_HV_ADC		Reference voltage and analog supply	34	52	74	P14
			for the ADC

1.LBGA208 available only as development package for Nexus2+.

2.A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see the recommended operating conditions in the device datasheet for details).

18/117

Doc ID 14619 Rev 9

SPC560B40x/50x, SPC560C40x/50x	Package pinouts and signal descriptions

3.4Pad types

In the device the following types of pads are available for system pins and functional port pins:

S = Slow(b)

M = Medium (b)(c) F = Fast (b)(c)

I = Input only with analog feature(b)

J = Input/Output (‘S’ pad) with analog feature

X = Oscillator

3.5System pins

		The system pins are listed in Table 5.
Table 5.		System pin descriptions
Systempin			directionI/O	Padtype	configurationRESET	LQFP64		LQFP100	LQFP144		LBGA208
							Pin number
		Function									(1)
		Bidirectional reset with Schmitt-Trigger characteristics			Input, weak
RESET			I/O	M	pull-up only	9		17	21		J1
		and noise filter.
					after PHASE2
		Analog output of the oscillator amplifier circuit, when the
EXTAL		oscillator is not in bypass mode.	I/O	X	Tristate	27		36	50		N8
		Analog input for the clock generator when the oscillator
		is in bypass mode.(2)
XTAL		Analog input of the oscillator amplifier circuit. Needs to	I	X	Tristate	25		34	48		P8
		be grounded if oscillator is used in bypass mode.(2)

1.LBGA208 available only as development package for Nexus2+.

2.See the relevant section of the datasheet .

b.See the I/O pad electrical characteristics in the device datasheet for details.

c.All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PCR.SRC in section Pad Configuration Registers (PCR0–PCR122) in the device reference manual).

Doc ID 14619 Rev 9

19/117

20/117

9 Rev 14619 ID Doc

3.6Functional ports

The functional port pins are listed in Table 6.

Table 6.	Functional port pin descriptions
		(1)		Peripheral	(2)		RESET configuration		Pin number
					I/Odirection						(3)
Portpin	PCR	Alternate function	Function			Padtype		LQFP64	LQFP100	LQFP144	LBGA208
PA[0]	PCR[0]	AF0	GPIO[0]	SIUL	I/O	M	Tristate	5	12	16	G4
		AF1	E0UC[0]	eMIOS_0	I/O
		AF2	CLKOUT	CGL	O
		AF3	—	—	—
		—	WKPU[19](4)	WKPU	I
PA[1]	PCR[1]	AF0	GPIO[1]	SIUL	I/O	S	Tristate	4	7	11	F3
		AF1	E0UC[1]	eMIOS_0	I/O
		AF2	—	—	—
		AF3	—	—	—
		—	NMI(5)	WKPU	I
		—	WKPU[2](4)	WKPU	I
PA[2]	PCR[2]	AF0	GPIO[2]	SIUL	I/O	S	Tristate	3	5	9	F2
		AF1	E0UC[2]	eMIOS_0	I/O
		AF2	—	—	—
		AF3	—	—	—
		—	WKPU[3](4)	WKPU	I
PA[3]	PCR[3]	AF0	GPIO[3]	SIUL	I/O	S	Tristate	43	68	90	K15
		AF1	E0UC[3]	eMIOS_0	I/O
		AF2	—	—	—
		AF3	—	—	—
		—	EIRQ[0]	SIUL	I
PA[4]	PCR[4]	AF0	GPIO[4]	SIUL	I/O	S	Tristate	20	29	43	N6
		AF1	E0UC[4]	eMIOS_0	I/O
		AF2	—	—	—
		AF3	—	—	—
		—	WKPU[9](4)	WKPU	I

descriptions signal and pinouts Package

SPC560C40x/50x SPC560B40x/50x,

Table 6.

Functional port pin descriptions (continued)

(1)

Peripheral

(2)

RESET configuration

Pin number

I/Odirection

(3)

Portpin

PCR

Alternate function

Function

Padtype

LQFP64

LQFP100

LQFP144

LBGA208

PA[5]

PCR[5]

AF0

GPIO[5]

SIUL

I/O

M

Tristate

51

79

118

C11

AF1

E0UC[5]

eMIOS_0

I/O

AF2

—

—

—

AF3

—

—

—

PA[6]

PCR[6]

AF0

GPIO[6]

SIUL

I/O

S

Tristate

52

80

119

D11

AF1

E0UC[6]

eMIOS_0

I/O

AF2

—

—

—

AF3

—

—

—

Doc

—

EIRQ[1]

SIUL

I

PA[7]

PCR[7]

AF0

GPIO[7]

SIUL

I/O

S

Tristate

44

71

104

D16

ID

AF1

E0UC[7]

eMIOS_0

I/O

14619

AF2

LIN3TX

LINFlex_3

O

AF3

—

—

—

Rev

—

EIRQ[2]

SIUL

I

PA[8]

PCR[8]

AF0

GPIO[8]

SIUL

I/O

S

Input, weak

45

72

105

C16

9

AF1

E0UC[8]

eMIOS_0

I/O

pull-up

AF2

—

—

—

AF3

—

—

—

—

EIRQ[3]

SIUL

I

N/A(6)

ABS[0]

BAM

I

—

LIN3RX

LINFlex_3

I

PA[9]

PCR[9]

AF0

GPIO[9]

SIUL

I/O

S

Pull-down

46

73

106

C15

AF1

E0UC[9]

eMIOS_0

I/O

AF2

—

—

—

AF3

—

—

—

N/A(6)

FAB

BAM

I

PA[10]

PCR[10]

AF0

GPIO[10]

SIUL

I/O

S

Tristate

47

74

107

B16

AF1

E0UC[10]

eMIOS_0

I/O

21/117

AF2

SDA

I2C_0

I/O

AF3

—

—

—

SPC560C40x/50x SPC560B40x/50x,

descriptions signal and pinouts Package

22/117

9 Rev 14619 ID Doc

Table 6.

Functional port pin descriptions (continued)

(1)

Peripheral

(2)

RESET configuration

Pin number

I/Odirection

(3)

Portpin

PCR

Alternate function

Function

Padtype

LQFP64

LQFP100

LQFP144

LBGA208

PA[11]

PCR[11]

AF0

GPIO[11]

SIUL

I/O

S

Tristate

48

75

108

B15

AF1

E0UC[11]

eMIOS_0

I/O

AF2

SCL

I2C_0

I/O

AF3

—

—

—

PA[12]

PCR[12]

AF0

GPIO[12]

SIUL

I/O

S

Tristate

22

31

45

T7

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

SIN_0

DSPI0

I

PA[13]

PCR[13]

AF0

GPIO[13]

SIUL

I/O

M

Tristate

21

30

44

R7

AF1

SOUT_0

DSPI_0

O

AF2

—

—

—

AF3

—

—

—

PA[14]

PCR[14]

AF0

GPIO[14]

SIUL

I/O

M

Tristate

19

28

42

P6

AF1

SCK_0

DSPI_0

I/O

AF2

CS0_0

DSPI_0

I/O

AF3

—

—

—

—

EIRQ[4]

SIUL

I

PA[15]

PCR[15]

AF0

GPIO[15]

SIUL

I/O

M

Tristate

18

27

40

R6

AF1

CS0_0

DSPI_0

I/O

AF2

SCK_0

DSPI_0

I/O

AF3

—

—

—

—

WKPU[10](4)

WKPU

I

PB[0]

PCR[16]

AF0

GPIO[16]

SIUL

I/O

M

Tristate

14

23

31

N3

AF1

CAN0TX

FlexCAN_0

O

AF2

—

—

—

AF3

—

—

—

descriptions signal and pinouts Package

SPC560C40x/50x SPC560B40x/50x,

Table 6.

Functional port pin descriptions (continued)

(1)

Peripheral

(2)

RESET configuration

Pin number

I/Odirection

(3)

Portpin

PCR

Alternate function

Function

Padtype

LQFP64

LQFP100

LQFP144

LBGA208

PB[1]

PCR[17]

AF0

GPIO[17]

SIUL

I/O

S

Tristate

15

24

32

N1

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

WKPU[4](4)

WKPU

I

—

CAN0RX

FlexCAN_0

I

PB[2]

PCR[18]

AF0

GPIO[18]

SIUL

I/O

M

Tristate

64

100

144

B2

AF1

LIN0TX

LINFlex_0

O

ID Doc

AF2

SDA

I2C_0

I/O

AF3

—

—

—

PB[3]

PCR[19]

AF0

GPIO[19]

SIUL

I/O

S

Tristate

1

1

1

C3

14619

AF1

—

—

—

AF2

SCL

I2C_0

I/O

Rev

AF3

—

—

—

—

WKPU[11](4)

WKPU

I

9

—

LIN0RX

LINFlex_0

I

PB[4]

PCR[20]

AF0

GPIO[20]

SIUL

I

I

Tristate

32

50

72

T16

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

GPI[0]

ADC

I

PB[5]

PCR[21]

AF0

GPIO[21]

SIUL

I

I

Tristate

35

53

75

R16

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

GPI[1]

ADC

I

PB[6]

PCR[22]

AF0

GPIO[22]

SIUL

I

I

Tristate

36

54

76

P15

AF1

—

—

—

23/117

AF2

—

—

—

AF3

—

—

—

—

GPI[2]

ADC

I

SPC560C40x/50x SPC560B40x/50x,

descriptions signal and pinouts Package

24/117

9 Rev 14619 ID Doc

Table 6.

Functional port pin descriptions (continued)

(1)

Peripheral

(2)

RESET configuration

Pin number

I/Odirection

(3)

Portpin

PCR

Alternate function

Function

Padtype

LQFP64

LQFP100

LQFP144

LBGA208

PB[7]

PCR[23]

AF0

GPIO[23]

SIUL

I

I

Tristate

37

55

77

P16

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

GPI[3]

ADC

I

PB[8]

PCR[24]

AF0

GPIO[24]

SIUL

I

I

Tristate

30

39

53

R9

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

ANS[0]

ADC

I

—

OSC32K_XTAL(7)

SXOSC

I/O

PB[9]

PCR[25]

AF0

GPIO[25]

SIUL

I

I

Tristate

29

38

52

T9

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

ANS[1]

ADC

I

—

OSC32K_EXTAL(7)

SXOSC

I/O

PB[10]

PCR[26]

AF0

GPIO[26]

SIUL

I/O

J

Tristate

31

40

54

P9

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

ANS[2]

ADC

I

—

WKPU[8](4)

WKPU

I

PB[11](8)

PCR[27]

AF0

GPIO[27]

SIUL

I/O

J

Tristate

38

59

81

N13

AF1

E0UC[3]

eMIOS_0

I/O

AF2

—

—

—

AF3

CS0_0

DSPI_0

I/O

—

ANS[3]

ADC

I

descriptions signal and pinouts Package

SPC560C40x/50x SPC560B40x/50x,

Table 6.

Functional port pin descriptions (continued)

(1)

Peripheral

(2)

RESET configuration

Pin number

I/Odirection

(3)

Portpin

PCR

Alternate function

Function

Padtype

LQFP64

LQFP100

LQFP144

LBGA208

PB[12]

PCR[28]

AF0

GPIO[28]

SIUL

I/O

J

Tristate

39

61

83

M16

AF1

E0UC[4]

eMIOS_0

I/O

AF2

—

—

—

AF3

CS1_0

DSPI_0

O

—

ANX[0]

ADC

I

PB[13]

PCR[29]

AF0

GPIO[29]

SIUL

I/O

J

Tristate

40

63

85

M13

AF1

E0UC[5]

eMIOS_0

I/O

AF2

—

—

—

ID Doc

AF3

CS2_0

DSPI_0

O

—

ANX[1]

ADC

I

PB[14]

PCR[30]

AF0

GPIO[30]

SIUL

I/O

J

Tristate

41

65

87

L16

14619

AF1

E0UC[6]

eMIOS_0

I/O

AF2

—

—

—

Rev

AF3

CS3_0

DSPI_0

O

—

ANX[2]

ADC

I

9

PB[15]

PCR[31]

AF0

GPIO[31]

SIUL

I/O

J

Tristate

42

67

89

L13

AF1

E0UC[7]

eMIOS_0

I/O

AF2

—

—

—

AF3

CS4_0

DSPI_0

O

—

ANX[3]

ADC

I

PC[0](9)

PCR[32]

AF0

GPIO[32]

SIUL

I/O

M

Input, weak

59

87

126

A8

AF1

—

—

—

pull-up

AF2

TDI

JTAGC

I

AF3

—

—

—

PC[1](9)

PCR[33]

AF0

GPIO[33]

SIUL

I/O

M

Tristate

54

82

121

C9

AF1

—

—

—

AF2

TDO(10)

JTAGC

O

AF3

—

—

—

25/117

SPC560C40x/50x SPC560B40x/50x,

descriptions signal and pinouts Package

26/117

9 Rev 14619 ID Doc

Table 6.

Functional port pin descriptions (continued)

(1)

Peripheral

(2)

RESET configuration

Pin number

I/Odirection

(3)

Portpin

PCR

Alternate function

Function

Padtype

LQFP64

LQFP100

LQFP144

LBGA208

PC[2]

PCR[34]

AF0

GPIO[34]

SIUL

I/O

M

Tristate

50

78

117

A11

AF1

SCK_1

DSPI_1

I/O

AF2

CAN4TX(11)

FlexCAN_4

O

AF3

—

—

—

—

EIRQ[5]

SIUL

I

PC[3]

PCR[35]

AF0

GPIO[35]

SIUL

I/O

S

Tristate

49

77

116

B11

AF1

CS0_1

DSPI_1

I/O

AF2

MA[0]

ADC

O

AF3

—

—

—

—

CAN1RX

FlexCAN_1

I

—

CAN4RX(11)

FlexCAN_4

I

—

EIRQ[6]

SIUL

I

PC[4]

PCR[36]

AF0

GPIO[36]

SIUL

I/O

M

Tristate

62

92

131

B7

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

SIN_1

DSPI_1

I

—

CAN3RX(11)

FlexCAN_3

I

PC[5]

PCR[37]

AF0

GPIO[37]

SIUL

I/O

M

Tristate

61

91

130

A7

AF1

SOUT_1

DSPI1

O

AF2

CAN3TX(11)

FlexCAN_3

O

AF3

—

—

—

—

EIRQ[7]

SIUL

I

PC[6]

PCR[38]

AF0

GPIO[38]

SIUL

I/O

S

Tristate

16

25

36

R2

AF1

LIN1TX

LINFlex_1

O

AF2

—

—

—

AF3

—

—

—

descriptions signal and pinouts Package

SPC560C40x/50x SPC560B40x/50x,

Table 6.

Functional port pin descriptions (continued)

(1)

Peripheral

(2)

RESET configuration

Pin number

I/Odirection

(3)

Portpin

PCR

Alternate function

Function

Padtype

LQFP64

LQFP100

LQFP144

LBGA208

PC[7]

PCR[39]

AF0

GPIO[39]

SIUL

I/O

S

Tristate

17

26

37

P3

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

LIN1RX

LINFlex_1

I

—

WKPU[12](4)

WKPU

I

PC[8]

PCR[40]

AF0

GPIO[40]

SIUL

I/O

S

Tristate

63

99

143

A1

AF1

LIN2TX

LINFlex_2

O

ID Doc

AF2

—

—

—

AF3

—

—

—

PC[9]

PCR[41]

AF0

GPIO[41]

SIUL

I/O

S

Tristate

2

2

2

B1

14619

AF1

—

—

—

AF2

—

—

—

Rev

AF3

—

—

—

—

LIN2RX

LINFlex_2

I

9

—

WKPU[13](4)

WKPU

I

PC[10]

PCR[42]

AF0

GPIO[42]

SIUL

I/O

M

Tristate

13

22

28

M3

AF1

CAN1TX

FlexCAN_1

O

AF2

CAN4TX(11)

FlexCAN_4

O

AF3

MA[1]

ADC

O

PC[11]

PCR[43]

AF0

GPIO[43]

SIUL

I/O

S

Tristate

—

21

27

M4

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

CAN1RX

FlexCAN_1

I

—

CAN4RX(11)

FlexCAN_4

I

—

WKPU[5](4)

WKPU

I

27/117

SPC560C40x/50x SPC560B40x/50x,

descriptions signal and pinouts Package

28/117

9 Rev 14619 ID Doc

Table 6.

Functional port pin descriptions (continued)

(1)

Peripheral

(2)

RESET configuration

Pin number

I/Odirection

(3)

Portpin

PCR

Alternate function

Function

Padtype

LQFP64

LQFP100

LQFP144

LBGA208

PC[12]

PCR[44]

AF0

GPIO[44]

SIUL

I/O

M

Tristate

—

97

141

B4

AF1

E0UC[12]

eMIOS_0

I/O

AF2

—

—

—

AF3

—

—

—

—

SIN_2

DSPI_2

I

PC[13]

PCR[45]

AF0

GPIO[45]

SIUL

I/O

S

Tristate

—

98

142

A2

AF1

E0UC[13]

eMIOS_0

I/O

AF2

SOUT_2

DSPI_2

O

AF3

—

—

—

PC[14]

PCR[46]

AF0

GPIO[46]

SIUL

I/O

S

Tristate

—

3

3

C1

AF1

E0UC[14]

eMIOS_0

I/O

AF2

SCK_2

DSPI_2

I/O

AF3

—

—

—

—

EIRQ[8]

SIUL

I

PC[15]

PCR[47]

AF0

GPIO[47]

SIUL

I/O

M

Tristate

—

4

4

D3

AF1

E0UC[15]

eMIOS_0

I/O

AF2

CS0_2

DSPI_2

I/O

AF3

—

—

—

PD[0]

PCR[48]

AF0

GPIO[48]

SIUL

I

I

Tristate

—

41

63

P12

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

GPI[4]

ADC

I

PD[1]

PCR[49]

AF0

GPIO[49]

SIUL

I

I

Tristate

—

42

64

T12

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

GPI[5]

ADC

I

descriptions signal and pinouts Package

SPC560C40x/50x SPC560B40x/50x,

Table 6. Functional port pin descriptions (continued)

				(1)		Peripheral	(2)		RESET configuration		Pin number
							I/Odirection						(3)
		Portpin	PCR	Alternate function	Function			Padtype		LQFP64	LQFP100	LQFP144	LBGA208
		PD[2]	PCR[50]	AF0	GPIO[50]	SIUL	I	I	Tristate	—	43	65	R12
				AF1	—	—	—
				AF2	—	—	—
				AF3	—	—	—
				—	GPI[6]	ADC	I
		PD[3]	PCR[51]	AF0	GPIO[51]	SIUL	I	I	Tristate	—	44	66	P13
				AF1	—	—	—
				AF2	—	—	—
	ID Doc			AF3	—	—	—
				—	GPI[7]	ADC	I
		PD[4]	PCR[52]	AF0	GPIO[52]	SIUL	I	I	Tristate	—	45	67	R13
	14619			AF1	—	—	—
				AF2	—	—	—
	Rev			AF3	—	—	—
				—	GPI[8]	ADC	I
	9
		PD[5]	PCR[53]	AF0	GPIO[53]	SIUL	I	I	Tristate	—	46	68	T13
				AF1	—	—	—
				AF2	—	—	—
				AF3	—	—	—
				—	GPI[9]	ADC	I
		PD[6]	PCR[54]	AF0	GPIO[54]	SIUL	I	I	Tristate	—	47	69	T14
				AF1	—	—	—
				AF2	—	—	—
				AF3	—	—	—
				—	GPI[10]	ADC	I
		PD[7]	PCR[55]	AF0	GPIO[55]	SIUL	I	I	Tristate	—	48	70	R14
				AF1	—	—	—
				AF2	—	—	—
	29/117			AF3	—	—	—
				—	GPI[11]	ADC	I

SPC560C40x/50x SPC560B40x/50x,

descriptions signal and pinouts Package

30/117

9 Rev 14619 ID Doc

Table 6.

Functional port pin descriptions (continued)

(1)

Peripheral

(2)

RESET configuration

Pin number

I/Odirection

(3)

Portpin

PCR

Alternate function

Function

Padtype

LQFP64

LQFP100

LQFP144

LBGA208

PD[8]

PCR[56]

AF0

GPIO[56]

SIUL

I

I

Tristate

—

49

71

T15

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

GPI[12]

ADC

I

PD[9]

PCR[57]

AF0

GPIO[57]

SIUL

I

I

Tristate

—

56

78

N15

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

GPI[13]

ADC

I

PD[10]

PCR[58]

AF0

GPIO[58]

SIUL

I

I

Tristate

—

57

79

N14

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

GPI[14]

ADC

I

PD[11]

PCR[59]

AF0

GPIO[59]

SIUL

I

I

Tristate

—

58

80

N16

AF1

—

—

—

AF2

—

—

—

AF3

—

—

—

—

GPI[15]

ADC

I

PD[12](8)

PCR[60]

AF0

GPIO[60]

SIUL

I/O

J

Tristate

—

60

82

M15

AF1

CS5_0

DSPI_0

O

AF2

E0UC[24]

eMIOS_0

I/O

AF3

—

—

—

—

ANS[4]

ADC

I

PD[13]

PCR[61]

AF0

GPIO[61]

SIUL

I/O

J

Tristate

—

62

84

M14

AF1

CS0_1

DSPI_1

I/O

AF2

E0UC[25]

eMIOS_0

I/O

AF3

—

—

—

—

ANS[5]

ADC

I

descriptions signal and pinouts Package

SPC560C40x/50x SPC560B40x/50x,