ST STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC User Manual

STM32F105xx

STM32F107xx

Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces

Features

■Core: ARM 32-bit Cortex™-M3 CPU

–72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access

–Single-cycle multiplication and hardware division

■Memories

–64 to 256 Kbytes of Flash memory

–up to 64 Kbytes of SRAM

■Clock, reset and supply management

–2.0 to 3.6 V application supply and I/Os

–POR, PDR, and programmable voltage detector (PVD)

–3-to-25 MHz crystal oscillator

–Internal 8 MHz factory-trimmed RC

–Internal 40 kHz RC with calibration

–32 kHz oscillator for RTC with calibration

■Low power

–Sleep, Stop and Standby modes

–VBAT supply for RTC and backup registers

■2 × 12-bit, 1 µs A/D converters (16 channels)

–Conversion range: 0 to 3.6 V

–Sample and hold capability

–Temperature sensor

–up to 2 MSps in interleaved mode

■2 × 12-bit D/A converters

■DMA: 12-channel DMA controller

–Supported peripherals: timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs

■Debug mode

–Serial wire debug (SWD) & JTAG interfaces

–Cortex-M3 Embedded Trace Macrocell™

■Up to 80 fast I/O ports

–51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

	Preliminary Data
	FBGA
LQFP64 10 × 10 mm,	LFBGA100 10 × 10 mm
LQFP100 14 × 14 mm,

■Up to 10 timers

–Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

–1 × 16-bit motor control PWM timer with dead-time generation and emergency stop

–2 × watchdog timers (Independent and Window)

–SysTick timer: a 24-bit downcounter

–2 × 16-bit basic timers to drive the DAC

■Up to 14 communication interfaces

–Up to 2 × I2C interfaces (SMBus/PMBus)

–Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)

–Up to 3 SPIs (18 Mbit/s), 2 with a multiplexed I2S interface that offers audio class accuracy via advanced PLL schemes

–2 × CAN interfaces (2.0B Active) with

512 bytes of dedicated SRAM

–USB 2.0 full-speed device/host/OTG controller with on-chip PHY that supports HNP/SRP/ID with 1.25 Kbytes of dedicated SRAM

–10/100 Ethernet MAC with dedicated DMA and SRAM (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages

■CRC calculation unit, 96-bit unique ID

Table 1. Device summary

Reference

Part number

STM32F105R8, STM32F105V8 STM32F105xx STM32F105RB, STM32F105VB STM32F105RC, STM32F105VC

STM32F107xx

STM32F107RB, STM32F107VB

STM32F107RC, STM32F107VC

February 2009

Rev 2

1/90

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to	www.st.com
change without notice.

Contents	STM32F105xx, STM32F107xx

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 9
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 9
	2.1	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.2	Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	2.3	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11

2.3.1 ARM® CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . 11 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 12 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 12 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 15

2.4 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.7 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.8Universal synchronous/asynchronous receiver transmitters (USARTs) 17

2.4.9 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.10 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.11Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 17

2.4.12	Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
2.4.13	Universal serial bus on-the-go full-speed (USB OTG FS) . . . . . . . . . . .	18

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STM32F105xx, STM32F107xx	Contents

2.4.14 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.15 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.16 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.17 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.18 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.19 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3	Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
4	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		33
5.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		34
	5.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	5.3.2	Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . .	35
	5.3.3	Embedded reset and power control block characteristics . . . . . . . . . . .	35
	5.3.4	Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
	5.3.5	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
	5.3.6	External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
	5.3.7	Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
	5.3.8	PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
	5.3.9	Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
	5.3.10	EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
	5.3.11	Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . .	53
	5.3.12	I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	54
	5.3.13	NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
	5.3.14	TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
	5.3.15	Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59

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Contents	STM32F105xx, STM32F107xx

5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		75
	6.1	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	75
7	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		80
Appendix A Applicative block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			81
	A.1	USB OTG FS interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
	A.2	Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
	A.3	Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	86
	A.4	USB OTG FS interface + Ethernet/I2S interface solutions . . . . . . . . . . . .	87

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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STM32F105xx, STM32F107xx	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F105xx and STM32F107xx features and peripheral counts . . . . . . . . . . . . . . . . . . 10 Table 3. STM32F105xx and STM32F107xx family versus STM32F103xx family . . . . . . . . . . . . . . 11 Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 6. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 7. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 8. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 9. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 10. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 11. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 12. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 13. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 14. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 39 Table 16. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 40 Table 17. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 18. Typical current consumption in Sleep mode, code with data processing

code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 20. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 21. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 22. HSE 3-25 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 24. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 25. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 26. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 27. PLL1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 28. PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 29. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 30. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 31. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 32. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 33. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 34. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 36. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 37. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 38. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 39. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 40. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 41. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 42. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 43. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 44. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

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List of tables	STM32F105xx, STM32F107xx

Table 45. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 46. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 47. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 48. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 49. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 50. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 51. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 52. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 53. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 54. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 55. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 56. LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . . 76 Table 57. LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 78 Table 58. LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 79 Table 59. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 60. PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 61. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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STM32F105xx, STM32F107xx	List of figures

List of figures

Figure 1.	STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . .	21
Figure 2.	STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout . . . . . . . . . . . . . .	22
Figure 3.	STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout . . . . . . . . . . . . . . .	23
Figure 4.	STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout . . . . . . . . . . . . . . .	24
Figure 5.	Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Figure 6.	Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 7.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 8.	Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 9.	Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 10.	Typical current consumption in Run mode versus frequency (at 3.6 V) -
	code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . .	38
Figure 11.	Typical current consumption in Run mode versus frequency (at 3.6 V) -
	code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . .	38
Figure 12.	Typical current consumption in Stop mode with regulator in Run mode versus
	temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 13.	Current consumption in Stop mode with regulator in Low-power mode versus
	temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
Figure 14.	Current consumption in Standby mode versus temperature at different VDD values . . . . .	41
Figure 15.	High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
Figure 16.	Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
Figure 17.	Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
Figure 18.	Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 19.	I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
Figure 20.	Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
Figure 21.	I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
Figure 22.	SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
Figure 23.	SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
Figure 24.	SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	63
Figure 25.	I2S slave timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
Figure 26.	I2S master timing diagram(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
Figure 27.	USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . .	66
Figure 28.	Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
Figure 29.	Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
Figure 30.	Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
Figure 31.	ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
Figure 32.	Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
Figure 33.	Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . .	72
Figure 34.	Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . .	72
Figure 35.	LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . .	76
Figure 36.	Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . .	77
Figure 37.	LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . .	78
Figure 38.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	78
Figure 39.	LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
Figure 40.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
Figure 41.	USB OTG FS device mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
Figure 42.	Host connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82
Figure 43.	OTG connection (any protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
Figure 44.	MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83

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List of figures	STM32F105xx, STM32F107xx

Figure 45. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 46. RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 47. RMII with a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 48. Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 49. Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 50. USB OTG FS + Ethernet solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 51. USB OTG FS + I2S (Audio) solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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STM32F105xx, STM32F107xx	Introduction

1 Introduction

This datasheet provides the description of the STM32F105xx and STM32F107xx connectivity line microcontrollers. For more details on the whole STMicroelectronics STM32F10xxx family, please refer to Section 2.2: Full compatibility throughout the family.

The STM32F105xx and STM32F107xx datasheet should be read in conjunction with the STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

2 Description

The STM32F105xx and STM32F107xx connectivity line family incorporates the highperformance ARM® Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 256 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, four general-purpose 16-bit timers plus a PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, five USARTs, an USB OTG FS and two CANs. Ethernet is available on the STM32F107xx only.

The STM32F105xx and STM32F107xx connectivity line family operates in the –40 to +105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of powersaving mode allows the design of low-power applications.

The STM32F105xx and STM32F107xx connectivity line family offers devices in three different package types: from 64 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

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Description	STM32F105xx, STM32F107xx

These features make the STM32F105xx and STM32F107xx connectivity line microcontroller family suitable for a wide range of applications:

●Motor drive and application control

●Medical and handheld equipment

●Industrial applications: PLC, inverters, printers, and scanners

●Alarm systems, Video intercom, and HVAC

●Car audio, home audio equipment

Figure 1 shows the general block diagram of the device family.

2.1Device overview

Table 2.	STM32F105xx and STM32F107xx features and peripheral counts
	Peripherals		STM32F105Rx			STM32F107Rx				STM32F105Vx			STM32F107Vx
Flash memory in Kbytes			64	128	256	128		256		64	128	256	128		256
SRAM in Kbytes			20	32	64	48		64		20	32	64	48		64
Ethernet				No			Yes				No		Yes
		General-purpose					4
Timers		Advanced-control					1
		Basic					2
		SPI(I2S)(1)					3(2)
		I2C					2
Communication
		USART					5
interfaces
		USB OTG FS						Yes
		CAN					2
GPIOs					51							80
12-bit ADC							2
Number of channels							16
12-bit DAC							2
Number of channels							2
CPU frequency								72 MHz
Operating voltage								2.0 to 3.6 V
Operating temperatures				Ambient temperatures: –40 to +85 °C /–40 to +105 °C
					Junction temperature: –40 to + 125 °C
Package					LQFP64						LQFP100, BGA100

1. The SPI2 and SPI3 interfaces give the flexibility to work in either the SPI mode or the I2S audio mode.

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STM32F105xx, STM32F107xx	Description

2.2Full compatibility throughout the family

The STM32F105xx and STM32F107xx constitute the connectivity line family whose members are fully pin-to-pin, software and feature compatible.

The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density (STM32F103x4/6), medium-density (STM32F103x8/B) and high-density (STM32F103xC/D/E) performance line devices, allowing the user to try different memory densities and peripherals providing a greater degree of freedom during the development cycle.

Table 3.

STM32F105xx and STM32F107xx family versus STM32F103xx family

STM32

Low-density

Medium-density

High-density

STM32F103xx

STM32F105xx

STM32F107xx

device

STM32F103xx devices

STM32F103xx devices

devices

Flash

16

32

32

64

128

256

384

512

64

128

256

128

256

size (KB)

RAM

6

10

10

20

20

48

64

64

20

32

64

48

64

size (KB)

144 pins

100 pins

5 × USARTs

5

× USARTs,

3 × USARTs

4 × 16-bit timers,

5 × USARTs,

4

× 16-bit timers,

2 × basic timers, 3 × SPIs,

2

× basic timers,

4 × 16-bit timers,

2 × USARTs

3 × 16-bit

3

× SPIs, 2 × I2Ss,

2 × I2Ss, 2 × I2Cs, USB,

2 × basic timers, 3 × SPIs,

2 × USARTs

2 × 16-bit

timers

CAN, 2 × PWM timers

2

× I2Cs,

timers

2 × SPIs,

2 × I2Ss, 2 × I2Cs,

USB OTG FS,

64 pins

2 × 16-bit timers

3 × ADCs, 1 × DAC,

USB OTG FS,

2 × I2Cs, USB,

2

1 × SPI,

1 × SDIO, FSMC (100-

2

× CANs,

1 × SPI, 1 × I

C,

1 × I2C,

CAN,

and 144-pin packages

(1)

)

2 × CANs, 1 × PWM timer,

1

× PWM timer,

USB, CAN,

USB, CAN,

1 × PWM timer

2 × ADCs, 1 × DAC

2

× ADCs,

1 × PWM timer

1 × PWM

2 × ADCs

1

× DAC, Ethernet

2 × ADCs

timer

48 pins

2 × ADCs

36 pins

1. Ports F and G are not available in devices delivered in 100-pin packages.

2.3Overview

2.3.1ARM® CortexTM-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

With its embedded ARM core, STM32F105xx and STM32F107xx connectivity line family is compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

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Description	STM32F105xx, STM32F107xx

2.3.2Embedded Flash memory

64 to 256 Kbytes of embedded Flash is available for storing programs and data.

2.3.3CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

2.3.4Embedded SRAM

20 to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

2.3.5Nested vectored interrupt controller (NVIC)

The STM32F105xx and STM32F107xx connectivity line embeds a nested vectored interrupt controller able to handle up to 67 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

●Closely coupled NVIC gives low latency interrupt processing

●Interrupt entry vector table address passed directly to the core

●Closely coupled NVIC core interface

●Allows early processing of interrupts

●Processing of late arriving higher priority interrupts

●Support for tail-chaining

●Processor state automatically saved

●Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

2.3.6External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 20 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.

2.3.7Clocks and startup

System clock selection is performed on startup, however, the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 3-25 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

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STM32F105xx, STM32F107xx	Description

interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

A single 25 MHz crystal can clock the entire system including the ethernet and USB OTG FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. Refer to Figure 50: USB OTG FS + Ethernet solution on page 87.

The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In order to achieve audio class performance, an audio crystal can be used. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy error. Refer to Figure 51: USB OTG FS + I2S (Audio) solution on page 87.

To configure the PLLs, please refer to Table 60 on page 88, which provides PLL configurations according to the application type.

2.3.8Boot modes

At startup, boot pins are used to select one of three boot options:

●Boot from User Flash

●Boot from System Memory

●Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1, USART2 (remapped), CAN2 (remapped), USB OTG FS in device mode (DFU: device firmware upgrade) and Ethernet.

2.3.9Power supply schemes

●VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins.

●VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively.

●VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

2.3.10Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher

than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

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Description	STM32F105xx, STM32F107xx

2.3.11Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●MR is used in the nominal regulation mode (Run)

●LPR is used in the Stop modes.

●Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

2.3.12Low-power modes

The STM32F105xx and STM32F107xx connectivity line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

●Stop mode

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB OTG FS wakeup.

●Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

Note:	The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
	or Standby mode.

2.3.13 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to- peripheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced control timers TIMx, DAC, I2S and ADC.

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STM32F105xx, STM32F107xx	Description

2.3.14RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present.

They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.4Timers and watchdogs

The STM32F105xx and STM32F107xx devices include six general-purpose timers, two basic timers and two watchdog timers.

Table 4 compares the features of the general-purpose and basic timers.

Table 4.		Timer feature comparison
Timer		Counter	Counter	Prescaler	DMA request	Capture/compare	Complementary
		resolution	type	factor	generation	channels	outputs
			Up,	Any integer
TIM1		16-bit	down,	between 1	Yes	4	Yes
			up/down	and 65536
TIMx
(TIM2,			Up,	Any integer
TIM3,		16-bit	down,	between 1	Yes	4	No
TIM4,			up/down	and 65536
TIM5)
TIM6,				Any integer
		16-bit	Up	between 1	Yes	0	No
TIM7
				and 65536

2.4.1Advanced-control timer (TIM1)

The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:

●Input capture

●Output compare

●PWM generation (edge or center-aligned modes)

●One-pulse mode output

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Description	STM32F105xx, STM32F107xx

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.

2.4.2General-purpose timers (TIMx)

There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F105xx and STM32F107xx connectivity line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. They can work together with the Advanced Control timer via the Timer Link feature for synchronization or event chaining.

The counter can be frozen in debug mode.

Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations.

2.4.3Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

2.4.4Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

2.4.5Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

2.4.6SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

●A 24-bit down counter

●Autoreload capability

●Maskable system interrupt generation when the counter reaches 0.

●Programmable clock source

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STM32F105xx, STM32F107xx	Description

2.4.7I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

2.4.8Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F105xx and STM32F107xx connectivity line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.

2.4.9Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

2.4.10Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 96 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency with less than 0.5% accuracy error owing to the advanced clock controller (see Section 2.3.7: Clocks and startup).

Please refer to the “Audio frequency precision” tables provided in the “Serial peripheral interface (SPI)” section of the STM32F10xxx reference manual.

2.4.11Ethernet MAC interface with dedicated DMA and IEEE 1588 support

Peripheral not available on STM32F105xx devices.

The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard media-independent interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx requires an external physical interface device (PHY) to connect to the physical LAN bus

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Description	STM32F105xx, STM32F107xx

(twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25 MHz (MII) or 50 MHz (RMII) output from the STM32F107xx.

The STM32F107xx includes the following features:

●Supports 10 and 100 Mbit/s rates

●Dedicated DMA channel

●Tagged MAC frame support (VLAN support)

●Half-duplex (CSMA/CD) and full-duplex operation

●MAC control sublayer (control frames) support

●32-bit CRC generation and removal

●Several address filtering modes for physical and multicast address (multicast and group addresses)

●32-bit status code for each transmitted or received frame

●Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes (512 × 35 bits), that is 4 Kbytes in total

●Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 1.0 with the timestamp comparator connected to the TIM2 trigger input

●Triggers interrupt when system time becomes greater than target time

2.4.12Controller area network (CAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total) are not shared with any other peripheral.

2.4.13Universal serial bus on-the-go full-speed (USB OTG FS)

The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG fullspeed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:

●1.25 KB of SRAM used exclusively by the endpoints (not shared with any other peripheral)

●4 bidirectional endpoints

●HNP/SNP/IP inside (no need for any external resistor)

●for OTG/Host modes, a power switch is needed in case bus-powered devices are connected

●the SOF output can be used to synchronize the external audio DAC clock in isochronous mode

●in accordance with the USB 2.0 Specification, the supported transfer speeds are:

–in Host mode: full speed and low speed

–in Device mode: full speed

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STM32F105xx, STM32F107xx	Description

2.4.14GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

I/Os on APB2 with up to 18 MHz toggling speed

2.4.15ADCs (analog-to-digital converters)

Two 12-bit analog-to-digital converters are embedded into STM32F105xx and STM32F107xx connectivity line devices and each ADC shares up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

●Simultaneous sample and hold

●Interleaved sample and hold

●Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the standard timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

2.4.16DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

●two DAC converters: one for each output channel

●8-bit or 12-bit monotonic output

●left or right data alignment in 12-bit mode

●synchronized update capability

●noise-wave generation

●triangular-wave generation

●dual DAC channel independent or simultaneous conversions

●DMA capability for each channel

●external triggers for conversion

●input voltage reference VREF+

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Description	STM32F105xx, STM32F107xx

Eight DAC trigger inputs are used in the STM32F105xx and STM32F107xx connectivity line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

2.4.17Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

2.4.18Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

2.4.19Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB OTG FS, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

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STM32F105xx, STM32F107xx	Description

Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram

TRACECLK

TRACED[0:3]

TPIU

ETM

as AF

SW/JTAG

Trace/Trig

JNTRST

obl

JTDI

Ibus

JTCK/SWCLK	Cortex-M3 CPU	Flashl
JTMS/SWDIO
JTDO	Fmax: 48 / 72 MHz	Dbus
as AF

MII_TXD[3:0]/RMII_TXD[1:0]

MII_TX_CLK/RMII_TX_CLK

MII_TX_EN/RMII_TX_EN

MII_RXD[3:0]/RMII_RXD[1:0]

MII_RX_ER/RMII_RX_ER

MII_RX_CLK/RMII_REF_CLK

MII_RX_DV/RMII_CRS_DV

MII_CRS

MII_COL/RMII_COL

MDC

MDIO

PPS_OUT

SOF

VBUS

ID

DM

DP

80 AF

PA[ 15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

	System
GP DMA1	x
	BusMatri
NVIC

7 channels

GP DMA2

5 channels

Ethernet MAC

10/100

DPRAM 2KB DPRAM 2KB

USB OTG FS

AHB2

APB2

SRAM 1.25KB

EXT.IT

WKUP

GPIO port A

GPIO port B

GPIO port C

GPIO port D

GPIO port E

APB2 : Fmax =48 / 72 MHz

Interface		Flash 256 KB
		64 bit

SRAM						@VDDA
64 KB
						RC HS
						RC LS
						PLL3
						PLL2
				PLL1

Reset &		PCLK1
clock		PCLK2
MANAGT
control		HCLK
		FCLK

AHB2

APB1

4 Channels
4 compl. Channels	TIM1
BKIN, ETR input as AF
MOSI,MISO,	SPI1
SCK,NSS as AF
RX,TX, CTS, RTS,	USART1		WWDG
CK as AF
	Temp sensor
16 ADC12_INs	12bit ADC1	IF
common to
ADC1 & ADC2	12bit ADC2	IF	TIM6
			TIM7

VREF–
						@VDDA
VREF+

VDD18

Power

VDD = 2 to 3.6 V

Voltage reg.

VSS

3.3 V to 1.8 V

@VDD

POR

Supply

Reset

supervision

NRST

Int

POR / PDR

VDDA

VSSA

PVD

@VDDA

@VDD

OSC_IN

XTAL osc

OSC_OUT

3-25 MHz

IWDG

	Standby
	interface		VBAT =1.8 V to 3.6 V
		@VBAT
	XTAL 32kHz		OSC32_IN
			OSC32_OUT
	RTC	Backup	TAMPER-RTC/
		register
	AWU		ALARM/SECOND OUT
	Backup interface

TIM2

4 Channels, ETR

as AF

TIM3

4 Channels, ETR

as AF

TIM4

4 Channels, ETR

as AF

TIM5

4 Channel s, ETR

as AF

RX,TX, CTS, RTS,

USART2

CK as AF

RX,TX, CTS, RTS,

USART3

CK as AF

RX,TX as AF

UART4

RX,TX as AF

UART5

MOSI/SD, MISO, MCK,

SPI2 / I2S2

SCK/CK, NSS/WS as AF

2x(8x16b it)

MOSI/SD, MISO, MCK,

SPI3 / I2S3

SCK/CK, NSS/WS as AF

2x(8x16b it)

I2C1

SCL,SDA,SMBAL

as AF

I2C2

SCL,SDA,SMBAL

as AF

bxCAN1 device

CAN1_TX as AF

CAN1_RX as AF

SRAM 512B

CAN2_TX as AF

bxCAN2 device

CAN2_RX as AF

IF	12bit DAC1	DAC_OUT1 as AF
IF
	12bit DAC 2	DAC_OUT2 as AF
	@VDDA	VREF+

ai15411

1.TA = –40 °C to +85 °C (suffix 6, see Table 59) or –40 °C to +105 °C (suffix 7, see Table 59), junction temperature up to 105 °C or 125 °C, respectively.

2.AF = alternate function on I/O port pin.

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Pin descriptions	STM32F105xx, STM32F107xx

3 Pin descriptions

Figure 2. STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout

	VDD 3	VSS 3	PE1	PE0	PB9	PB8	BOOT0	PB7	PB6	PB5	PB4	PB3	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0	PC12	PC11	PC10	PA15	PA14
PE2	100	99	98	97	96	95	94	93	92	91	90	89	88	87	86	85	84	83	82	81	80	79	78	77	76
	1																								75	VDD_2
PE3	2																								74	VSS_2
PE4	3																								73	NC
PE5	4																								72	PA 13
PE6	5																								71	PA 12
VBAT	6																								70	PA 11
PC13-TAMPER-RTC 7																									69	PA 10
PC14-OSC32_IN	8																								68	PA 9
PC15-OSC32_OUT	9																								67	PA 8
VSS_5	10																								66	PC9
VDD_5	11																								65	PC8
OSC_IN	12										LQFP100														64	PC7
OSC_OUT	13																								63	PC6
NRST	14																								62	PD15
PC0	15																								61	PD14
PC1	16																								60	PD13
PC2	17																								59	PD12
PC3	18																								58	PD11
VSSA	19																								57	PD10
VREF-	20																								56	PD9
VREF+	21																								55	PD8
VDDA	22																								54	PB15
PA0-WKUP	23																								53	PB14
PA1	24																								52	PB13
PA2	25																								51	PB12
	26	27	28	29	30	31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50
	PA3	VSS 4	VDD 4	PA4	PA5	PA6	PA7	PC4	PC5	PB0	PB1	PB2	PE7	PE8	PE9	PE10	PE11	PE12	PE13	PE14	PE15	PB10	PB11	VSS 1	VDD 1
																										ai14391

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STM32F105xx, STM32F107xx

Pin descriptions

Figure 3. STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout

V

V

PB9

PB8

BOOT0

PB7

PB6 PB5 PB4 PB3

PD2

PC12

PC11

PC10

PA15

PA14

DD3

SS3

VBAT

VDD_2

PC13-TAMPER-RTC

VSS_2

PC14-OSC32_IN

PA13

PC15-OSC32_OUT

PA12

PD0 OSC_IN

PA11

PD1 OSC_OUT

PA10

NRST

PA9

PC0

LQFP64

PA8

PC1

PC9

PC2

PC8

PC3

PC7

VSSA

PC6

VDDA

PB15

PA0-WKUP

PB14

PA1

PB13

PA2

PB10

PB11

PB12

PA3

V

V

PA4

PA5

PA6

PA7 PC4 PC5 PB0

PB1

PB2

V

V

SS4

DD4

SS1

DD1

ai14392

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	Pin descriptions								STM32F105xx, STM32F107xx
	Figure 4. STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout
		1	2	3	4	5	6	7	8	9	10
	A	PC14-	PC13-	PE2	PB9	PB7	PB4	PB3	PA15	PA14	PA13
		OSC32_INTAMPER-RTC
	B	PC15-	VBAT	PE3	PB8	PB6	PD5	PD2	PC11	PC10	PA12
		OSC32_OUT
	C	OSC_IN VSS_5		PE4	PE1	PB5	PD6	PD3	PC12	PA9	PA11
	D	OSC_OUT VDD_5		PE5	PE0	BOOT0	PD7	PD4	PD0	PA8	PA10
	E	NRST	PC2	PE6	VSS_4	VSS_3	VSS_2	VSS_1	PD1	PC9	PC7
	F	PC0	PC1	PC3	VDD_4	VDD_3	VDD_2	VDD_1	NC	PC8	PC6
	G	VSSA PA0-WKUP		PA4	PC4	PB2	PE10	PE14	PB15	PD11	PD15
	H	VREF–	PA1	PA5	PC5	PE7	PE11	PE15	PB14	PD10	PD14
	J	VREF+	PA2	PA6	PB0	PE8	PE12	PB10	PB13	PD9	PD13
	K	VDDA	PA3	PA7	PB1	PE9	PE13	PB11	PB12	PD8	PD12
											AI16001c

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STM32F105xx, STM32F107xx									Pin descriptions
Table 5.			Pin definitions
BGA100	Pins	LQFP100			Type	(2)		Alternate functions
	LQFP64					O/ILevel	Main
				Pin name	(1)		function(3)
							(after reset)	Default	Remap
A3	-	1		PE2	I/O	FT	PE2	TRACECK
B3	-	2		PE3	I/O	FT	PE3	TRACED0
C3	-	3		PE4	I/O	FT	PE4	TRACED1
D3	-	4		PE5	I/O	FT	PE5	TRACED2
E3	-	5		PE6	I/O	FT	PE6	TRACED3
B2	1	6		VBAT	S		VBAT
A2	2	7		PC13-TAMPER-	I/O		PC13(5)	TAMPER-RTC
				RTC(4)
A1	3	8		PC14-	I/O		PC14(5)	OSC32_IN
				OSC32_IN(4)
B1	4	9		PC15-	I/O		PC15(5)	OSC32_OUT
				OSC32_OUT(4)
C2	-	10		VSS_5	S		VSS_5
D2	-	11		VDD_5	S		VDD_5
C1	5	12		OSC_IN	I		OSC_IN
D1	6	13		OSC_OUT	O		OSC_OUT
E1	7	14		NRST	I/O		NRST
F1	8	15		PC0	I/O		PC0	ADC12_IN10
F2	9	16		PC1	I/O		PC1	ADC12_IN11/ ETH_MII_MDC/
								ETH_RMII_MDC
E2	10	17		PC2	I/O		PC2	ADC12_IN12/ ETH_MII_TXD2
F3	11	18		PC3	I/O		PC3	ADC12_IN13/
								ETH_MII_TX_CLK
G1	12	19		VSSA	S		VSSA
H1	-	20		VREF-	S		VREF-
J1	-	21		VREF+	S		VREF+
K1	13	22		VDDA	S		VDDA
								WKUP/USART2_CTS(6)
G2	14	23		PA0-WKUP	I/O		PA0	ADC12_IN0/TIM2_CH1_ETR
								TIM5_CH1/
								ETH_MII_CRS_WKUP
								USART2_RTS(6)/ ADC12_IN1/
H2	15	24		PA1	I/O		PA1	TIM5_CH2 /TIM2_CH2(6)/
								ETH_MII_RX_CLK/
								ETH_RMII_REF_CLK

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Pin descriptions								STM32F105xx, STM32F107xx
Table 5.			Pin definitions		(continued)
BGA100	Pins	LQFP100			Type	(2)		Alternate functions
	LQFP64					O/ILevel	Main
				Pin name	(1)		function(3)
							(after reset)	Default	Remap
								USART2_TX(6)/
J2	16	25		PA2	I/O		PA2	TIM5_CH3/ADC12_IN2/
								TIM2_CH3 (6)/ ETH_MII_MDIO/
								ETH_RMII_MDIO
								USART2_RX(6)/
K2	17	26		PA3	I/O		PA3	TIM5_CH4/ADC12_IN3
								TIM2_CH4(6)/ ETH_MII_COL
E4	18	27		VSS_4	S		VSS_4
F4	19	28		VDD_4	S		VDD_4
G3	20	29		PA4	I/O		PA4	SPI1_NSS(6)/DAC_OUT1
								USART2_CK(6) ADC12_IN4
H3	21	30		PA5	I/O		PA5	SPI1_SCK(6)
								DAC_OUT2 ADC12_IN5
J3	22	31		PA6	I/O		PA6	SPI1_MISO(6)/ADC12_IN6	TIM1_BKIN
								TIM3_CH1(6)
								SPI1_MOSI(6)/ADC12_IN7
K3	23	32		PA7	I/O		PA7	TIM3_CH2(6)/	TIM1_CH1N
								ETH_MII_RX_DV/
								ETH_RMII_CRS_DV
								ADC12_IN14/
G4	24	33		PC4	I/O		PC4	ETH_MII_RXD0/
								ETH_RMII_RXD0
								ADC12_IN15/
H4	25	34		PC5	I/O		PC5	ETH_MII_RXD1/
								ETH_RMII_RXD1
J4	26	35		PB0	I/O		PB0	ADC12_IN8/TIM3_CH3/	TIM1_CH2N
								ETH_MII_RXD2
K4	27	36		PB1	I/O		PB1	ADC12_IN9/TIM3_CH4(6)/	TIM1_CH3N
								ETH_MII_RXD3
G5	28	37		PB2	I/O	FT	PB2/BOOT1
H5	-	38		PE7	I/O	FT	PE7		TIM1_ETR
J5	-	39		PE8	I/O	FT	PE8		TIM1_CH1N
K5	-	40		PE9	I/O	FT	PE9		TIM1_CH1
-	-	-		VSS_7	S
-	-	-		VDD_7	S
G6	-	41		PE10	I/O	FT	PE10		TIM1_CH2N
H6	-	42		PE11	I/O	FT	PE11		TIM1_CH2
J6	-	43		PE12	I/O	FT	PE12		TIM1_CH3N

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STM32F105xx, STM32F107xx									Pin descriptions
Table 5.			Pin definitions		(continued)
BGA100	Pins	LQFP100			Type	(2)		Alternate functions
	LQFP64					O/ILevel	Main
				Pin name	(1)		function(3)
							(after reset)	Default	Remap
K6	-	44		PE13	I/O	FT	PE13		TIM1_CH3
G7	-	45		PE14	I/O	FT	PE14		TIM1_CH4
H7	-	46		PE15	I/O	FT	PE15		TIM1_BKIN
J7	29	47		PB10	I/O	FT	PB10	I2C2_SCL/USART3_TX(6)/	TIM2_CH3
								ETH_MII_RX_ER
								I2C2_SDA/USART3_RX(6)/
K7	30	48		PB11	I/O	FT	PB11	ETH_MII_TX_EN/	TIM2_CH4
								ETH_RMII_TX_EN
E7	31	49		VSS_1	S		VSS_1
F7	32	50		VDD_1	S		VDD_1
								SPI2_NSS/I2S2_WS/
								I2C2_SMBAL// USART3_CK(6)/
K8	33	51		PB12	I/O	FT	PB12	TIM1_BKIN(6)/CAN2_RX/
								ETH_MII_TXD0/
								ETH_RMII_TXD0
								SPI2_SCK/I2S2_CK
								USART3_CTS(6)/
J8	34	52		PB13	I/O	FT	PB13	TIM1_CH1N/CAN2_TX/
								ETH_MII_TXD1/
								ETH_RMII_TXD1
H8	35	53		PB14	I/O	FT	PB14	SPI2_MISO/TIM1_CH2N
								USART3_RTS(6)
G8	36	54		PB15	I/O	FT	PB15	SPI2_MOSI/I2S2_SD
								TIM1_CH3N(6)
K9	-	55		PD8	I/O	FT	PD8		USART3_TX/
									ETH_MII_RX_DV
J9	-	56		PD9	I/O	FT	PD9		USART3_RX/
									ETH_MII_RX_D0
H9	-	57		PD10	I/O	FT	PD10		USART3_CK/
									ETH_MII_RX_D1
G9	-	58		PD11	I/O	FT	PD11		USART3_CTS/
									ETH_MII_RX_D2
									TIM4_CH1 /
K10	-	59		PD12	I/O	FT	PD12		USART3_RTS/
									ETH_MII_RX_D3
J10	-	60		PD13	I/O	FT	PD13		TIM4_CH2
H10	-	61		PD14	I/O	FT	PD14		TIM4_CH3
G10	-	62		PD15	I/O	FT	PD15		TIM4_CH4
F10	37	63		PC6	I/O	FT	PC6	I2S2_MCK/	TIM3_CH1

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