ST STM8L151F3, STM8L151G3, STM8L151K3, STM8L151C3, STM8L151F2 User Manual

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STM8L151C2/K2/G2/F2

STM8L151C3/K3/G3/F3

8-bit ultralow power MCU, up to 8 KB Flash, up to 256 B data EEPROM, RTC, timers, USART, I2C, SPI, ADC, comparators

Datasheet − production data

Features

■Operating conditions

–Operating power supply: 1.65 to 3.6 V (without BOR), 1.8 to 3.6 V (with BOR)

–Temperature range: -40 to 85 or 125 °C

■Low power features

–5 low power modes: Wait, Low power run, Low power wait, Active-halt with RTC, Halt

–Ultralow leakage per I/0: 50 nA

–Fast wakeup from Halt: 5 µs

■Advanced STM8 core

–Harvard architecture and 3-stage pipeline

–Max freq: 16 MHz, 16 CISC MIPS peak

–Up to 40 external interrupt sources

■Reset and supply management

–Low power, ultrasafe BOR reset with 5 selectable thresholds

–Ultralow power POR/PDR

–Programmable voltage detector (PVD)

■Clock management

–32 kHz and 1-16 MHz crystal oscillators

–Internal 16 MHz factory-trimmed RC

–Internal 38 kHz low consumption RC

–Clock security system

■Low power RTC

–BCD calendar with alarm interrupt

–Digital calibration with +/- 0.5 ppm accuracy

–LSE security system

–Auto-wakeup from Halt w/ periodic interrupt

■Memories

–Up to 8 Kbytes of Flash program memory plus 256 bytes of data EEPROM with ECC

–Flexible write/read protection modes

–1 Kbyte of RAM

LQFP48	UFQFPN32
	UFQFPN20
UFQFPN28	TSSOP20

■DMA

–4 channels supporting ADC, SPI, I2C, USART, timers

–1 channel for memory-to-memory

■12-bit ADC up to 1 Msps/28 channels

–Temp. sensor and internal ref. voltage

■2 ultralow power comparators

–1 with fixed threshold and 1 rail to rail

–Wakeup capability

■Timers

–Two 16-bit timers with 2 channels (IC, OC, PWM), quadrature encoder (TIM2, TIM3)

–One 8-bit timer with 7-bit prescaler (TIM4)

–1 Window and 1 independent watchdog

–Beeper timer with 1, 2 or 4 kHz frequencies

■Communication interfaces

–One synchronous serial interface (SPI)

–Fast I2C 400 kHz

–One USART

■Up to 41 I/Os, all mappable on interrupt vectors

■Up to 20 capacitive sensing channels supporting touchkey, proximity touch, linear touch, and rotary touch sensors

■Development support

–Fast on-chip programming and nonintrusive debugging with SWIM

–Bootloader using USART

■96-bit unique ID

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This is information on a product in full production.

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Contents	STM8L151x2, STM8L151x3

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 9
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	2.1	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	2.2	Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
3	Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14

3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3	Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	3.3.1	Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.3.2	Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.3.3	Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
3.4	Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
3.5	Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
3.6	Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
3.7	DMA . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
3.8	Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
3.9	Ultra-low-power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
3.10	System configuration controller and routing interface . . . . . . . . . . . . . . .		21
3.11	Touchsensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
3.12	Timers .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	3.12.1	16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	3.12.2	8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
3.13	Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22

3.13.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.14 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.15.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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		3.15.2	I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 23
		3.15.3	USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 23
	3.16	Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 23
	3.17	Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 24
4	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . 25

4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5	Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			31
	5.1	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31
	5.2	Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
6	Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			47
7	Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			49
	7.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		49
		7.1.1	Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
		7.1.2	Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
		7.1.3	Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
		7.1.4	Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
		7.1.5	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
	7.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		50
	7.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		52

7.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 53 7.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.9 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.3.11 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.3.12 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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	7.4	Thermal characteristics . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . 96
8	Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . 97
9	Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . 100
10	Package characteristics . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . 101
	10.1	ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . 101
	10.2	Package mechanical data . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . 102

10.2.1 48-pin low profile quad flat 7x7mm package (LQFP48) . . . . . . . . . . . . 102

10.2.232-lead ultra thin fine pitch quad flat no-lead 5x5 mm package

(UFQFPN32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.2.328-lead ultra thin fine pitch quad flat no-lead 4x4 mm package

(UFQFPN28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

10.2.420-lead ultra thin fine pitch quad flat no-lead package (UFQFPN20) . 107

11	Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	110
12	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	111

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STM8L151x2, STM8L151x3	List of tables

List of tables

Table 1. Low density STM8L15xxx low power device features and peripheral counts. . . . . . . . . . . 12 Table 2. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 3. Legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 4. Low density STM8L15xxx pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 6. Factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 7. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 8. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 9. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 10. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 15. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 16. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 17. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 18. Total current consumption and timing in Low power run mode at VDD = 1.65 V to

3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 19. Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . 61 Table 20. Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V. . . . . 62 Table 21. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 62 Table 22. Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V . . . . . . . . . . . 63 Table 23. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 24. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 25. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 26. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 27. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 28. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 29. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 30. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 31. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 32. Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 33. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 34. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 35. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 36. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 37. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 76 Table 38. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 39. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 40. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 41. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 42. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 43. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 44. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 45. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 46. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 47. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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List of tables	STM8L151x2, STM8L151x3

Table 48. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 49. RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 50. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 51. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 52. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 53. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 54. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 55. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 56. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 57. Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 58. LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 59. UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 60. UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 61. UFQFPN20 - 20-lead ultra thin fine pitch quad flat package (3x3)

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 62. TSSOP20 - 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . 109

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STM8L151x2, STM8L151x3	List of figures

List of figures

Figure 1.	Low density STM8L151xx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 14
Figure 2.	Low density STM8L15x clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 19
Figure 3.	STM8L151Cx LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 25
Figure 4.	STM8L151Kx UFQFPN32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 25
Figure 5.	STM8L151Gx UFQFPN28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 6.	STM8L151Fx UFQFPN20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 7.	STM8L151Fx TSSOP20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 8.	Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 9.	Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 10.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
Figure 11.	POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	54
Figure 12.	Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
Figure 13.	Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
Figure 14.	Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
Figure 15.	Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
Figure 16.	HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
Figure 17.	LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
Figure 18.	Typical HSI frequency vs VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
Figure 19.	Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
Figure 20.	Typical VIL and VIH vs VDD (high sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	74
Figure 21.	Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	74
Figure 22.	Typical pull-up resistance RPU vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . .	75
Figure 23.	Typical pull-up current Ipu vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	75
Figure 24.	Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
Figure 25.	Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
Figure 26.	Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
Figure 27.	Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
Figure 28.	Typ. VDD - VOH @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
Figure 29.	Typ. VDD - VOH @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
Figure 30.	Typical NRST pull-up resistance RPU vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	78
Figure 31.	Typical NRST pull-up current Ipu vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
Figure 32.	Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
Figure 33.	SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
Figure 34.	SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
Figure 35.	SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82
Figure 36.	Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .	84
Figure 37.	ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
Figure 38.	Typical connection diagram using the ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
Figure 39.	Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . .	92
Figure 40.	Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . .	92
Figure 41.	Max. dynamic current consumption on VREF+ supply pin during ADC
	conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	93
Figure 42.	LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	102
Figure 43.	UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	103
Figure 44.	Recommended UFQFPN32 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	104
Figure 45.	UFQFPN28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	105
Figure 46.	Recommended UFQFPN28 footprint (dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . .	106
Figure 47.	UFQFPN20 - 20-lead ultra thin fine pitch quad flat package outline (3x3) . . . . . . . . . . . .	107

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List of figures	STM8L151x2, STM8L151x3

Figure 48. UFQFPN20 recommended footprint (dimensions in mm). . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 49. TSSOP20 - 20-pin thin shrink small outline package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 50. Low density STM8L15xxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . 110

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STM8L151x2, STM8L151x3	Introduction

1 Introduction

This document describes the features, pinout, mechanical data and ordering information for the Low density STM8L15xxx devices: STM8L151x2 and STM8L151x3 microcontrollers with a Flash memory density of up to 8 Kbytes.

For further details on the STMicroelectronics Ultralow power family please refer to

Section 2.2: Ultra-low-power continuum on page 13.

For detailed information on device operation and registers, refer to the reference manual (RM0031).

For information on to the Flash program memory and data EEPROM, refer to the programming manual (PM0054).

For information on the debug module and SWIM (single wire interface module), refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).

Low density devices provide the following benefits:

●Integrated system

–Up to 8 Kbytes of low-density embedded Flash program memory

–256 bytes of data EEPROM

–1 Kbyte of RAM

–Internal high-speed and low-power low speed RC.

–Embedded reset

●Ultralow power consumption

–1 µA in Active-halt mode

–Clock gated system and optimized power management

–Capability to execute from RAM for Low power wait mode and Low power run mode

●Advanced features

–Up to 16 MIPS at 16 MHz CPU clock frequency

–Direct memory access (DMA) for memory-to-memory or peripheral-to-memory access.

●Short development cycles

–Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals.

–Wide choice of development tools

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Introduction	STM8L151x2, STM8L151x3

STM8L Ultralow power microcontrollers can operate either from 1.8 to 3.6 V (down to 1.65 V at power-down) or from 1.65 to 3.6 V. They are available in the -40 to +85 °C and -40 to +125 °C temperature ranges.

These features make the STM8L Ultralow power microcontroller families suitable for a wide range of applications:

●Medical and handheld equipment

●Application control and user interface

●PC peripherals, gaming, GPS and sport equipment

●Alarm systems, wired and wireless sensors

●Metering

The devices are offered in five different packages from 20 to 48 pins. Different sets of peripherals are included depending on the device. Refer to Section 3 for an overview of the complete range of peripherals proposed in this family.

All STM8L Ultralow power products are based on the same architecture with the same memory mapping and a coherent pinout.

Figure 1 shows the block diagram of the STM8L Low density family.

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STM8L151x2, STM8L151x3	Description

2 Description

The Low density STM8L15xxx Ultralow power devices feature an enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultrafast Flash programming.

All Low density STM8L15xxx microcontrollers feature embedded data EEPROM and low power low-voltage single-supply program Flash memory.

The devices incorporate an extensive range of enhanced I/Os and peripherals, a 12-bit ADC, two comparators, a real-time clock, two 16-bit timers, one 8-bit timer, as well as standard communication interfaces such as an SPI, an I2C interface, and one USART. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.

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Description	STM8L151x2, STM8L151x3

2.1Device overview

Table 1.	Low density STM8L15xxx low power device features and peripheral counts
Features		STM8L151F3	STM8L151G3	STM8L151K3/		STM8L151F2	STM8L151G2	STM8L151K2/
				STM8L151C3				STM8L151C2

Flash (Kbytes)			8				4

Data EEPROM				256
(bytes)				256
(bytes)

RAM (Kbytes)					1

	Basic				1
	Basic			(8-bit)
Timers				(8-bit)

	General				2
	General				2
	purpose			(16-bit)

Commun	SPI				1
Commun
-ication	I2C				1
interfaces
interfaces	USART				1

GPIOs		18 (1)	26 (1)	30(2)/41(1)(2)		18 (1)	26 (1)	30(2)/41(1)(2)
12-bit synchronized		1	1	1		1	1	1
ADC (number of		1	1	1		1	1	1
ADC (number of		(10)	(18)	(23/28)(3)		(10)	(18)	(23/28)(3)
channels)		(10)	(18)	(23/28)(3)		(10)	(18)	(23/28)(3)
channels)

Comparators					2
(COMP1/COMP2)					2
(COMP1/COMP2)

Others			RTC, window watchdog, independent watchdog,
Others		16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator


CPU frequency				16 MHz

Operating voltage			1.8 to 3.6 V (down to 1.65 V at power-down) with BOR
Operating voltage				1.65 to 3.6 V without BOR
				1.65 to 3.6 V without BOR

Operating				− 40 to +85 °C / − 40 to +125 °C
temperature				− 40 to +85 °C / − 40 to +125 °C
temperature

Packages		TSSOP20	UFQFPN28	UFQFPN32		TSSOP20	UFQFPN28	UFQFPN32
Packages		UFQFPN20	UFQFPN28	LQFP48		UFQFPN20	UFQFPN28	LQFP48
		UFQFPN20		LQFP48		UFQFPN20		LQFP48

1.The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as general purpose output only (PA1).

2.26 GPIOs in the STM8L151K3 and 40 GPIOs in the STM8L151C3.

3.22 channels in the STM8L151K3 and 28 channels in the STM8L151C3.

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STM8L151x2, STM8L151x3	Description

2.2Ultra-low-power continuum

The ultra-low-power Low density STM8L15xxx devices are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features.

They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.

Note: 1 The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices.

Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.

Shared peripherals

STM8L151xx/152xx and STM32L15xx share identical peripherals which ensure a very easy migration from one family to another:

●Analog peripherals: ADC1 and comparators COMP1/COMP2

●Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L151xx/152xx and STM32L15xx devices use a common architecture:

●Same power supply range from 1.8 to 3.6 V, down to 1.65 V at power down

●Architecture optimized to reach ultra-low consumption both in low power modes and Run mode

●Fast startup strategy from low power modes

●Flexible system clock

●Ultra-safe reset: same reset strategy for both STM8L15x and STM32L15xxx including power-on reset, power-down reset, brownout reset and programmable voltage detector.

Features

ST ultra-low-power continuum also lies in feature compatibility:

●More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm

●Memory density ranging from 4 to 128 Kbytes

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ST STM8L151F3, STM8L151G3, STM8L151K3, STM8L151C3, STM8L151F2 User Manual

Functional overview	STM8L151x2, STM8L151x3

3 Functional overview

Figure 1. Low density STM8L151xx device block diagram

	OSC_IN,			1-16 MHz oscillator					@VDD
	OSC_OUT			1-16 MHz oscillator				VDD18	Power	VDD=1.65 V
	OSC_OUT						Clock
				16 MHz internal RC			Clock
				16 MHz internal RC			controller			to 3.6 V
	OSC32_IN,						controller		VOLT. REG.	VSS
	OSC32_IN,				32 kHz oscillator		and CSS	Clocks	VOLT. REG.
OSC32_OUT					32 kHz oscillator			Clocks
OSC32_OUT								to core and
				38 kHz internal RC				to core and
				38 kHz internal RC				peripherals		NRST
								peripherals	RESET
				Interrupt controller


					STM8 Core				POR/PDR
					STM8 Core
		SWIM			Debug module				BOR
		SWIM			(SWIM)
					(SWIM)					PVD_IN
									PVD	PVD_IN
									PVD
	2 channels				16-bit Timer 2	(2)			up to
					16-bit Timer 2

	2 channels				16-bit Timer 3(2)				8-Kbyte
					8-bit Timer 4(2)		ses		Program memory
					8-bit Timer 4(2)		ses		256-byte
							b u		Data EEPROM
	IR_TIM			Infrared interface			d at a		1-Kbyte RAM
				DMA1 (4 channels)			d
				DMA1 (4 channels)			an
	SCL, SDA,						an			PA[7:0]
	SCL, SDA,				I²C1		t rol		Port A	PA[7:0]
		SMB			I²C1		t rol		Port A
SPI1_MOSI, SPI1_MISO,							n		Port B	PB[7:0]
SPI1_MOSI, SPI1_MISO,					SPI1		, co		Port B	PB[7:0]
SPI1_SCK, SPI1_NSS					SPI1		, co			PC[7:0]
							d ress		Port C	PC[7:0]
USART1_RX, USART1_TX,							d ress		Port D	PD[7:0]
					USART1		A d		Port D

USART1_CK									Port E	PE[7:0]
USART1_CK

V	DDA,	V	SSA	@V	/V				Port F	PF0
	DDA,		SSA	DDA SSA

ADC1_INx	12-bit ADC1
VDDREF	12-bit ADC1
VDDREF			BEEP
VSSREF		Beeper	BEEP
VSSREF	Temp sensor	Beeper
	Temp sensor	RTC
		RTC	ALARM, CALIB,
VREFINT out	Internal reference	IWDG
VREFINT out	voltage	(38 kHz clock)
	voltage	(38 kHz clock)
COMP1_INP	COMP 1	WWDG
COMP2_INP
COMP2_INM	COMP 2
	COMP 2
			MS18275V2

1.Legend:

ADC: Analog-to-digital converter BOR: Brownout reset

DMA: Direct memory access

I²C: Inter-integrated circuit multimaster interface IWDG: Independent watchdog

POR/PDR: Power on reset / power down reset RTC: Real-time clock

SPI: Serial peripheral interface SWIM: Single wire interface module

USART: Universal synchronous asynchronous receiver transmitter WWDG: Window watchdog

2.There is no TIM1 on STM8L151x2, STM8L151x3 devices.

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STM8L151x2, STM8L151x3	Functional overview

3.1Low power modes

The Low density STM8L15x devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Wait mode: The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode). Wait consumption: refer to Table 17.

●Low power run mode: The CPU and the selected peripherals are running. Execution is done from RAM with a low speed oscillator (LSI or LSE). Flash and data EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode. The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset.

All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power run mode consumption: refer to Table 18.

●Low power wait mode: This mode is entered when executing a Wait for event in Low power run mode. It is similar to Low power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an event, the system goes back to Low power run mode.

All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power wait mode consumption: refer to Table 19.

●Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup can be triggered by RTC interrupts, external interrupts or reset. Active-halt consumption: refer to Table 20 and Table 21.

●Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The RAM content is preserved. The wakeup is triggered by an external interrupt or reset. A few peripherals have also a wakeup from Halt capability. Switching off the internal reference voltage reduces power consumption. Through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 µs. Halt consumption: refer to

Table 22.

3.2Central processing unit STM8

3.2.1Advanced STM8 Core

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions.

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Functional overview	STM8L151x2, STM8L151x3

Architecture and registers

●Harvard architecture

●3-stage pipeline

●32-bit wide program memory bus - single cycle fetching most instructions

●X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations

●8-bit accumulator

●24-bit program counter - 16 Mbyte linear memory space

●16-bit stack pointer - access to a 64 Kbyte level stack

●8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

●20 addressing modes

●Indexed indirect addressing mode for lookup tables located anywhere in the address space

●Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

●80 instructions with 2-byte average instruction size

●Standard data movement and logic/arithmetic functions

●8-bit by 8-bit multiplication

●16-bit by 8-bit and 16-bit by 16-bit division

●Bit manipulation

●Data transfer between stack and accumulator (push/pop) with direct stack access

●Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2Interrupt controller

The Low density STM8L15x features a nested vectored interrupt controller:

●Nested interrupts with 3 software priority levels

●32 interrupt vectors with hardware priority

●Up to 40 external interrupt sources on 11 vectors

●Trap and reset interrupts

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STM8L151x2, STM8L151x3	Functional overview

3.3Reset and supply management

3.3.1Power supply scheme

The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows:

●VSS1 ; VDD1 = 1.8 to 3.6 V, down to 1.65 V at power down: external power supply for I/Os and for the internal regulator. Provided externally through VDD1 pins, the corresponding ground pin is VSS1.

●VSSA ; VDDA = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for analog peripherals (minimum voltage to be applied to VDDA is 1.8 V when the ADC1 is used). VDDA and VSSA must be connected to VDD1 and VSS1, respectively.

●VSS2 ; VDD2 = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for I/Os. VDD2 and VSS2 must be connected to VDD1 and VSS1, respectively.

●VREF+ ; VREF- (for ADC1): external reference voltage for ADC1. Must be provided externally through VREF+ and VREF- pin.

3.3.2Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently (in which case, the VDD min value at power down is 1.65 V).

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the BOR) in Halt mode. The device remains

under reset when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3Voltage regulator

The Low density STM8L15x embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes:

●Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event (WFE) modes.

●Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low power wait modes.

When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.

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Functional overview	STM8L151x2, STM8L151x3

3.4Clock management

The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

●Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

●Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register.

●Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

●System clock sources: 4 different clock sources can be used to drive the system clock:

–1-16 MHz High speed external crystal (HSE)

–16 MHz High speed internal RC oscillator (HSI)

–32.768 kHz Low speed external crystal (LSE)

–38 kHz Low speed internal RC (LSI)

●RTC clock sources: the above four sources can be chosen to clock the RTC whatever the system clock.

●Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

●Clock security system (CSS): This feature can be enabled by software. If a HSE clock failure occurs, the system clock is automatically switched to HSI.

●Configurable main clock output (CCO): This outputs an external clock for use by the application.

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Figure 2. Low density STM8L15x clock tree diagram

			SWIM[3:0]
OSC_OUT	HSE OSC	HSE		SYSCLK to core and
OSC_OUT	HSE OSC	HSE	SYSCLK			memory
OSC_IN	1-16 MHz	HSI	SYSCLK
		LSI	prescaler
	HSI RC	LSI	/1;2;4;8;16;32;64			PCLK to
	1-16 MHz	LSE				PCLK to
	1-16 MHz			Peripheral	peripherals
				Peripheral	peripherals
				Clock
				enable (13 bits)
		LSE				to
				BEEPCLK		to
				BEEPCLK		BEEP
			CLKBEEPSEL[1:0]			BEEP
			CLKBEEPSEL[1:0]
	LSI RC	LSI				to
	LSI RC			IWDGCLK		to
	38 kHz			IWDGCLK		IWDG
		RTCSEL[3:0]
			RTC			to
	LSE OSC		RTC			RTC
OSC32_OUT	LSE OSC		prescaler	RTCCLK		RTC
OSC32_OUT	32.768 kHz		/1;2;4;8;16;32;64
OSC32_IN			/1;2;4;8;16;32;64


	Configurable		HSI
	clock output	CCO	HSI
CCO	clock output	CCO	LSI
CCO		prescaler	HSE
			HSE
			LSE
	/1;2;4;8;16;32;64		LSE
	/1;2;4;8;16;32;64
		CCOSEL[3:0]			MS18281V1
					MS18281V1

3.5Low power real-time clock

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.

Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically.

It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability.

●Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach 36 hours

●Periodic alarms based on the calendar can also be generated from every second to every year

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Functional overview	STM8L151x2, STM8L151x3

3.6Memories

The Low density STM8L15x devices have the following main features:

●Up to 1 Kbyte of RAM

●The non-volatile memory is divided into three arrays:

–Up to 8 Kbytes of low-density embedded Flash program memory

–256 bytes of data EEPROM

–Option bytes.

The EEPROM embeds the error correction code (ECC) feature.

The option byte protects part of the Flash program memory from write and readout piracy.

3.7DMA

A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and peripherals-from/to-memory transfer capability. The 4 channels are shared between the following IPs with DMA capability: ADC1, I2C1, SPI1, USART1, the three Timers.

3.8Analog-to-digital converter

●12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel), temperature sensor and internal reference voltage

●Conversion time down to 1 µs with fSYSCLK= 16 MHz

●Programmable resolution

●Programmable sampling time

●Single and continuous mode of conversion

●Scan capability: automatic conversion performed on a selected group of analog inputs

●Analog watchdog

●Triggered by timer

Note:

ADC1 can be served by DMA1.

3.9Ultra-low-power comparators

The Low density STM8L15x embeds two comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal or external (coming from an I/O).

●One comparator with fixed threshold (COMP1).

●One comparator rail to rail with fast or slow mode (COMP2). The threshold can be one of the following:

–External I/O

–Internal reference voltage or internal reference voltage submultiple (1/4, 1/2, 3/4)

The two comparators can be used together to offer a window function. They can wake up from Halt mode.

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3.10System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.

The highly flexible routing interface controls the routing of internal analog signals to ADC1,

COMP1, COMP2, and the internal reference voltage VREFINT. It also provides a set of registers for efficiently managing the charge transfer acquisition sequence (Section 3.11:

Touchsensing).

3.11Touchsensing

Low density STM8L15xxx devices provide a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (example, glass, plastic). The capacitive variation introduced by a finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. In Low density STM8L15xxx devices, the acquisition sequence is managed either by software or by hardware and it involves analog I/O groups, the routing interface, and timers.Reliable touch sensing solutions can be quickly and easily implemented using the free STM8 Touch Sensing Library.

3.12Timers

Low density STM8L15x devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4).

All the timers can be served by DMA1.

Table 2 compares the features of the advanced control, general-purpose and basic timers.

Table 2.		Timer feature comparison
		Counter	Counter		DMA1	Capture/compare	Complementary
Timer		Counter	Counter	Prescaler factor	request	Capture/compare	Complementary
Timer	resolution		type	Prescaler factor	request	channels	outputs
					generation

TIM2		16-bit	up/down	Any power of 2		2
				Any power of 2
TIM3				from 1 to 128	Yes		None
				from 1 to 128


TIM4		8-bit	up	Any power of 2		0
TIM4		8-bit	up	from 1 to 32768		0
				from 1 to 32768

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Functional overview	STM8L151x2, STM8L151x3

3.12.116-bit general purpose timers

●16-bit autoreload (AR) up/down-counter

●7-bit prescaler adjustable to fixed power of 2 ratios (1…128)

●2 individually configurable capture/compare channels

●PWM mode

●Interrupt capability on various events (capture, compare, overflow, break, trigger)

●Synchronization with other timers or external signals (external clock, reset, trigger and enable)

3.12.28-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.13Watchdog timers

The watchdog system is based on two independent timers providing maximum security to the applications.

3.13.1Window watchdog timer

The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

3.13.2Independent watchdog timer

The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the internal LSI RC clock source, and thus stays active even in case of a CPU clock failure.

3.14Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

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3.15Communication interfaces

3.15.1SPI

The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial communication with external devices.

●Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave

●Full duplex synchronous transfers

●Simplex synchronous transfers on 2 lines with a possible bidirectional data line

●Master or slave operation - selectable by hardware or software

●Hardware CRC calculation

●Slave/master selection input pin

Note:

SPI1 can be served by the DMA1 Controller.

3.15.2I²C

The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C busspecific sequencing, protocol, arbitration and timing.

	● Master, slave and multi-master capability
	● Standard mode up to 100 kHz and fast speed modes up to 400 kHz.
	● 7-bit and 10-bit addressing modes.
	● SMBus 2.0 and PMBus support
	● Hardware CRC calculation
Note:	I2C1 can be served by the DMA1 Controller.

3.15.3	USART
	The USART interface (USART1) allows full duplex, asynchronous communications with
	external devices requiring an industry standard NRZ asynchronous serial data format. It
	offers a very wide range of baud rates.
	● 1 Mbit/s full duplex SCI
	●	SPI1 emulation
	● High precision baud rate generator
	●	Smartcard emulation
	● IrDA SIR encoder decoder
	● Single wire half duplex mode
Note:	USART1 can be served by the DMA1 Controller.

3.16 Infrared (IR) interface

The Low density STM8L15x devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.

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Functional overview	STM8L151x2, STM8L151x3

3.17Development support

Development tools

Development tools for the STM8 microcontrollers include:

●The STice emulation system offering tracing and code profiling

●The STVD high-level language debugger including C compiler, assembler and integrated development environment

●The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, CPU operation can also be monitored in realtime by means of shadow registers.

Bootloader

The Low density STM8L15xxx Ultralow power devices feature a built-in bootloader (see

UM0560: STM8 bootloader user manual).

The bootloader is used to download application software into the device memories, including RAM, program and data memory, using standard serial interfaces. It is a complementary solution to programming via the SWIM debugging interface.

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STM8L151x2, STM8L151x3	Pin description

4 Pin description

Figure 3. STM8L151Cx LQFP48 package pinout

	PE7	PE6		PC7		PC6		PC5		PC4		PC3	PC2	SSIO		DDIO	PC1	PC0
	PE7	PE6		PC7		PC6		PC5		PC4		PC3	PC2		V V		PC1	PC0


PA0	48	47	46		45		44		43		42		41	40		39	38	37	PD7
PA0	1																	36	PD7
NRST/PA1																		35	PD6
NRST/PA1	2																	35	PD6
PA2																		34	PD5
PA2	3																	34	PD5
PA3	4																	33	PD4
PA4	5																	32	PF0
PA5																		31	PB7
	6
	6
PA6																		30	PB6
PA6	7																	30	PB6
PA7																		29	PB5
PA7	8																	29	PB5
VSS1/VSSA/VREF-	9																	28	PB4
VDD	10																	27	PB3
VDDA	11																	26	PB2
VDDA	11																	26
VREF+	12
	13	14			16		17											25	PB1
																		25	PB1
			15						18		19		20	21		22	23	24

(1)	PE0 PE1 PE2 PE3 PE4 PE5 PD0 PD1 PD2 PD3 PB0
Res.

MS18276V1

Figure 4. STM8L151Kx UFQFPN32 package pinout

	PA0 PC6 PC5 PC4 PC3				PC2 PC1 PC0
NRST/PA1	32	31	30	29 28	27 26 25	PD7
NRST/PA1	1				24	PD7
PA2	2				23	PD6
PA3	3				22	PD5
PA4	4				22	PD5
PA4	4				21	PD4
PA5	5				20	PB7
PA6	6				19	PB6
VSS1	7				18	PB5
VDD1	8 9	10 11 12 13			14 15 1617	PB4
	PD0 PD1		PD2	PD3 PB0	PB1 PB2 PB3

MS18277V1

Figure 5. STM8L151Gx UFQFPN28 package pinout

	PA0	PC6	PC5	PC4	PC3	PC2	PC1
NRST/PA1	28	27	26	25	24	23	22
NRST/PA1	1						21	PC0
PA2	2						20	PD4
PA3	3						19	PB7
PA4	4						18	PB6
PA5	5						17	PB5
VSS1/VSSA/VREF-	6						16	PB4
VDD1/VDDA/VREF+	7	9	10	11	12	13	15	PB3
	8	9	10	11	12	13	14
	PD0	PD1	PD2	PD3	PB0	PB1	PB2

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Pin description	STM8L151x2, STM8L151x3

Figure 6.	STM8L151Fx UFQFPN20 package pinout

NRST / PA1

PA2

PA3

VSS/VSSA/VREF- VDD/VDDA/VREF+

PA0	PC6	PC5	PC4	PC1

20	19	18	17	16
1				15
2				14
3				13
4				12
				12
5				11
				11
6	7	8	9	10

PD0	PB0	PB1	PB2	PB3

PC0

PB7

PB6

PB5

PB4

MS18279V1

Figure 7. STM8L151Fx TSSOP20 package pinout

PC5	1	20	PC4
PC6	2	19	PC1
PA0	3	18	PC0
NRST / PA1	4	17	PB7
PA2	5	16	PB6
PA3	6	15	PB5
VSS/VSSA/VREF-	7	14	PB4
VDD/VDDA/VREF+	8	13	PB3
PD0	9	12	PB2
PB0	10	11	PB1

MS18280V1

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Pin description

Table 3.

Legend/abbreviation for table 4

Type

I= input, O = output, S = power supply

Level

Output

HS = high sink/source (20 mA)

Five-volt tolerant

Port and control

Input

float = floating, wpu = weak pull-up

configuration

Output

T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Reset state

Unless otherwise specified, the pin state is the same during the reset phase (i.e.

“under reset”) and after internal reset release (i.e. at reset state).

Table 4.

Low density STM8L15xxx pin description

Pin number

Input

Output

Type

levelI/O

functionMain reset)(after

LQFP48

UFQFPN32

UFQFPN28

UFQFPN20

TSSOP20

Pin name

floating

wpu

interruptExt.

sink/sourceHigh

Default alternate

function

NRST/PA1(1)

I/O

Reset

PA1

PA2/OSC_IN/

HSE oscillator input /

[USART_TX](2)/

I/O

Port A2

[USART transmit] / [SPI

[SPI_MISO] (2)

master inslave out] /

PA3/OSC_OUT/[USA

HSE oscillator output /

RT_RX](2)/[SPI_MOSI

I/O

Port A3

[USART receive]/ [SPI

](2)

master out/slave in]/

PA4/TIM2_BKIN/

Timer 2 - break input /

[TIM2_ETR](2)

I/O

Port A4

[Timer 2 - external

ADC1_IN2

trigger] /ADC1 input 2

PA5/TIM3_BKIN/

Timer 3 - break input /

[Timer 3 - external

[TIM3_ETR](2)/ADC1_

I/O

Port A5

trigger] /

IN1

ADC1input 1

PA6/ADC1_TRIG/

I/O

Port A6

ADC1trigger

ADC1_IN0

/ADC1input 0

PA7

I/O

Port A7

PB0(3)/TIM2_CH1/

I/O

Port B0

Timer 2 - channel 1 /

ADC1_IN18

PB1/TIM3_CH1/

I/O

Port B1

Timer 3 - channel 1 /

ADC1_IN17

PB2/ TIM2_CH2/

I/O

Port B2

Timer 2 - channel 2

ADC1_IN16

PB3/TIM2_ETR/

Timer 2 - external

ADC1_IN15/RTC_AL

I/O

Port B3

trigger / ADC1_IN15 /

ARM(4)

RTC_ALARM (4)

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Pin description

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Table 4.

Low density STM8L15xxx pin description (continued)

Pin number

Input

Output

Type

levelI/O

functionMain reset)(after

LQFP48

UFQFPN32

UFQFPN28

UFQFPN20

TSSOP20

Pin name

floating

wpu

interruptExt.

sink/sourceHigh

Default alternate

function

PB4(3)/SPI1_NSS/

I/O

Port B4

SPI master/slave select

ADC1_IN14

/ ADC1_IN14

PB5/SPI_SCK/

I/O

Port B5

[SPI clock] /

/ADC1_IN13

ADC1_IN13

PB6/SPI1_MOSI/

I/O

Port B6

SPI master out/

ADC1_IN12

slave in / ADC1_IN12

PB7/SPI1_MISO/

SPI1 master inslave

I/O

Port B7

out/

ADC1_IN11

PC0/I2C_SDA

I/O

T(5)

Port C0

I2C data

PC1/I2C_SCL

I/O

T(3)

Port C1

I2C clock

PC2/USART_RX/ADC

I/O

Port C2

USART receive /

1_IN6

ADC1_IN6

PC3/USART_TX/

I/O

Port C3

USART transmit /

ADC1_IN5

PC4/USART_CK]/

USART synchronous

clock / I2C1_SMB /

I2C_SMB/CCO/

I/O

Port C4

Configurable clock

ADC1_IN4

output / ADC1_IN4

PC5/OSC32_IN

LSE oscillator input /

[SPI master/slave

/[SPI1_NSS](2)/

I/O

Port C5

select] / [USART

[USART_TX](2)/

TIM2_CH1(6)

transmit]/

Timer 2 -channel 1(6)

PC6/OSC32_OUT/

LSE oscillator output /

[SPI_SCK](2)/

I/O

Port C6

[SPI clock] / [USART

[USART_RX](2)/

receive]/

TIM2_CH2(6)

Timer 2 -channel 2(6)

PC7/ADC1_IN3

I/O

Port C7

ADC1_IN3

PD0/TIM3_CH2/

Timer 3 - channel 2 /

[ADC1_TRIG](2)/

I/O

Port D0

[ADC1_Trigger] /

ADC1_IN22

PD1/TIM3_ETR/

I/O

Port D1

Timer 3 - external

ADC1_IN21

trigger / ADC1_IN21

PD2/

I/O

Port D2

ADC1_IN20

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Pin description

Table 4.

Low density STM8L15xxx pin description (continued)

Pin number

Input

Output

Type

levelI/O

functionMain reset)(after

LQFP48

UFQFPN32

UFQFPN28

UFQFPN20

TSSOP20

Pin name

floating

wpu

interruptExt.

sink/sourceHigh

Default alternate

function

PD3/

ADC1_IN19/

I/O

Port D3

RTC calibration(7)

RTC_CALIB(7)

PD4/

I/O

Port D4

ADC1_IN10

PD5/ ADC1_IN9

I/O

Port D5

ADC1_IN9

PD6/

ADC1_IN8 / RTC

ADC1_IN8/RTC_CALI

I/O

Port D6

calibration

PD7

/ADC1_IN7/RTC_ALA

I/O

Port D7

ADC1_IN7 / RTC alarm

PE0

I/O

Port E0

PE1

I/O

Port E1

PE2

I/O

Port E2

PE3/ADC1_IN26

I/O

Port E3

ADC1_IN26

PE4/ADC1_IN27

I/O

Port E4

ADC1_IN27

PE5/ADC1_IN23/

ADC1_IN23/

I/O

Port E5

Comparator positive

COMP_INP

input

PE6/PVD_IN

I/O

Port E6

PVD_IN

PE7/ADC1_IN25

I/O

Port E7

ADC1_IN25

PF0/ADC1_IN24

I/O

Port F0

ADC1_IN24

VDD

Digital supply voltage

VDD /VDDA / VREF+

Digital supply voltage /

ADC1 positive voltage reference

Ground voltage / ADC1 negative

VSS / VREF- / VSSA

voltage reference / Analog ground

voltage

VDDA

Analog supply voltage

VREF+

ADC1 positive voltage

reference

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Pin description

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Table 4.

Low density STM8L15xxx pin description (continued)

Pin number

Input

Output

Type

levelI/O

functionMain reset)(after

LQFP48

UFQFPN32

UFQFPN28

UFQFPN20

TSSOP20

Pin name

floating

wpu

interruptExt.

sink/sourceHigh

Default alternate

function

PA0(8)/[USART_CK](2)

[USART1 synchronous

I/O

Port A0

clock](2) / SWIM input

and output /

SWIM/BEEP/IR_TIM

(9)

Beep output / Infrared

Timer output

VSSIO

I/O ground voltage

VDDIO

I/O supply voltage

1.At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L15xxx and STM8L16xxx reference manual (RM0031).

2.[ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).

3.A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

4.20-pin and 28-pin packages only.

5.In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented).

6.20-pin packages only.

7.28-pin packages only

8.The PA0 pin is in input pull-up during the reset phase and after reset release.

9.High Sink LED driver capability available on PA0.

Note:	The slope control of all GPIO pins, except true open drain pins, can be programmed. By
	default, the slope control is limited to 2 MHz.

4.1System configuration options

As shown in Table 4: Low density STM8L15xxx pin description, some alternate functions can be remapped on different I/O ports by programming one of the two remapping registers described in the “ Routing interface (RI) and system configuration controller” section in the STM8L15x and STM8L16x reference manual (RM0031).

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PA0	PC6	PC5	PC4	PC1

20	19	18	17	16
1				15
2				14
3				13
4				12
				12
5				11
				11
6	7	8	9	10

PD0	PB0	PB1	PB2	PB3

PA0	PC6	PC5	PC4	PC1

20	19	18	17	16
1				15
2				14
3				13
4				12
				12
5				11
				11
6	7	8	9	10

PD0	PB0	PB1	PB2	PB3

PA0	PC6	PC5	PC4	PC1

20	19	18	17	16
1				15
2				14
3				13
4				12
				12
5				11
				11
6	7	8	9	10

PD0	PB0	PB1	PB2	PB3