ST STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG User Manual

STM32F103xF

STM32F103xG

XL-density performance line ARM-based 32-bit MCU with 768 KB to 1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces

Features

■Core: ARM 32-bit Cortex™-M3 CPU with MPU

–72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access

–Single-cycle multiplication and hardware division

■Memories

–768 Kbytes to 1 Mbyte of Flash memory

–96 Kbytes of SRAM

–Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories

–LCD parallel interface, 8080/6800 modes

■Clock, reset and supply management

–2.0 to 3.6 V application supply and I/Os

–POR, PDR, and programmable voltage detector (PVD)

–4-to-16 MHz crystal oscillator

–Internal 8 MHz factory-trimmed RC

–Internal 40 kHz RC with calibration

–32 kHz oscillator for RTC with calibration

■Low power

–Sleep, Stop and Standby modes

–VBAT supply for RTC and backup registers

■3 × 12-bit, 1 µs A/D converters (up to 21 channels)

–Conversion range: 0 to 3.6 V

–Triple-sample and hold capability

–Temperature sensor

■2 × 12-bit D/A converters

■DMA: 12-channel DMA controller

–Supported peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs

■Debug mode

–Serial wire debug (SWD) & JTAG interfaces

–Cortex-M3 Embedded Trace Macrocell™

Target specification

FBGA

LQFP64 10 × 10 mm,

LQFP100 14 × 14 mm, LFBGA144 10 × 10 mm LQFP144 20 × 20 mm

■Up to 112 fast I/O ports

–51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

■Up to 17 timers

–Up to ten 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

–2 × 16-bit motor control PWM timers with dead-time generation and emergency stop

–2 × watchdog timers (Independent and Window)

–SysTick timer: a 24-bit downcounter

–2 × 16-bit basic timers to drive the DAC

■Up to 13 communication interfaces

–Up to 2 × I2C interfaces (SMBus/PMBus)

–Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)

–Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed

–CAN interface (2.0B Active)

–USB 2.0 full speed interface

–SDIO interface

■CRC calculation unit, 96-bit unique ID

■ECOPACK® packages

Table 1. Device summary

Reference

Part number

STM32F103xF

STM32F103RF STM32F103VF

STM32F103ZF

STM32F103xG

STM32F103RG STM32F103VG

STM32F103ZG

January 2012

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This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.

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Contents	STM32F103xF, STM32F103xG

Contents

1	Introduction		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
2	Description . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.1	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	2.2	Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	2.3	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
		2.3.1	ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . .	15
		2.3.2	Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
		2.3.3	Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
		2.3.4	CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . .	15
		2.3.5	Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
		2.3.6	FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . .	16
		2.3.7	LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
		2.3.8	Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . .	16
		2.3.9	External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . .	16
		2.3.10	Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
		2.3.11	Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
		2.3.12	Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
		2.3.13	Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
		2.3.14	Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
		2.3.15	Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
		2.3.16	DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
		2.3.17	RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . .	19
		2.3.18	Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
		2.3.19	I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21

2.3.20Universal synchronous/asynchronous receiver transmitters (USARTs) 21

2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.22 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.23 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.24 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.28 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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2.3.29 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.30 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.31 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3	Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
4	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
	5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		40
5.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
	5.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 41
	5.3.2	Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . .	. 42
	5.3.3	Embedded reset and power control block characteristics . . . . . . . . . .	. 42
	5.3.4	Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
	5.3.5	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
	5.3.6	External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	5.3.7	Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
	5.3.8	PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
	5.3.9	Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
	5.3.10	FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
	5.3.11	EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
	5.3.12	Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . .	82
	5.3.13	I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
	5.3.14	I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	84
	5.3.15	NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	89
	5.3.16	TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	90
	5.3.17	Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
	5.3.18	CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . .	100

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5.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			109
	6.1	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		109
	6.2	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		114
		6.2.1	Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 114
		6.2.2	Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . .	. 115
7	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			117
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			118

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STM32F103xF, STM32F103xG	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F103xF and STM32F103xG features and peripheral counts . . . . . . . . . . . . . . . . . 11 Table 3. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. STM32F103xF and STM32F103xG timer feature comparison . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. STM32F103xF and STM32F103xG pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 6. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 7. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 8. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 9. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 11. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 12. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 13. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 14. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 15. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 46 Table 17. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 47 Table 18. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 19. Typical current consumption in Sleep mode, code running from Flash or

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 20. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 21. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 22. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 23. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 24. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 25. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 26. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 28. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 29. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 30. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 63 Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 64 Table 33. Asynchronous read muxed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 34. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 35. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 36. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 37. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 38. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 39. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 40. Switching characteristics for PC Card/CF read and write cycles in

attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 41. Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . 78 Table 42. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 43. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

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Table 44. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 45. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 46. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 47. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 48. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 49. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 50. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 51. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 52. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 53. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 54. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 55. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 56. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 57. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 58. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 59. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 60. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 61. USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 62. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 63. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 64. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 65. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 66. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 67. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 68. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 69. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 111 Table 70. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 112 Table 71. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 113 Table 72. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 73. STM32F103xF and STM32F103xG ordering information scheme . . . . . . . . . . . . . . . . . . 117

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STM32F103xF, STM32F103xG	List of figures

List of figures

Figure 1.	STM32F103xF and STM32F103xG performance line block diagram. . . . . . . . . . . . . . . . .	12
Figure 2.	Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Figure 3.	STM32F103xF and STM32F103xG XL-density performance line BGA144 ballout . . . . . .	25
Figure 4.	STM32F103xF and STM32F103xG XL-density performance line LQFP144 pinout. . . . . .	26
Figure 5.	STM32F103xF and STM32F103xG XL-density performance line LQFP100 pinout. . . . . .	27
Figure 6.	STM32F103xF and STM32F103xG XL-density performance line
	LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 7.	Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
Figure 8.	Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Figure 9.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Figure 10.	Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
Figure 11.	Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
Figure 12.	Typical current consumption in Run mode versus frequency (at 3.6 V) -
	code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . .	45
Figure 13.	Typical current consumption in Run mode versus frequency (at 3.6 V)-
	code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . .	45
Figure 14.	Typical current consumption on VBAT with RTC on vs. temperature at different VBAT
	values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
Figure 15.	Typical current consumption in Stop mode with regulator in run mode
	versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 16.	Typical current consumption in Stop mode with regulator in low-power
	mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 17.	Typical current consumption in Standby mode versus temperature at
	different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 18.	High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
Figure 19.	Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
Figure 20.	Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
Figure 21.	Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
Figure 22.	Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . .	62
Figure 23.	Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . .	63
Figure 24.	Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . .	65
Figure 25.	Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . .	66
Figure 26.	Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
Figure 27.	Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
Figure 28.	Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . .	71
Figure 29.	Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	72
Figure 30.	PC Card/CompactFlash controller waveforms for common memory read access . . . . . . .	73
Figure 31.	PC Card/CompactFlash controller waveforms for common memory write access . . . . . . .	74
Figure 32.	PC Card/CompactFlash controller waveforms for attribute memory read
	access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	75
Figure 33.	PC Card/CompactFlash controller waveforms for attribute memory write
	access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	76
Figure 34.	PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . .	76
Figure 35.	PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . .	77
Figure 36.	NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
Figure 37.	NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
Figure 38.	NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . .	79
Figure 39.	NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . .	80

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List of figures		STM32F103xF, STM32F103xG
Figure 40. Standard I/O input characteristics - CMOS port . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . .	. 85
Figure 41. Standard I/O input characteristics - TTL port . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . .	. 85
Figure 42. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	86
Figure 43. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	86
Figure 44. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	89
Figure 45. Recommended NRST pin protection . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	89
Figure 46. I2C bus AC waveforms and measurement circuit . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	92
Figure 47. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	94
Figure 48. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	94
Figure 49. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	95
Figure 50. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	97
Figure 51. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	97
Figure 52. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	98
Figure 53. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . .	98
Figure 54. USB timings: definition of data signal rise and fall time . . . .		. . . . . . . . . . . . . . . . . . . . . .	100
Figure 55. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . .	103
Figure 56. Typical connection diagram using the ADC . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . .	104
Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . .			104
Figure 58. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . .			105
Figure 59. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . .	107
Figure 60. Recommended PCB design rules (0.80/0.75 mm pitch BGA		. . . . . . . . . . . . . . . . . . . . . .	109
Figure 61. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
	0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . .	110
Figure 62. LQFP144, 20 x 20 mm, 144-pin low-profile quad
	flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . .	111
Figure 63.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . .	111
Figure 64. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . .			112
Figure 65.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . .	112
Figure 66. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . .			113
Figure 67.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . .	113
Figure 68.	LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . .	116

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STM32F103xF, STM32F103xG	Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xF and STM32F103xG XL-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to

Section 2.2: Full compatibility throughout the family.

The XL-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

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Description	STM32F103xF, STM32F103xG

2 Description

The STM32F103xF and STM32F103xG performance line family incorporates the highperformance ARM® Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 1 Mbyte and SRAM up to 96 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, ten general-purpose 16-bit timers plus two PWM timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN.

The STM32F103xx XL-density performance line family operates in the –40 to +105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

These features make the STM32F103xx high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems and video intercom.

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STM32F103xF, STM32F103xG	Description

2.1Device overview

The STM32F103xx XL-density performance line family offers devices in four different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

Figure 1 shows the general block diagram of the device family.

Table 2.	STM32F103xF and STM32F103xG features and peripheral counts
Peripherals		STM32F103Rx			STM32F103Vx			STM32F103Zx
Flash memory		768 KB		1 MB	768 KB		1 MB	768 KB		1 MB
SRAM in Kbytes			96		96			96
FSMC			No		Yes(1)			Yes
	General-purpose				10
Timers	Advanced-control				2
	Basic				2
	SPI(I2S)(2)				3(2)
	I2C				2
Comm	USART				5
	USB				1
	CAN				1
	SDIO				1
GPIOs			51		80			112
12-bit ADC			3		3			3
Number of channels			16		16			21
12-bit DAC					2
Number of channels					2
CPU frequency					72 MHz
Operating voltage					2.0 to 3.6 V
Operating temperatures		Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 10)
			Junction temperature: –40 to + 125 °C (see Table 10)
Package		LQFP64			LQFP100			LQFP144, BGA144

1.For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.

2.The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.

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Description	STM32F103xF, STM32F103xG

Figure 1. STM32F103xF and STM32F103xG performance line block diagram

TRACECLK

TRACED[0:3]

TPIU

ETM

as AF

SWJTAG

Trace/Trig

NJTRST

Ib u s

JTDI

MPU

JTCK/SWCLK

JTMS/SWDAT

JTDO

Cortex-M3 CPU

Dbus

as AF

Fmax: 48/72 MHz

NVIC

S

ystem

obl		ce
Flash		interfa
bl
o		ce
Flash		interfa

Flash1 512 KB	VDD					POWER				VDD =2 t o 3 .6V
64 bit						VOLT. REG.
										VSS
						3.3V TO 1.8V
Flash2 512 KB						@VDD
64 bit	POR					SUPPLY
	Reset
					SUPERVISION					NRST
	Int
						POR / PDR				VDDA
										VSSA

	NVIC				@VDDA		PVD
				SRAM	RC HS	@VDDA		@V	DD
				96 Kbyte	RC LS					OSC_IN
					PLL		XTAL OSC			OSC_OUT
	GP DMA1						4-16 MHz
	7 channels					IWDG
	GP DMA2					Standby
A[25:0]					PCLK1	interface				VBAT=1.8 V to 3 .6V
	5 channels			Reset &
D[15:0]					PCLK2			@VSW
CLK				clock	PCLK3
										OSC32_IN
NOE				controller	HCLK	XTAL 32 kHz
										OSC32_OUT
NWE					FCLK
								Backup
NE[3:0]						RTC				TAMPER-RTC
NBL[1:0]								reg
	FSMC					AWU				(ALARM OUT)
NWAIT
						Backup interface
NL
as AF			AHB2			TIM2				4 Ch, ETR as AF
D[7:0], CMD
	SDIO	APB3	APB2	APB1		TIM3				4 Ch, ETR as AF
CK as AF

112 AF

EXT.IT

WKUP

PA[15:0]

GPIO port A

PB[15:0]

GPIO port B

PC[15:0]

GPIO port C

PD[15:0]

GPIO port D

PE[15:0]

GPIO port E

PF[15:0]

GPIO port F

PG[15:0]

GPIO port G

4 channels

4 compl. channels

TIM1

BKIN, ETR input as AF

4 channels

4 compl. channels

TIM8

BKIN, ETR input as AF

2 channels as AF

TIM9

1 channel as AF

TIM10

1 channel as AF

TIM11

MOSI,MISO,

SPI1

SCK,NSS as AF

RX,TX, CTS, RTS,

USART1

CK as AF

8 ADINs common

Temp sensor

to the 3 ADCs

12b it ADC1

IF

8 ADINs common

to the ADC1 & 2

12bit ADC2

IF

5 ADINs on ADC3

12b it ADC3

IF

VREF–

VREF+

@VDDA

APB2 : Fmax=48 / 72 MHz

WWDG

SRAM 512B

TIM6

TIM7

		TIM4							4 Ch, ETR as AF
		TIM5							4 Ch, ETR as AF
									2 channels as AF
		TIM12
		TIM13							1 channel as AF
									1 channel as AF
		TIM14
									RX,TX, CTS, RTS,
		USART2
									CK as AF
									RX,TX, CTS, RTS,
		USART3
									CK as AF
		UART4							RX,TX as AF
									RX,TX as AF
		UART5
									MOSI/SD,MISO,
	SPI2/I2S2								SCK/CK,NSS/WS,
									MCLK as AF
									MOSI/SD,MISO,
	SPI3/I2S3
									SCK/CK,NSS/WS,
									MCLK as AF
			I2C1						SCL,SDA,SMBA
									as AF
			I2C2							SCL,SDA,SMBA
										as AF
	b xCAN device										USBDP/CAN_TX
USB 2.0 FS device											USBDM/CAN_RX
	IF	12bit DAC1							DAC1_OUT as AF
	IF
		12bit DAC2							DAC2_OUT as AF
			@VDDA

ai17352

1.TA = –40 °C to +85 °C (suffix 6, see Table 73) or –40 °C to +105 °C (suffix 7, see Table 73), junction temperature up to 105 °C or 125 °C, respectively.

2.AF = alternate function on I/O port pin.

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STM32F103xF, STM32F103xG	Description

Figure 2.	Clock tree
						FLITFCLK
						to Flash programming interface
					USB	48 MHz		USBCLK
					Prescaler			to USB interface
					/1, 1.5
						I2S3CLK			to I2S3
					Peripheral clock
					enable	I2S2CLK			to I2S2
					Peripheral clock				SDIOCLK
	8 MHz				enable						to SDIO
						Peripheral clock
		HSI
	HSI RC					enable			FSMCCLK
											to FSMC
						Peripheral clock
		/2
						enable			HCLK
						72 MHz max
									to AHB bus, core,
						Clock			memory and DMA
						Enable			to Cortex System timer
	PLLSRC			SW		/8
		PLLMUL							FCLK Cortex
		..., x16	HSI	SYSCLK	AHB	APB1			free running clock
							36 MHz max				PCLK1
		x2, x3, x4	PLLCLK	72 MHz	Prescaler	Prescaler
											to APB1
		PLL			/1, 2..512	/1, 2, 4, 8, 16
				max			Peripheral Clock				peripherals
			HSE
							Enable
						TIM2,3,4,5,12,13,14,6,7				to TIM2/3/4/5/12/13/14
										and TIM6/7
						If (APB1 prescaler =1) x1
										TIMxCLK
				CSS			else	x2
									Peripheral Clock
									Enable
		PLLXTPRE				APB2	72 MHz max				PCLK2
						Prescaler
OSC_OUT										peripherals to APB2
	4-16 MHz					/1, 2, 4, 8, 16
							Peripheral Clock
OSC_IN	HSE OSC	/2					Enable
						TIM1, 8, 9, 10, 11				to TIM1/8
										and TIM9/10/11
						If (APB2 prescaler =1) x1
										TIMxCLK
							else x2
		/128							Peripheral Clock
						ADC			Enable
OSC32_IN				to RTC							to ADC1, 2 or 3
	LSE OSC	LSE				Prescaler	ADCCLK
	32.768 kHz		RTCCLK			/2, 4, 6, 8
OSC32_OUT

RTCSEL[1:0]

/2

HCLK/2

To SDIO AHB interface

to Independent Watchdog (IWDG)

Peripheral clock

LSI RC

LSI

enable

40 kHz

IWDGCLK

Main

Legend:

/2

PLLCLK

Clock Output

HSE = High-speed external clock signal

MCO

HSI

HSI = High-speed internal clock signal

HSE

LSI = Low-speed internal clock signal

SYSCLK

LSE = Low-speed external clock signal

MCO

ai17354

1.When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz.

2.For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz.

3.To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.

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Description	STM32F103xF, STM32F103xG

2.2Full compatibility throughout the family

The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices and the STM32F103xF and STM32F103xG are called XL-density devices.

Low-density, high-density and XL-density devices are an extension of the STM32F103x8/B medium-density devices, they are specified in the STM32F103x4/6, STM32F103xC/D/E and STM32F103xF/G datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC. XL-density devices bring even more Flash and RAM memory, and extra features, namely an MPU, a greater number of timers and a dual bank Flash structure while remaining fully compatible with the other members of the family.

The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD, STM32F103xE, STM32F103xF and STM32F103xG are a drop-in replacement for the STM32F103x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices.

Table 3.

STM32F103xx family

Low-density

Medium-density

High-density devices

XL-density devices

devices

devices

16 KB

32 KB

64 KB

128 KB

256 KB

384 KB

512 KB

768 KB Flash

1 MB Flash

Pinout

Flash

Flash(1)

Flash

Flash

Flash

Flash

Flash

6 KB

10 KB

20 KB

20 KB

48 or

64 KB

64 KB

64 KB(2)

96 KB RAM

96 KB RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

144

5 × USARTs

5 × USARTs

10 × 16-bit timers,

100

4 × 16-bit timers,

2 × basic timers

2 × basic timers

3 × SPIs, 2 × I2Ss, 2 × I2Cs

3 × USARTs

3 × SPIs, 2 × I2Ss, 2 × I2Cs

USB, CAN, 2 × PWM timers

3 × 16-bit timers

USB, CAN, 2 × PWM timers

2 × USARTs

3 × ADCs, 2 × DACs, 1 × SDIO,

2 × SPIs, 2 × I2Cs,

3 × ADCs, 2 × DACs,

64

Cortex-M3 with MPU

2 × 16-bit timers

USB, CAN,

1 × SDIO

1 × SPI, 1 × I2C,

FSMC (100and 144-pin

1 × PWM timer

FSMC (100and 144-pin

USB, CAN,

packages(4)), dual bank Flash

packages(3))

2 × ADCs

memory

1 × PWM timer

2 × ADCs

48

36

1.For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices.

2.64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only.

3.Ports F and G are not available in devices delivered in 100-pin packages.

4.Ports F and G are not available in devices delivered in 100-pin packages.

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STM32F103xF, STM32F103xG	Description

2.3Overview

2.3.1ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

With its embedded ARM core, STM32F103xF and STM32F103xG performance line family is compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2Memory protection unit

The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

2.3.3Embedded Flash memory

768 Kbytes to 1 Mbyte of embedded Flash are available for storing programs and data. The Flash memory is organized as two banks. The first bank has a size of 512 Kbytes. The second bank is either 256 or 512 Kbytes depending on the device. This gives the device the capability of writing to one bank while executing code from the other bank (read-while-write capability).

2.3.4CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

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Description	STM32F103xF, STM32F103xG

2.3.5Embedded SRAM

96 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

2.3.6FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F103xF and STM32F103xG performance line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND.

Functionality overview:

●The three FSMC interrupt lines are ORed in order to be connected to the NVIC

●Write FIFO

●Code execution from external memory except for NAND Flash and PC Card

●The targeted frequency, fCLK, is HCLK/2, so external access is at 36 MHz when HCLK is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz

2.3.7LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.

2.3.8Nested vectored interrupt controller (NVIC)

The STM32F103xF and STM32F103xG performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

●Closely coupled NVIC gives low latency interrupt processing

●Interrupt entry vector table address passed directly to the core

●Closely coupled NVIC core interface

●Allows early processing of interrupts

●Processing of late arriving higher priority interrupts

●Support for tail-chaining

●Processor state automatically saved

●Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

2.3.9External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines.

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STM32F103xF, STM32F103xG	Description

2.3.10Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. See Figure 2 for details on the clock tree.

2.3.11Boot modes

At startup, boot pins are used to select one of three boot options:

●Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes.

●Boot from system memory

●Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1.

2.3.12Power supply schemes

●VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins.

●VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is used). VDDA and VSSA must be connected to VDD and VSS, respectively.

●VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

For more details on how to connect power pins, refer to Figure 10: Power supply scheme.

2.3.13Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher

than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.

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Description	STM32F103xF, STM32F103xG

2.3.14Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●MR is used in the nominal regulation mode (Run)

●LPR is used in the Stop modes.

●Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

2.3.15Low-power modes

The STM32F103xF and STM32F103xG performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

●Stop mode

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.

●Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

Note:	The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
	or Standby mode.

2.3.16 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to- peripheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

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STM32F103xF, STM32F103xG	Description

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced-control timers TIMx, DAC, I2S, SDIO and ADC.

2.3.17RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present.

They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.18Timers and watchdogs

The XL-density STM32F103xx performance line devices include up to two advanced-control timers, up to ten general-purpose timers, two basic timers, two watchdog timers and a SysTick timer.

Table 4 compares the features of the advanced-control, general-purpose and basic timers.

	Table 4.	STM32F103xF and STM32F103xG timer feature comparison
	Timer		Counter	Counter	Prescaler factor	DMA request	Capture/compare	Complementary
			resolution	type		generation	channels	outputs
				Up,	Any integer between
	TIM1, TIM8		16-bit	down,		Yes	4	Yes
					1 and 65536
				up/down
	TIM2, TIM3,			Up,	Any integer between
			16-bit	down,		Yes	4	No
	TIM4, TIM5				1 and 65536
				up/down
	TIM9, TIM12		16-bit	Up	Any integer between	No	2	No
					1 and 65536
	TIM10, TIM11		16-bit	Up	Any integer between	No	1	No
	TIM13, TIM14				1 and 65536
	TIM6, TIM7		16-bit	Up	Any integer between	Yes	0	No
					1 and 65536

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Description	STM32F103xF, STM32F103xG

Advanced-control timers (TIM1 and TIM8)

The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:

●Input capture

●Output compare

●PWM generation (edge or center-aligned modes)

●One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are10 synchronizable general-purpose timers embedded in the STM32F103xF and STM32F103xG performance line devices (see Table 4 for differences).

●TIM2, TIM3, TIM4, TIM5

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xF and STM32F103xG access line devices.

These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages.

Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

●TIM10, TIM11 and TIM9

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

●TIM13, TIM14 and TIM12

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13 and TIM14 feature one independent channel, whereas TIM12 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

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STM32F103xF, STM32F103xG	Description

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

●A 24-bit down counter

●Autoreload capability

●Maskable system interrupt generation when the counter reaches 0.

●Programmable clock source

2.3.19I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

2.3.20Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F103xF and STM32F103xG performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.

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Description	STM32F103xF, STM32F103xG

2.3.21Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

2.3.22Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 48 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

2.3.23SDIO

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD Memory Card Specifications Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital protocol Rev1.1.

2.3.24Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.

2.3.25Universal serial bus (USB)

The STM32F103xF and STM32F103xG performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

2.3.26GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.

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STM32F103xF, STM32F103xG	Description

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

2.3.27ADC (analog to digital converter)

Three 12-bit analog-to-digital converters are embedded into STM32F103xF and STM32F103xG performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

●Simultaneous sample and hold

●Interleaved sample and hold

●Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

2.3.28DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

●two DAC converters: one for each output channel

●8-bit or 12-bit monotonic output

●left or right data alignment in 12-bit mode

●synchronized update capability

●noise-wave generation

●triangular-wave generation

●dual DAC channel independent or simultaneous conversions

●DMA capability for each channel

●external triggers for conversion

●input voltage reference VREF+

Eight DAC trigger inputs are used in the STM32F103xF and STM32F103xG performance line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

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Description	STM32F103xF, STM32F103xG

2.3.29Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

2.3.30Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

2.3.31Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

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Doc ID 16554 Rev 3

STM32F103xF, STM32F103xG	Pinouts and pin descriptions

3 Pinouts and pin descriptions

Figure 3. STM32F103xF and STM32F103xG XL-density performance line BGA144 ballout

1

2

3

4

5

6

7

8

9

10

11

12

A

PC13-

PE3

PE2

PE1

PE0

PB4

PB3

PD6

PD7

PA15

PA14

PA13

JTRST

JTDO

JTDI

JTCK

JTMS

TAMPER-RTC

B

PC14-

PE4

PE5

PE6

PB9

PB5

PG15

PG12

PD5

PC11

PC10

PA12

OSC32_IN

C

PC15-

VBAT

PF0

PF1

PB8

PB6

PG14

PG11

PD4

PC12

NC

PA11

OSC32_OUT

D

OSC_IN

VSS_5

VDD_5

PF2

BOOT0

PB7

PG13

PG10

PD3

PD1

PA10

PA9

E

OSC_OUT

PF3

PF4

PF5

VSS_3

VSS_11

VSS_10

PG9

PD2

PD0

PC9

PA8

F

NRST

PF7

PF6

VDD_4

VDD_3

VDD_11

VDD_10

VDD_8

VDD_2

VDD_9

PC8

PC7

G

PF10

PF9

PF8

VSS_4

VDD_6

VDD_7

VDD_1

VSS_8

VSS_2

VSS_9

PG8

PC6

H

PC0

PC1

PC2

PC3

VSS_6

VSS_7

VSS_1

PE11

PD11

PG7

PG6

PG5

J

VSSA

PA0-WKUP

PA4

PC4

PB2/

PG1

PE10

PE12

PD10

PG4

PG3

PG2

BOOT1

K

VREF–

PA1

PA5

PC5

PF13

PG0

PE9

PE13

PD9

PD13

PD14

PD15

L

VREF+

PA2

PA6

PB0

PF12

PF15

PE8

PE14

PD8

PD12

PB14

PB15

M

VDDA

PA3

PA7

PB1

PF11

PF14

PE7

PE15

PB10

PB11

PB12

PB13

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Pinouts and pin descriptions	STM32F103xF, STM32F103xG

Figure 4. STM32F103xF and STM32F103xG XL-density performance line LQFP144 pinout

PE2	1
PE3	2
PE4	3
PE5	4
PE6	5
VBAT	6
PC13-TAMPER-RTC	7
PC14-OSC32_IN	8
PC15-OSC32_OUT	9
PF0	10
PF1	11
PF2	12
PF3	13
PF4	14
PF5	15
VSS_5	16
VDD_5	17
PF6	18
PF7	19
PF8	20
PF9	21
PF10	22
OSC_IN	23
OSC_OUT	24
NRST	25
PC0	26
PC1	27
PC2	28
PC3	29
VSSA	30
VREF-	31
VREF+	32
VDDA	33
PA0-WKUP	34
PA1	35
PA2	36

DD 3		SS 3			PE1			PE0
V		V
144		143			142			141

	37			38			39			40
PA3				SS 4			DD 4 PA4
			V			V

PB9		PB8			BOOT0			PB7		PB6			PB5			PB4			PB3			PG15			V				V				PG14		PG13			PG12			PG11			PG10
																										DD11				SS11
140		139			138			137			136			135			134			133			132			131				130			129			128			127			126			125

LQFP144

	41			42				43				44				45				46				47				48				49				50				51				52				53				54			55			56
PA5			PA6				PA7				PC4				PC5				PB0				PB1				PB2				PF11				PF12					VSS6			V				PF13			PF14				PF15			PG0
																																												DD6

PG9			PD7			PD6				DD 10				SS 10		PD5		PD4
									V				V
	124			123			122			121
														120			119		118

	57			58			59			60				61		62		63
PG1			PE7			PE8			PE9					SS 7		DD 7 PE10
													V			V

PD3				PD2				PD1				PD0				PC12				PC11				PC10				PA15 PA14
																																	109
	117				116				115				114				113					112				111				110
																																	108						VDD_2
																																	107
																																							VSS_2
																																	106
																																							NC
																																	105
																																							PA13
																																	104
																																							PA12
																																	103
																																							PA11
																																	102
																																							PA10
																																	101
																																							PA9
																																	100
																																							PA8
																																	99
																																							PC9
																																	98
																																							PC8
																																	97
																																							PC7
																																	96
																																							PC6
																																	95
																																							VDD_9
																																	94
																																							VSS_9
																																	93
																																							PG8
																																	92
																																							PG7
																																	91
																																							PG6
																																	90
																																							PG5
																																	89
																																							PG4
																																	88
																																							PG3
																																	87
																																							PG2
																																	86
																																							PD15
																																	85
																																							PD14
																																	84
																																							VDD_8
																																	83						VSS_8
																																							PD13
																																	82
																																							PD12
																																	81
																																							PD11
																																	80
																																							PD10
																																	79
																																	78						PD9
																																	77						PD8
																																	76						PB15
																																	75						PB14
																																	74						PB13
																																							PB12
																																	73
		64				65				66				67				68			69				70				71					72
	PE11				PE12				PE13				PE14				PE15					PB10				PB11				SS_1				DD_1
																														V			V

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STM32F103xF, STM32F103xG																			Pinouts and pin descriptions
	Figure 5. STM32F103xF and STM32F103xG XL-density performance line LQFP100
	pinout
		VDD 3	VSS 3	PE1	PE0	PB9	PB8	BOOT0	PB7	PB6	PB5	PB4	PB3	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0	PC12	PC11	PC10	PA15	PA14
	PE2	100	99	98	97	96	95	94	93	92	91	90	89	88	87	86	85	84	83	82	81	80	79	78	77	76
		1																								75	VDD_2
	PE3	2																								74	VSS_2
	PE4	3																								73	NC
	PE5	4																								72	PA 13
	PE6	5																								71	PA 12
	VBAT	6																								70	PA 11
	PC13-TAMPER-RTC 7																									69	PA 10
	PC14-OSC32_IN	8																								68	PA 9
	PC15-OSC32_OUT	9																								67	PA 8
	VSS_5	10																								66	PC9
	VDD_5	11																								65	PC8
	OSC_IN	12										LQFP100														64	PC7
	OSC_OUT	13																								63	PC6
	NRST	14																								62	PD15
	PC0	15																								61	PD14
	PC1	16																								60	PD13
	PC2	17																								59	PD12
	PC3	18																								58	PD11
	VSSA	19																								57	PD10
	VREF-	20																								56	PD9
	VREF+	21																								55	PD8
	VDDA	22																								54	PB15
	PA0-WKUP	23																								53	PB14
	PA1	24																								52	PB13
	PA2	25																								51	PB12
		26	27	28	29	30	31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50
		PA3	VSS 4	VDD 4	PA4	PA5	PA6	PA7	PC4	PC5	PB0	PB1	PB2	PE7	PE8	PE9	PE10	PE11	PE12	PE13	PE14	PE15	PB10	PB11	VSS 1	VDD 1
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Pinouts and pin descriptions

STM32F103xF, STM32F103xG

Figure 6. STM32F103xF and STM32F103xG XL-density performance line

LQFP64 pinout

VDD 3

VSS 3

PB9

PB8

BOOT0

PB7

PB6 PB5 PB4 PB3

PD2

PC12

PC11 PC10

PA15

PA14

VBAT

VDD_2

PC13-TAMPER-RTC

VSS_2

PC14-OSC32_IN

PA13

PC15-OSC32_OUT

PA12

PD0 OSC_IN

PA11

PD1 OSC_OUT

PA10

NRST

PA9

PC0

LQFP64

PA8

PC1

PC9

PC2

PC8

PC3

PC7

VSSA

PC6

VDDA

PB15

PA0-WKUP

PB14

PA1

PB13

PA2

PB12

PA3

VSS 4

VDD 4

PA4

PA5

PA6

PA7 PC4 PC5 PB0

PB1

PB2

PB10 PB11

VSS 1

VDD 1

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STM32F103xF, STM32F103xG								Pinouts and pin descriptions
Table 5.			STM32F103xF and STM32F103xG pin definitions
	Pins					(2)		Alternate functions(4)
					(1)	levelO/I	Main
LFBGA144	LQFP64	LQFP100	LQFP144
				Pin name	Type		function(3)	Default	Remap
							(after reset)
A3	-	1	1	PE2	I/O	FT	PE2	TRACECK / FSMC_A23
A2	-	2	2	PE3	I/O	FT	PE3	TRACED0 / FSMC_A19
B2	-	3	3	PE4	I/O	FT	PE4	TRACED1/ FSMC_A20
B3	-	4	4	PE5	I/O	FT	PE5	TRACED2/ FSMC_A21	TIM9_CH1
B4	-	5	5	PE6	I/O	FT	PE6	TRACED3 / FSMC_A22	TIM9_CH2
C2	1	6	6	VBAT	S		VBAT
A1	2	7	7	PC13-TAMPER-	I/O		PC13(6)	TAMPER-RTC
				RTC(5)
B1	3	8	8	PC14-OSC32_IN(5)	I/O		PC14(6)	OSC32_IN
C1	4	9	9	PC15-	I/O		PC15(6)	OSC32_OUT
				OSC32_OUT(5)
C3	-	-	10	PF0	I/O	FT	PF0	FSMC_A0
C4	-	-	11	PF1	I/O	FT	PF1	FSMC_A1
D4	-	-	12	PF2	I/O	FT	PF2	FSMC_A2
E2	-	-	13	PF3	I/O	FT	PF3	FSMC_A3
E3	-	-	14	PF4	I/O	FT	PF4	FSMC_A4
E4	-	-	15	PF5	I/O	FT	PF5	FSMC_A5
D2	-	10	16	VSS_5	S		VSS_5
D3	-	11	17	VDD_5	S		VDD_5
F3	-	-	18	PF6	I/O		PF6	ADC3_IN4 / FSMC_NIORD	TIM10_CH1
F2	-	-	19	PF7	I/O		PF7	ADC3_IN5 / FSMC_NREG	TIM11_CH1
G3	-	-	20	PF8	I/O		PF8	ADC3_IN6 / FSMC_NIOWR	TIM13_CH1
G2	-	-	21	PF9	I/O		PF9	ADC3_IN7 / FSMC_CD	TIM14_CH1
G1	-	-	22	PF10	I/O		PF10	ADC3_IN8 / FSMC_INTR
D1	5	12	23	OSC_IN	I		OSC_IN		PD0(7)
E1	6	13	24	OSC_OUT	O		OSC_OUT		PD1(7)
F1	7	14	25	NRST	I/O		NRST
H1	8	15	26	PC0	I/O		PC0	ADC123_IN10
H2	9	16	27	PC1	I/O		PC1	ADC123_IN11
H3	10	17	28	PC2	I/O		PC2	ADC123_IN12
H4	11	18	29	PC3	I/O		PC3	ADC123_IN13
J1	12	19	30	VSSA	S		VSSA
K1	-	20	31	VREF-	S		VREF-

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Pinouts and pin descriptions								STM32F103xF, STM32F103xG
Table 5.			STM32F103xF and STM32F103xG pin definitions (continued)
	Pins					(2)		Alternate functions(4)
					(1)	levelO/I	Main
LFBGA144	LQFP64	LQFP100	LQFP144
				Pin name	Type		function(3)	Default	Remap
							(after reset)
L1	-	21	32	VREF+	S		VREF+
M1	13	22	33	VDDA	S		VDDA
								WKUP/USART2_CTS(8) /
J2	14	23	34	PA0-WKUP	I/O		PA0	ADC123_IN0 / TIM2_CH1_ETR /
								TIM5_CH1 / TIM8_ETR
K2	15	24	35	PA1	I/O		PA1	USART2_RTS(7) / ADC123_IN1 /
								TIM5_CH2 / TIM2_CH2(7)
								USART2_TX(7) / TIM5_CH3 /
L2	16	25	36	PA2	I/O		PA2	ADC123_IN2 / TIM9_CH1 /
								TIM2_CH3 (7)
								USART2_RX(7) / TIM5_CH4 /
M2	17	26	37	PA3	I/O		PA3	ADC123_IN3 / TIM2_CH4(7)/
								TIM9_CH2
G4	18	27	38	VSS_4	S		VSS_4
F4	19	28	39	VDD_4	S		VDD_4
J3	20	29	40	PA4	I/O		PA4	SPI1_NSS(7) / USART2_CK(7) /
								DAC_OUT1 / ADC12_IN4
K3	21	30	41	PA5	I/O		PA5	SPI1_SCK(7) / DAC_OUT2 /
								ADC12_IN5
								SPI1_MISO(7) / TIM8_BKIN /
L3	22	31	42	PA6	I/O		PA6	ADC12_IN6 / TIM3_CH1(7)/	TIM1_BKIN
								TIM13_CH1
								SPI1_MOSI(7)/ TIM8_CH1N /
M3	23	32	43	PA7	I/O		PA7	ADC12_IN7 / TIM3_CH2(7) /	TIM1_CH1N
								TIM14_CH1
J4	24	33	44	PC4	I/O		PC4	ADC12_IN14
K4	25	34	45	PC5	I/O		PC5	ADC12_IN15
L4	26	35	46	PB0	I/O		PB0	ADC12_IN8 / TIM3_CH3 /	TIM1_CH2N
								TIM8_CH2N
M4	27	36	47	PB1	I/O		PB1	ADC12_IN9 / TIM3_CH4(7) /	TIM1_CH3N
								TIM8_CH3N
J5	28	37	48	PB2	I/O	FT	PB2/BOOT1
M5	-	-	49	PF11	I/O	FT	PF11	FSMC_NIOS16
L5	-	-	50	PF12	I/O	FT	PF12	FSMC_A6
H5	-	-	51	VSS_6	S		VSS_6
G5	-	-	52	VDD_6	S		VDD_6
K5	-	-	53	PF13	I/O	FT	PF13	FSMC_A7

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