ST ST72324LJ6, ST72324LK6, ST72324LJ4, ST72324LK4, ST72324LS4 User Manual

ST72324Lxx

3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface

Features

■Memories

–8 to 32K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and InCircuit Programming for HDFlash devices

–384 to 1K bytes RAM

–HDFlash endurance: 100 cycles, data retention: 40 years at 85°C

■Clock, Reset And Supply Management

–Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock

–PLL for 2x frequency multiplication

–Four power saving modes: Halt, Active-Halt, Wait and Slow

■Interrupt Management

–Nested interrupt controller

–10 interrupt vectors plus TRAP and RESET

–9/6 external interrupt lines (on 4 vectors)

■Up to 32 I/O Ports

–32/24 multifunctional bidirectional I/O lines

–22/17 alternate function lines

–12/10 high sink outputs

■4 Timers

–Main Clock Controller with: Real time base, Beep and Clock-out capabilities

–Configurable watchdog timer

–16-bit Timer A with: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes

–16-bit Timer B with: 2 input captures, 2 output compares, PWM and pulse generator modes

Table 1. Device Summary

LQFP32 LQFP44 7 x 7 10 x 10

LQFP48	SDIP32
7 x 7	400 mil

■2 Communication Interfaces

–SPI synchronous serial interface

–SCI asynchronous serial interface

■1 Analog Peripheral

–10-bit ADC with up to 12 input ports

■Instruction Set

–8-bit Data Manipulation

–63 Basic Instructions

–17 main Addressing Modes

–8 x 8 Unsigned Multiply Instruction

■Development Tools

–Full hardware/software development package

–In-Circuit Testing capability

Features	ST72324LJ6		ST72324LJ4		ST72324LJ2
			ST72324LK4		ST72324LK2
	ST72324LK6
			ST72324LS4		ST72324LS2
Program memory -	Flash 32K		Flash/ROM 16K		Flash/ROM 8K
bytes
RAM (stack) - bytes	1024 (256)		512 (256)		384 (256)
Voltage Range			2.85 to 3.6V
Temp. Range			up to -40°C to +85°C
Packages		LQFP44 10x10 (J), LQFP48 7x7 (S), SDIP32, LQFP32 7x7 (K)

Rev. 5

September 2007

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Table of Contents

1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
5.2	MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
5.3	CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			23
6.1	PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
6.2	MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24
6.3	RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
	6.3.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
	6.3.3	External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	6.3.4	Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			26

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 33

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		35
8.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
8.2	SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
8.3	WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
8.4	ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37

8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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9.2	FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		40
	9.2.1	Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
	9.2.2	Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
	9.2.3	Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
9.3	I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
9.4	LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
9.5	INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
	9.5.1	I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 50

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 84
10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	86
10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	93
10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	93
10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	94
10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	100

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	104
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	104

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

	12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	111
	12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	111
	12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	112
12.3	OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	112
12.4	SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	113
	12.4.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	113
	12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	115
	12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	115
12.5	CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	116
	12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	116
	12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	116
	12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	117
	12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	118
	12.5.5 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	119
12.6	MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	120
	12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	120
	12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	120

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Table of Contents

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

121

12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 121 12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 123 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		129
12.11	COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . .	130
12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		130
12.12	10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	132
12.12.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		133
12.12.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		133
12.12.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		135
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		136
13.1	PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	136
13.2	THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	138
13.3	SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	139
14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . .		140
14.1	FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	140
14.2	DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . .	142
14.3	DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	145
14.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		145
14.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		145
14.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		145
14.3.4 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		146
14.4	ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	147

15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15.1.1 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.1.2 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . 149 15.1.4 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.1.5 ADC Conversion Spurious Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.1.6 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.1.7 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

15.2 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

15.2.1 I/O Port A and F Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 15.3 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

15.3.1 Timer A Restrictions in Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 15.3.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 15.3.3 39-Pulse ICC Entry Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

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ST72324Lxx

1 DESCRIPTION

The ST72F324L and ST72324BL devices are members of the ST7 microcontroller family designed for mid-range applications running at 3.3V. Different package options offer up to 32 I/O pins. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers,

Figure 1. Device Block Diagram

enabling the design of highly efficient and compact application code.

The on-chip peripherals include an A/D converter, 2 general purpose timers, an SPI interface and an SCI interface.

For power economy, microcontroller can switch dynamically into WAIT, SLOW, ACTIVE-HALT or HALT mode when the application is in idle or stand-by state.

Typical applications are consumer, home, office and industrial products.

8-BIT CORE

ALU

RESET

CONTROL

VPP

VSS

VDD

OSC1

OSC2

OSC

MCC/RTC/BEEP

PF7:6,4,2:0

PORT F

(6 bits on J and S devices)

TIMER A

(5 bits on K devices)

BEEP

PE1:0

PORT E

(2 bits)

SCI

PD5:0

PORT D

(6 bits on J and S devices)

10-BIT ADC

(2 bits on K devices)

VAREF

VSSA

BUS DATA AND ADDRESS

PROGRAM

MEMORY

(8K - 32K Bytes)

RAM

(384 - 2048 Bytes)

WATCHDOG

PORT A

PORT B

PORT C

TIMER B

SPI

PA7:3

(5 bits on J and S devices) (4 bits on K devices)

PB4:0

(5 bits on J and S devices) (3 bits on K devices)

PC7:0 (8 bits)

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3

ST72324Lxx

2 PIN DESCRIPTION

Figure 2. 48-Pin LQFP 7x7 Device Pinout

		PE1/RDI PE0/ TDO	2	2		RESET	/ICCSEL	PA6(HS) PA5(HS)	PA4(HS)
			V OSC1	OSC2 V			V (HS)PA7
			DD	SS			PP
NC	48 47 46 45			44 43 42 41 40 39 38 37
	1								36 VSS_1
NC	2								35	VDD_1
PB0	3								34	PA3 (HS)
PB1	4	ei2							33	NC
PB2	5								32	PC7 /	SS	/ AIN15
PB3	6	ei3						ei0	31	PC6 / SCK / ICCCLK
(HS) PB4	7								30	PC5 / MOSI / AIN14
NC	8								29	PC4 / MISO / ICCDATA
AIN0 / PD0	9								28	PC3 (HS) / ICAP1_B
AIN1 / PD1	10								27	PC2 (HS) / ICAP2_B
AIN3 / PD2	11		ei1						26	PC1 / OCMP1_B / AIN13
AIN4 / PD3	12								25	PC0 / OCMP2_B / AIN12
	13 14 15 16 17 18 19 20 21 22 23 24

Legend

NC = Not Connected (not bonded)

AIN4 / PD4	AIN5 / PD5	V	V	/MCOAIN8 / PF0	BEEP/ (HS) PF1	(HS) PF2	/AOCMP1AIN10 / PF4	AICAP1/ (HS) PF6	AEXTCLK/ (HS) PF7	V	V
		AREF	SSA							DD0	SS0

(HS)	20mA high sink capability
eix	associated external interrupt vector

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ST72324Lxx

Figure 3. 44-Pin LQFP Package Pinout

PE0/ TDO

2

OSC1

OSC2

2

RESET

/ ICCSEL

PA7(HS)

PA6(HS)

PA5(HS)

PA4(HS)

V

V

V

DD

SS

PP

RDI / PE1

44 43 42 41 40 39 38 37 36 35 34

VSS_1

1

33

PB0

2

32

VDD_1

PB1

3

ei2

ei0

31

PA3 (HS)

PB2

4

30

PC7 / SS / AIN15

PB3

5

29

PC6 / SCK / ICCCLK

(HS) PB4

6

ei3

28

PC5 / MOSI / AIN14

AIN0 / PD0

7

27

PC4 / MISO / ICCDATA

AIN1 / PD1

8

26

PC3 (HS) / ICAP1_B

AIN2 / PD2

9

25

PC2 (HS) / ICAP2_B

AIN3 / PD3

10

ei1

24

PC1 / OCMP1_B / AIN13

AIN4 / PD4

11

23

PC0 / OCMP2_B / AIN12

12 13 14 15 16 17 18 19 20 21 22

AIN5 / PD5

AREF

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

OCMP1 A / AIN10 / PF4

ICAP1 A / (HS) PF6

EXTCLK A / (HS) PF7

DD_0

SS_0

V

V

V

V

eix associated external interrupt vector

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1

ST72324Lxx

PIN DESCRIPTION (Cont’d)

Figure 4. 32-Pin SDIP Package Pinout

(HS) PB4

PB3

1

ei3

ei2

32

AIN0 / PD0

PB0

2

31

AIN1 / PD1

PE1 / RDI

3

30

VAREF

4

29

PE0 / TDO

VSSA

5

28

VDD_2

MCO / AIN8 / PF0

6

ei1

27

OSC1

BEEP / (HS) PF1

7

26

OSC2

OCMP1_A / AIN10 / PF4

8

25

VSS_2

ICAP1_A / (HS) PF6

9

24

RESET

EXTCLK_A / (HS) PF7

10

23

VPP / ICCSEL

AIN12 / OCMP2_B / PC0

11

22

PA7 (HS)

AIN13 / OCMP1_B / PC1

12

21

PA6 (HS)

ICAP2_B / (HS) PC2

13

20

PA4 (HS)

ICAP1_B / (HS) PC3

14

ei0

19

PA3 (HS)

ICCDATA/ MISO / PC4

PC7 /

/ AIN15

15

18

SS

AIN14 / MOSI / PC5

16

17

PC6 / SCK / ICCCLK

(HS)

8mA high sink capability

eix

associated external interrupt vector

Figure 5. 32-Pin LQFP 7x7 Package Pinout

/ AIN1

/ AIN0

(HS)

PB3 PB0

/ RDI

/ TDO

_2

PD1

PD0

PB4

PE1

PE0

V

DD

VAREF

32 31 30

29 28 27 26 25

OSC1

1

ei3

ei2

24

VSSA

2

23

OSC2

MCO / AIN8 / PF0

3

22

VSS_2

BEEP / (HS) PF1

ei1

21

4

RESET

OCMP1_A / AIN10 / PF4

5

20

VPP / ICCSEL

ICAP1_A / (HS) PF6

6

19

PA7 (HS)

EXTCLK_A / (HS) PF7

7

18

PA6 (HS)

AIN12 / OCMP2_B / PC0

8

ei0 17

PA4 (HS)

9

10 11 12 13 14 15 16

AIN13 / OCMP1 B / PC1	ICAP2 B / (HS) PC2	ICAP1 B / (HS) PC3	ICCDATA / MISO / PC4	AIN14 / MOSI / PC5	ICCCLK / SCK / PC6		AIN15 / SS / PC7	(HS) PA3

(HS) 8mA high sink capability

eix associated external interrupt vector

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1

ST72324Lxx

PIN DESCRIPTION (Cont’d)

For more details, refer to “ELECTRICAL CHARACTERISTICS” on page 110

Legend / Abbreviations for Table 2:

Type:		I = input, O = output, S = supply
In/Output level: C = CMOS
Output level:		CT= CMOS with input trigger
		HS = high sink (on N-buffer only)
Port and control configuration:
–	Input:	float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog ports
–	Output:	OD = open drain 2), PP = push-pull

Refer to “I/O PORTS” on page 40 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.

Table 2. Device Pin Description

Pin n°

Level

Port

Main

Type

LQFP48

LQFP44

LQFP32

SDIP32

Pin Name

Input

Output

float

Input

ana

Output

function

Alternate Function

wpu

int

OD

PP

(after

reset)

7

6

30

1

PB4 (HS)

I/O

CT

HS

X

ei3

X

X

Port B4

9

7

31

2

PD0/AIN0

I/O

CT

X

X

X

X

X

Port D0

ADC Analog Input 0

10

8

32

3

PD1/AIN1

I/O

CT

X

X

X

X

X

Port D1

ADC Analog Input 1

11

9

PD2/AIN2

I/O

CT

X

X

X

X

X

Port D2

ADC Analog Input 2

12

10

PD3/AIN3

I/O

CT

X

X

X

X

X

Port D3

ADC Analog Input 3

13

11

PD4/AIN4

I/O

CT

X

X

X

X

X

Port D4

ADC Analog Input 4

14

12

PD5/AIN5

I/O

CT

X

X

X

X

X

Port D5

ADC Analog Input 5

15

13

1

4

VAREF

S

Analog

Reference Voltage for ADC5)

16

14

2

5

VSSA

S

Analog Ground Voltage5)

17

15

3

6

PF0/MCO/AIN8

I/O

CT

X

ei1

X

X

X

Port F0

Main clock

ADC Analog

out (fOSC/2)

Input 8

18

16

4

7

PF1 (HS)/BEEP

I/O

CT

HS

X

ei1

X

X

Port F1

Beep signal output

19

17

PF2 (HS)

I/O

CT

HS

X

ei1

X

X

Port F2

PF4/OCMP1_A/

X

Timer A Out-

ADC Analog

20

18

5

8

AIN10

I/O

CT

X

X

X

X

Port F4

put Com-

Input 10

pare 1

21

19

6

9

PF6 (HS)/ICAP1_A

I/O

CT

HS

X

X

X

X

Port F6

Timer A Input Capture 1

22

20

7

10

PF7 (HS)/

I/O

CT

HS

X

X

X

X

Port F7

Timer A External Clock

EXTCLK_A

Source

23

21

VDD_0

S

Digital Main Supply Voltage5)

24

22

VSS_0

S

Digital Ground Voltage5)

PC0/OCMP2_B/

X

Timer B Out-

ADC Analog

25

23

8

11

AIN12

I/O

CT

X

X

X

X

Port C0

put Com-

Input 12

pare 2

PC1/OCMP1_B/

X

Timer B Out-

ADC Analog

26

24

9

12

AIN13

I/O

CT

X

X

X

X

Port C1

put Com-

Input 13

pare 1

10/154

1

ST72324Lxx

Pin n°

Level

Port

Main

Type

LQFP48

LQFP44

LQFP32

SDIP32

Pin Name

Input

Output

float

Input

ana

Output

function

Alternate Function

wpu

int

OD

PP

(after

reset)

27

25

10

13

PC2 (HS)/ICAP2_B

I/O

CT

HS

X

X

X

X

Port C2

Timer B Input Capture 2

28

26

11

14

PC3 (HS)/ICAP1_B

I/O

CT

HS

X

X

X

X

Port C3

Timer B Input Capture 1

PC4/MISO/ICCDA-

SPI Master

ICC Data In-

29

27

12

15

I/O

CT

X

X

X

X

Port C4

In / Slave

TA

put

Out Data

SPI Master

ADC Analog

30

28

13

16

PC5/MOSI/AIN14

I/O

CT

X

X

X

X

X

Port C5

Out / Slave

Input 14

In Data

31

29

14

17

PC6/SCK/ICCCLK

I/O

CT

X

X

X

X

Port C6

SPI Serial

ICC Clock

Clock

Output

SPI Slave

ADC Analog

32

30

15

18

PC7/SS/AIN15

I/O

CT

X

X

X

X

X

Port C7

Select (ac-

Input 15

tive low)

34

31

16

19

PA3 (HS)

I/O

CT

HS

X

ei0

X

X

Port A3

35

32

VDD_1

S

Digital Main Supply Voltage5)

36

33

VSS_1

S

Digital Ground Voltage5)

37

34

17

20

PA4 (HS)

I/O

CT

HS

X

X

X

X

Port A4

38

35

PA5 (HS)

I/O

CT

HS

X

X

X

X

Port A5

39

36

18

21

PA6 (HS)

I/O

CT

HS

X

T

Port A6 1)

40

37

19

22

PA7 (HS)

I/O

CT

HS

X

T

Port A7 1)

Must be tied low. In the flash pro-

gramming mode, this pin acts as the

41

38

20

23

VPP /ICCSEL

I

programming voltage input VPP. See

Section 12.9.2 for more details. High

voltage must not be applied to ROM

devices.

42

39

21

24

I/O

CT

Top priority non maskable interrupt.

RESET

43

40

22

25

VSS_2

S

Digital Ground Voltage5)

44

41

23

26

OSC2

O

Resonator oscillator inverter output

45

42

24

27

OSC1

I

External clock input or Resonator os-

cillator inverter input

46

43

25

28

VDD_2

S

Digital Main Supply Voltage5)

47

44

26

29

PE0/TDO

I/O

CT

X

X

X

X

Port E0

SCI Transmit Data Out

48

1

27

30

PE1/RDI

I/O

CT

X

X

X

X

Port E1

SCI Receive Data In

3

2

28

31

PB0

I/O

CT

X

ei2

X

X

Port B0

4

3

PB1

I/O

CT

X

ei2

X

X

Port B1

5

4

PB2

I/O

CT

X

ei2

X

X

Port B2

6

5

29

32

PB3

I/O

CT

X

ei2

X

X

Port B3

Notes:

1.In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2.In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD

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are not implemented). See See “I/O PORTS” on page 40. and Section 12.8 I/O PORT PIN CHARACTERISTICS for more details.

3.OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 2 PIN DESCRIPTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details.

4.On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

5.It is mandatory to connect all available VDD and VREF pins to the supply voltage and all VSS and VSSA pins to ground.

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3 REGISTER & MEMORY MAP

As shown in Figure 6, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 1024 bytes of RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

Figure 6. Memory Map

The highest address bytes contain the user reset and interrupt vectors.

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.

0000h		0080h
	HW Registers		Short Addressing
	(see Table 3)
007Fh			RAM (zero page)
		00FFh
0080h
	RAM	0100h	256 Bytes Stack
	(1024,
		01FFh
	512 or 384 Bytes)
087Fh		0200h	16-bit Addressing
0880h
	Reserved		RAM
		027Fh
7FFFh
		or 047Fh
8000h
	Program Memory			8000h	32 KBytes
	(32K, 16K or 8K)			C000h
FFDFh					16 KBytes
FFE0h	Interrupt & Reset Vectors			E000h
					8 Kbytes
	(see Table 9)
FFFFh				FFFFh

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Table 3. Hardware Register Map

Address	Block	Register	Register Name	Reset	Remarks
		Label		Status
0000h	Port A 2)	PADR	Port A Data Register	00h1)	R/W
0001h		PADDR	Port A Data Direction Register	00h	R/W
0002h		PAOR	Port A Option Register	00h	R/W
0003h	Port B 2)	PBDR	Port B Data Register	00h1)	R/W
0004h		PBDDR	Port B Data Direction Register	00h	R/W
0005h		PBOR	Port B Option Register	00h	R/W
0006h		PCDR	Port C Data Register	00h1)	R/W
0007h	Port C	PCDDR	Port C Data Direction Register	00h	R/W
0008h		PCOR	Port C Option Register	00h	R/W
0009h	Port D 2)	PDADR	Port D Data Register	00h1)	R/W
000Ah		PDDDR	Port D Data Direction Register	00h	R/W
000Bh		PDOR	Port D Option Register	00h	R/W
000Ch		PEDR	Port E Data Register	00h1)	R/W
000Dh	Port E 2)	PEDDR	Port E Data Direction Register	00h	R/W2)
000Eh		PEOR	Port E Option Register	00h	R/W2)
000Fh	Port F 2)	PFDR	Port F Data Register	00h1)	R/W
0010h		PFDDR	Port F Data Direction Register	00h	R/W
0011h		PFOR	Port F Option Register	00h	R/W
0012h
to			Reserved Area (15 Bytes)
0020h
0021h		SPIDR	SPI Data I/O Register	xxh	R/W
0022h	SPI	SPICR	SPI Control Register	0xh	R/W
0023h		SPICSR	SPI Control/Status Register	00h	R/W
0024h		ISPR0	Interrupt Software Priority Register 0	FFh	R/W
0025h		ISPR1	Interrupt Software Priority Register 1	FFh	R/W
0026h	ITC	ISPR2	Interrupt Software Priority Register 2	FFh	R/W
0027h		ISPR3	Interrupt Software Priority Register 3	FFh	R/W
0028h		EICR	External Interrupt Control Register	00h	R/W
0029h	FLASH	FCSR	Flash Control/Status Register	00h	R/W
002Ah	WATCHDOG	WDGCR	Watchdog Control Register	7Fh	R/W
002Bh			Reserved Area (1 Byte)
002Ch	MCC	MCCSR	Main Clock Control / Status Register	00h	R/W
002Dh		MCCBCR	Main Clock Controller: Beep Control Register	00h	R/W
002Eh
to			Reserved Area (3 Bytes)
0030h
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Address	Block	Register	Register Name	Reset	Remarks
		Label		Status
0031h		TACR2	Timer A Control Register 2	00h	R/W
0032h		TACR1	Timer A Control Register 1	00h	R/W
0033h		TACSR	Timer A Control/Status Register3)4)	xxxx x0xxb	R/W
0034h		TAIC1HR	Timer A Input Capture 1 High Register	xxh	Read Only
0035h		TAIC1LR	Timer A Input Capture 1 Low Register	xxh	Read Only
0036h		TAOC1HR	Timer A Output Compare 1 High Register	80h	R/W
0037h		TAOC1LR	Timer A Output Compare 1 Low Register	00h	R/W
0038h	TIMER A	TACHR	Timer A Counter High Register	FFh	Read Only
0039h		TACLR	Timer A Counter Low Register	FCh	Read Only
003Ah		TAACHR	Timer A Alternate Counter High Register	FFh	Read Only
003Bh		TAACLR	Timer A Alternate Counter Low Register	FCh	Read Only
003Ch		TAIC2HR	Timer A Input Capture 2 High Register3)	xxh	Read Only
003Dh		TAIC2LR	Timer A Input Capture 2 Low Register3)	xxh	Read Only
003Eh		TAOC2HR	Timer A Output Compare 2 High Register4)	80h	R/W
003Fh		TAOC2LR	Timer A Output Compare 2 Low Register4)	00h	R/W
0040h			Reserved Area (1 Byte)
0041h		TBCR2	Timer B Control Register 2	00h	R/W
0042h		TBCR1	Timer B Control Register 1	00h	R/W
0043h		TBCSR	Timer B Control/Status Register	xxxx x0xxb	R/W
0044h		TBIC1HR	Timer B Input Capture 1 High Register	xxh	Read Only
0045h		TBIC1LR	Timer B Input Capture 1 Low Register	xxh	Read Only
0046h		TBOC1HR	Timer B Output Compare 1 High Register	80h	R/W
0047h		TBOC1LR	Timer B Output Compare 1 Low Register	00h	R/W
0048h	TIMER B	TBCHR	Timer B Counter High Register	FFh	Read Only
0049h		TBCLR	Timer B Counter Low Register	FCh	Read Only
004Ah		TBACHR	Timer B Alternate Counter High Register	FFh	Read Only
004Bh		TBACLR	Timer B Alternate Counter Low Register	FCh	Read Only
004Ch		TBIC2HR	Timer B Input Capture 2 High Register	xxh	Read Only
004Dh		TBIC2LR	Timer B Input Capture 2 Low Register	xxh	Read Only
004Eh		TBOC2HR	Timer B Output Compare 2 High Register	80h	R/W
004Fh		TBOC2LR	Timer B Output Compare 2 Low Register	00h	R/W
0050h		SCISR	SCI Status Register	C0h	Read Only
0051h		SCIDR	SCI Data Register	xxh	R/W
0052h		SCIBRR	SCI Baud Rate Register	00h	R/W
0053h	SCI	SCICR1	SCI Control Register 1	x000 0000h	R/W
0054h		SCICR2	SCI Control Register 2	00h	R/W
0055h		SCIERPR	SCI Extended Receive Prescaler Register	00h	R/W
0056h			Reserved area	---
0057h		SCIETPR	SCI Extended Transmit Prescaler Register	00h	R/W
0058h
to			Reserved Area (24 Bytes)
006Fh
0070h		ADCCSR	Control/Status Register	00h	R/W
0071h	ADC	ADCDRH	Data High Register	00h	Read Only
0072h		ADCDRL	Data Low Register	00h	Read Only
0073h			Reserved Area (13 Bytes)
007Fh
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Legend: x=undefined, R/W=read/write

Notes:

1.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2.The bits associated with unavailable pins must always keep their reset value.

3.The Timer A Input Capture 2 pin is not available (not bonded).

– In Flash devices:

The TAIC2HR and TAIC2LR registers are not present. Bit 4 of the TACSR register (ICF2) is forced by hardware to 0. Consequently, the corresponding interrupt cannot be used.

4. The Timer A Output Compare 2 pin is not available (not bonded).

– In ROM devices:

The TAOC2HR and TAOC2LR Registers can be used in PWM mode or for timebase generation.

– In Flash devices:

The TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values. Bit 3 of the TACSR register (OCF2) is forced by hardware to 0. Consequently, the corresponding interrupt cannot be used.

Caution: The TAIC2HR and TAIC2LR registers and the ICF2 and OCF2 flags are not present in the ST72F324L but are present in the emulator. For compatibility with the emulator, it is recommended to perform a dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.

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4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply.

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■Three Flash programming modes:

–Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased.

–ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board.

–IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.

■ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM

■Read-out protection

■Register Access Security System (RASS) to prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can be used for both code and data storage.

Figure 7. Memory Map and Sector Address

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 4). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 7). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 4. Sectors available in Flash devices

Flash Size (bytes)	Available Sectors
4K	Sector 0
8K	Sectors 0,1
> 8K	Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased.

Read-out protection selection depends on the device type:

–In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

–In ROM devices it is enabled by mask option specified in the Option List.

4K

8K

10K

16K

24K

32K

48K

60K

FLASH

MEMORY SIZE

1000h

3FFFh

7FFFh

9FFFh

SECTOR 2

BFFFh

D7FFh

52 Kbytes

DFFFh

2 Kbytes

8 Kbytes

16 Kbytes

24 Kbytes

40 Kbytes

EFFFh

4 Kbytes

SECTOR 1

FFFFh

4 Kbytes

SECTOR 0

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FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a minimum of 5 and up to 6 pins to be connected to the programming tool (see Figure 8). These pins are:

–RESET: device reset

–VSS: device power supply ground

–ICCCLK: ICC output serial clock pin

–ICCDATA: ICC input/output serial data pin

–ICCSEL/VPP: programming voltage

–OSC1(or OSCIN): main clock input for external source

–VDD: application board power supply (optional, see Figure 8, Note 3)

Figure 8. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

APPLICATION BOARD

(See Note 3)

APPLICATION

POWER SUPPLY

		OSC2
V
DD

		(See Note 4)
												9				7			5			3			1
												10				8			6			4			2
									10kΩ

OSC1	V	ICCSEL/VPP	RESET	ICCCLK	ICCDATA
	SS
	ST7

ICC CONNECTOR

HE10 CONNECTOR TYPE

APPLICATION

RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

Notes:

1.If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2.During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-

agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3.The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4.External clock ICC entry mode is mandatory in this device. Pin 9 must be connected to the OSC1 or OSCIN pin of the ST7 and OSC2 must be grounded.

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FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool using 36-pulse mode.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 8). For more details on the pin locations, refer to the device pinout description.

4.6 IAP (In-Application Programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is

possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.

4.7.1 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 0000 0000 (00h)

7							0
0	0	0	0	0	0	0	0

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

Table 5. Flash Control/Status Register Address and Reset Value

	Address	Register	7	6	5	4	3	2	1	0
	(Hex.)	Label
	0029h	FCSR
		Reset Value	0	0	0	0	0	0	0	0

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5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■Enable executing 63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes (with indirect addressing mode)

■Two 8-bit index registers

■16-bit stack pointer

■Low power HALT and WAIT modes

■Priority maskable hardware interrupts

■Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The six CPU registers shown in Figure 9 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Figure 9. CPU Registers

											7												0
																										ACCUMULATOR
														RESET VALUE = XXh
											7												0
																										X INDEX REGISTER
													RESET VALUE = XXh
											7												0
																										Y INDEX REGISTER
													RESET VALUE = XXh
					PCH			8					7				PCL						0			PROGRAM COUNTER
	15
	RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
											7												0
														1	1	I1	H		I0	N		Z	C			CONDITION CODE REGISTER
				RESET VALUE = 1											1	1 X			1 X			X	X
		15						8															0			STACK POINTER
												7
RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

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CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write

Reset Value: 111x1xxx

7							0
1	1	I1	H	I0	N	Z	C

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0:No half carry has occurred.

1:A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7th bit.

0:The result of the last operation is positive or null.

1:The result of the last operation is negative (that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0:The result of the last operation is different from zero.

1:The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0:No overflow or underflow has occurred.

1:An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

Interrupt Software Priority		I1	I0
Level 0	(main)	1	0
Level 1		0	1
Level 2		0	0
Level 3	(= interrupt disable)	1	1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

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CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

15							8
0	0	0	0	0	0	0	1
7							0
SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 10).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

Figure 10. Stack Manipulation Example

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 10.

–When an interrupt is received, the SP is decremented and the context is pushed on the stack.

–On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

CALL	Interrupt	PUSH Y	POP Y	IRET	RET
Subroutine	Event				or RSP

@ 0100h

SP

SP

SP

Y

CC

CC

CC

A

A

A

X

X

X

SP

PCH

PCH

PCH

SP

PCL

PCL

PCL

PCH

PCH

PCH

PCH

PCH

SP

@ 01FFh PCL

PCL

PCL

PCL

PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

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6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 11.

For more details, refer to dedicated parametric section.

Main features

■Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator)

■Reset Sequence Manager (RSM)

■Multi-Oscillator Clock Management (MO)

–5 Crystal/Ceramic resonator oscillators

–1 Internal RC oscillator

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply

the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL

is disabled, then fOSC2 = fOSC/2.

Caution: The PLL is not recommended for applications where timing accuracy is required. See Section 6.1 on page 23.

Caution: The PLL must not be used with the internal RC oscillator.

Figure 11. Clock, Reset and Supply Block Diagram

				PLL Block
	OSC2	MULTI-	fOSC	PLL x 2	0	MAIN CLOCK	fCPU
						CONTROLLER
		OSCILLATOR
					fOSC2	WITH REALTIME
	OSC1			/ 2
		(MO)				CLOCK (MCC/RTC)
					1
					PLL OPTION BIT
		RESET SEQUENCE
	RESET	MANAGER				WATCHDOG
		(RSM)				TIMER (WDG)

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6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by three different source types coming from the multioscillator block:

■an external source

■4 crystal or ceramic resonator oscillators

■an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 6. Refer to the electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 14.1 on page 140 for more details on the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing.

In this mode, the two oscillator pins have to be tied to ground.

Table 6. ST7 Clock Sources

	Hardware Configuration
External Clock	ST7
	OSC1	OSC2
	EXTERNAL
	SOURCE
Resonators	ST7
	OSC1	OSC2
Crystal/Ceramic	CL1	CL2
	LOAD
	CAPACITORS
Internal RC Oscillator	ST7
	OSC1	OSC2

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6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

The reset sequence manager includes two RESET sources as shown in Figure 13:

■External RESET source pulse

■Internal WATCHDOG RESET

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases as shown in Figure 12:

■Active Phase depending on the RESET source

■256 or 4096 CPU clock cycle delay (selected by option byte)

■RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application.

The RESET vector fetch phase duration is 2 clock cycles.

Figure 12. RESET Sequence Phases

RESET

	Active Phase	INTERNAL RESET	FETCH
		256 or 4096 CLOCK CYCLES	VECTOR

6.3.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchro-

nous and therefore the MCU can enter reset state even in HALT mode.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

6.3.3 External Power-On RESET

To start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency.

A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin.

6.3.4 Internal Watchdog RESET

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

Figure 13. Reset Block Diagram

VDD

RON

Filter

INTERNAL

RESET

RESET

PULSE

WATCHDOG RESET

GENERATOR

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7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management provides the following features:

■Hardware interrupts

■Software interrupt (TRAP)

■Nested or concurrent interrupt management with flexible interrupt priority and level management:

–Up to 4 software programmable nesting levels

–Up to 16 interrupt vectors fixed by hardware

–2 non maskable events: RESET, TRAP

This interrupt management is based on:

–Bit 5 and bit 3 of the CPU CC register (I1:0),

–Interrupt software priority registers (ISPRx),

–Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 7). The processing flow is shown in Figure 14

When an interrupt request has to be serviced:

–Normal processing is suspended at the end of the current instruction execution.

–The PC, X, A and CC registers are saved onto the stack.

–I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector.

–The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.

Table 7. Interrupt Software Priority Levels

Interrupt software priority		Level		I1	I0
Level 0	(main)	Low		1	0
Level 1				0	1
Level 2		High		0	0
Level 3	(= interrupt disable)			1	1

Figure 14. Interrupt Processing Flowchart

RESET	PENDING	Y		TRAP	Y
	INTERRUPT
	N		Interrupt has the same or a	N
			lower software priority
			than current one	I1:0
	FETCH NEXT		THE INTERRUPT
	INSTRUCTION		STAYS PENDING
	Y		Interrupt hashighera	softwarepriority than currentone
	“IRET”
	N
RESTORE PC, X, A, CC	EXECUTE
FROM STACK	INSTRUCTION		STACK PC, X, A, CC
			LOAD I1:0 FROM INTERRUPT SW REG.
			LOAD PC FROM INTERRUPT VECTOR

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INTERRUPTS (Cont’d)

Servicing Pending Interrupts

As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process:

–the highest software priority interrupt is serviced,

–if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first.

Figure 15 describes this decision process.

Figure 15. Priority Decision Process

	PENDING
	INTERRUPTS
Same	SOFTWARE	Different
	PRIORITY
	HIGHEST SOFTWARE
	PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt.

Note 2: RESET and TRAP can be considered as having the highest software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 14). After stacking the PC, X, A and CC registers (except for RESET), the corresponding

vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 14.

■ RESET

The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority.

See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.

■ External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR).

External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.

If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register.

Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

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INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 15.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 16 and Figure 17 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 17. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

Figure 16. Concurrent Interrupt Management

IT2

IT1

IT4

IT3

TRAP

IT0

SOFTWARE

I1

I0

PRIORITY

LEVEL

PRIORITY			TRAP		3	1		1
			IT0		3	1		1
HARDWARE		IT1	IT1		3	1		1
		IT2			3	1		1
	RIM		IT3		3	1		1
					3	1		1
			IT4
	MAIN			MAIN	3/0
	11 / 10			10

USED STACK = 10 BYTES

Figure 17. Nested Interrupt Management

PRIORITY
HARDWARE	RIM
	MAIN
	11 / 10

IT2		IT1		IT4		IT3		TRAP		IT0		SOFTWARE		I1								I0
												PRIORITY
												LEVEL
										TRAP			3			1			1
												IT0	3			1			1
				IT1								IT1	2			0			0
		IT2										IT2	1			0			1
												IT3	3			1			1
						IT4						IT4	3			1			1
												MAIN	3/0
												10

USED STACK = 20 BYTES

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INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS

Read/Write

Reset Value: 111x 1010 (xAh)

7							0
1	1	I1	H	I0	N	Z	C

Bit 5, 3 = I1, I0 Software Interrupt Priority

These two bits indicate the current interrupt software priority.

Interrupt Software Priority		Level	I1	I0
Level 0	(main)	Low	1	0
Level 1			0	1
Level 2			0	0
Level 3	(= interrupt disable*)	High	1	1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx).

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction Set” table).

*Note: TRAP and RESET events can interrupt a level 3 program.

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)

	7							0
ISPR0	I1_3	I0_3	I1_2	I0_2	I1_1	I0_1	I1_0	I0_0
ISPR1	I1_7	I0_7	I1_6	I0_6	I1_5	I0_5	I1_4	I0_4
ISPR2	I1_11	I0_11	I1_10	I0_10	I1_9	I0_9	I1_8	I0_8
ISPR3	1	1	1	1	I1_13	I0_13	I1_12	I0_12

These four registers contain the interrupt software priority of each interrupt vector.

–Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.

Vector address	ISPRx bits
FFFBh-FFFAh	I1_0 and I0_0 bits*
FFF9h-FFF8h	I1_1 and I0_1 bits
...	...
FFE1h-FFE0h	I1_13 and I0_13 bits

–Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register.

–Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h)

The RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

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INTERRUPTS (Cont’d)

Table 8. Dedicated Interrupt Instruction Set

Instruction	New Description	Function/Example	I1	H	I0	N	Z	C
HALT	Entering Halt mode		1		0
IRET	Interrupt routine return	Pop CC, A, X, PC	I1	H	I0	N	Z	C
JRM	Jump if I1:0=11 (level 3)	I1:0=11 ?
JRNM	Jump if I1:0<>11	I1:0<>11 ?
POP CC	Pop CC from the Stack	Mem => CC	I1	H	I0	N	Z	C
RIM	Enable interrupt (level 0 set)	Load 10 in I1:0 of CC	1		0
SIM	Disable interrupt (level 3 set)	Load 11 in I1:0 of CC	1		1
TRAP	Software trap	Software NMI	1		1
WFI	Wait for interrupt		1		0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.

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