ST STM32F372C8, STM32F372R8, STM32F372V8, STM32F372CB, STM32F372RB User Manual

STM32F372xx STM32F373xx

ARM™-Cortex-M4 32b MCU+FPU,up to 256KB Flash+32KB SRAM 4 ADCs (12- & 16-bit), 3 DACs, 2 comp., timers, 2.0-3.6V operation

Features

■ARM 32-bit Cortex®-M4 CPU (72 MHz max), single-cycle multiplication and HW division, DSP instruction with FPU (floating-point unit) and MPU (memory protection unit)

■Memories

–64 to 256 Kbytes of Flash memory

–32 Kbytes of SRAM with HW parity check

■Clock management

–4 to 32 MHz crystal oscillator

–32 kHz oscillator for RTC with calibration

–Internal 8 MHz RC with x 16 PLL option

–Internal 40 kHz oscillator

■Calendar RTC

–Alarm, periodic wakeup from Stop/Standby

■Reset and supply management

–2.0 to 3.6 V

–POR, PDR and PVD

	Datasheet preliminary data
	FBGA
LQFP48 (7 × 7 mm)	UFBGA100 (7 x 7 mm)
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)

■Up to 2 fast rail-to-rail analog comparators

■Temperature sensor

■Up to 3 x 12-bit DAC channels

■Support for up to 24 capacitive sensing keys

■Up to 84 fast I/O ports, all mappable on ext. interrupt vectors, and several 5 V-tolerant

■17 timers

–2 x 32-bit timer and 3 x 16-bit timers with up to 4 IC/OC/PWM or pulse counter

–2 x 16-bit timers with up to 2 IC/OC/PWM or pulse counter

–4 x 16-bit timers with up to 1 IC/OC/PWM or pulse counter

–2 x watchdog timers (independent, window)

■Low power

–Sleep, Stop, and Standby modes

–VBAT supply for RTC and backup registers (1.65 V to 3.6 V)

■Debug mode: serial wire debug (SWD), JTAG interfaces, Cortex-M4 ETM

■DMA

–12-channel DMA controller

–Peripherals supported: timers, ADCs, SPIs, I2Cs, USARTs and DACs

■Up to 3 x 16-bit Sigma Delta ADC with separate analog supply from 2.2 V to 3.6 V, up to 21 single/ 11 diff channels, 7 programmable gains per channel

■1 x 12-bit, 1 µs ADC with separate analog supply from 2.4 V to 3.6 V

–SysTick timer: 24-bit downcounter

–3 x 16-bit basic timers to drive the DAC

■Communication interfaces

–CAN interface (2.0B Active)

–USB 2.0 full speed interface

–2 x I2C with 20 mA current sink to support Fast mode plus

–Up to 3 USARTs (ISO 7816 interface, LIN, IrDA, modem control, autobaudrate)

–Up to 3 SPIs, with muxed I2S

–CRC calculation unit, 96-bit unique ID

–HDMI-CEC bus interface

Table 1. Device summary

Reference

Part number

STM32F372C8, STM32F372R8, STM32F372V8, STM32F372xx STM32F372CB, STM32F372RB, STM32F372VB, STM32F372CC, STM32F372RC, STM32F372VC

STM32F373C8, STM32F373R8, STM32F373V8, STM32F373xx STM32F373CB, STM32F373RB, STM32F373VB, STM32F373CC, STM32F373RC, STM32F373VC

June 2012

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Details are subject to change without notice.

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Contents	STM32F37x

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 8
2	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	2.1 ARM® Cortex™-M4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11

2.1.1 ARM® Cortex™-M4 core with embedded Flash and SRAM . . . . . . . . . 11 2.1.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 12 2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.10 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.11 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 15 2.12 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.13 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.14 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.15 12-bit ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.16 16-bit sigma delta analog-to-digital converters (SDADC) . . . . . . . . . . . . . 18 2.17 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.18 Fast comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.19 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.19.1 General-purpose timers (TIM2 to TIM5, TIM12 to TIM17, TIM19) . . . . . 21 2.19.2 Basic timers (TIM6, TIM7, TIM18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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2.19.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.19.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.19.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.20 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
2.20.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22

2.20.2Universal synchronous/asynchronous receiver transmitter (USART) . . 22

2.20.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.20.4High-definition multimedia interface (HDMI) - consumer

electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.20.5 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.20.6 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.20.7 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

	2.21	Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
		2.21.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . .	24
		2.21.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
3	Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
4	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		44
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		48
	5.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		51
5.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		53
	5.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	5.3.2	Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . .	54
	5.3.3	Embedded reset and power control block characteristics . . . . . . . . . . .	54
	5.3.4	Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
	5.3.5	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
	5.3.6	External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	66

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5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.15 BOOT0 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.16 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.23 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.3.24 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.25 SDADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			110
	6.1	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		110
	6.2	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		115
		6.2.1	Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 115
		6.2.2	Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . .	. 116
7	Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			118
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			119

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STM32F37x	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Capacitive sensing GPIOs available on STM32F37x devices . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. No. of capacitive sensing channels available on STM32F37x devices. . . . . . . . . . . . . . . . 17 Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9. STM32F37x BGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 11. STM32F37x pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 12. Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 13. STM32F37x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 18. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 20. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 21. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 22. Typical and maximum current consumption from VDD supply at VDD = 3.6 V . . . . . . . . . . 57 Table 23. Typical and maximum current consumption from VDDA supply . . . . . . . . . . . . . . . . . . . . . 58 Table 24. Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 59 Table 25. Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 60

Table 26. Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 60 Table 27. Typical current consumption in Run mode, code with data processing running from Flash 62

Table 28. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 63 Table 29. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 30. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 31. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 34. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 35. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 36. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 37. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 38. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 39. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 40. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 41. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 42. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 43. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 44. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 45. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 46. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 47. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 48. BOOT0 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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List of tables	STM32F37x

Table 49. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 50. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 51. WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 52. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 53. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 54. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 55. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 56. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 57. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 58. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 59. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 60. Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 61. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 62. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 63. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 64. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 65. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 66. SDADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 67. SDVREF+ pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 68. UFBGA100 – ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 69. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 112 Table 70. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 113 Table 71. LQFP48 – 7 x 7 mm 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . 114 Table 72. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 73. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

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STM32F37x	List of figures

List of figures

Figure 1.	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 10
Figure 2.	STM32F37x LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 25
Figure 3.	STM32F37x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 26
Figure 4.	STM32F37x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 5.	STM32F37x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
Figure 6.	Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 7.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 8.	Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 9.	Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
Figure 10.	High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
Figure 11.	Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
Figure 12.	Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
Figure 13.	Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
Figure 14.	TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
Figure 15.	TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	80
Figure 16.	Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . .	81
Figure 17.	Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . .	81
Figure 18.	I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	85
Figure 19.	Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	86
Figure 20.	I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	89
Figure 21.	SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
Figure 22.	SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
Figure 23.	SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	92
Figure 24.	I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	94
Figure 25.	I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	94
Figure 26.	ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
Figure 27.	Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
Figure 28.	12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	99
Figure 29.	USB timings: definition of data signal rise and fall time (to be added) . . . . . . . . . . . . . . .	103
Figure 30.	UFBGA100 – ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch,
	package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	111
Figure 31.	LQFP100 –14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . .	112
Figure 32.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	112
Figure 33.	LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . .	113
Figure 34.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	113
Figure 35.	LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat
	package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	114
Figure 36.	Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	114
Figure 37.	LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	117

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Description	STM32F37x

1 Description

The STM32F37x family is based on the high-performance ARM® Cortex™-M4 32-bit RISC core operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM). The family incorporates high-speed embedded memories (up to 256 Kbyte of Flash memory, up to

32 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.

The STM32F37x devices offer one fast 12-bit ADC (1 Msps), up to three 16-bit Sigma delta ADCs, up to two Comparators, up to two DACs (DAC1 with 2 channels and DAC2 with 1 channel), a low-power RTC, 9 general-purpose 16-bit timers, two general-purpose 32-bit timers, three basic timers.

They also feature standard and advanced communication interfaces: up to two I2Cs, three SPIs, all with muxed I2Ss, three USARTs, CAN and USB.

The STM32F37x family operates in the -40 to +85 °C and -40 to +105 °C temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F37x family offers devices in five packages ranging from 48 pins to 100 pins. The set of included peripherals changes with the device chosen.

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STM32F37x	Device overview

2 Device overview

Table 2.	Device overview
Peripheral			STM32F					STM32F				STM32F					STM32F					STM32F				STM32F
				372Cx					372Rx				372Vx					373Cx					373Rx				373Vx
Flash (Kbytes)		64		128		256	64		128	256	64		128		256	64		128		256	64		128	256	64		128		256
SRAM (Kbytes)		16		24		32	16		24	32	16		24		32	16		24		32	16		24	32	16		24		32
	General						9 (16-bit)														9 (16-bit)
Timers	purpose							2 (32 bit)														2 (32 bit)
	Basic						3 (16-bit)														3 (16-bit)
	SPI/I2S							3														3
	I2C							2														2
Comm.
	USART							3														3
interfaces
	CAN							1														1
	USB							1														1
GPIOs			36					52				84					36					52				84
12-bit ADCs								1														1
16-bit ADCs								1														3
SigmaDelta
12-bit DACs								1														3
outputs
Analog comparator								1														2
CPU frequency								72 MHz														72 MHz
Main operating							2.0 to 3.6 V														2.0 to 3.6 V
voltage
16-bit SDADC							2.2 to 3.6 V														2.2 to 3.6 V
operating voltage
Operating				Ambient operating temperature:														Ambient operating temperature:
					40 to 85 °C / 40 to 105 °C														40 to 85 °C / 40 to 105 °C
temperature
				Junction temperature: 40 to 125 °C														Junction temperature: 40 to 125 °C
Packages			LQFP48				LQFP64,				LQFP100						LQFP48				LQFP64,				LQFP100
											UFBGA100(1)														UFBGA100(1)

1. UFBGA100 package available on 256-KB versions only.

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Device overview	STM32F37x

Figure 1.

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STM32F37x	Device overview

2.Example given for STM32F373xx device.

2.1ARM® Cortex™-M4 core

2.1.1ARM® Cortex™-M4 core with embedded Flash and SRAM

The ARM Cortex-M4 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The ARM Cortex-M4 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.

With its embedded ARM core, the STM32F37x family is compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the STM32F37x family.

2.1.2Memory protection unit

The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:

●Outstanding processing performance combined with fast interrupt handling

●Enhanced system debug with extensive breakpoint and trace capabilities

●Efficient processor core, system and memories

●Ultralow power consumption with integrated sleep modes

●Platform security robustness with optional integrated memory protection unit (MPU).

With its embedded ARM core, the STM32F37x devices are compatible with all ARM development tools and software.

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Device overview	STM32F37x

2.2Nested vectored interrupt controller (NVIC)

The STM32F37x devices embed a nested vectored interrupt controller (NVIC) able to handle up to 60 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

●Closely coupled NVIC gives low latency interrupt processing

●Interrupt entry vector table address passed directly to the core

●Closely coupled NVIC core interface

●Allows early processing of interrupts

●Processing of late arriving higher priority interrupts

●Support for tail chaining

●Processor state automatically saved

●Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

2.3Extended interrupt/event controller (EXTI)

The external interrupt/event controller consists of 29 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 84 GPIOs can be connected to the 16 external interrupt lines.

2.4Embedded Flash memory

All STM32F37x devices feature up to 256 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above).

2.5CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

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2.6Embedded SRAM

All STM32F37x devices feature up to 32 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states.

2.7Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed APB domain is 36 MHz.

2.8Boot modes

At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:

●Boot from user Flash

●Boot from system memory

●Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1, USART2 or USB.

2.9Power management

2.9.1Power supply schemes

●VDD: external power supply for I/Os and the internal regulator. It is provided externally through VDD pins, and can be 2.0 to 3.6 V.

●VDDA = 2.0 to 3.6 V:

–external analog power supplies for Reset blocks, RCs and PLL

–supply voltage for 12-bit ADC, DACs and comparators (minimum voltage to be applied to VDDA is 2.4 V when the 12-bit ADC and DAC are used).

●SDADC1_VDD/SDADC2_VDD and SDADC3_VDD = 2.2 V to 3.6: supply voltages for SDADC1/2 and SDADCD3 sigma delta ADCs. Independent from VDD/VDDA.

●VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

2.9.2Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains

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Device overview	STM32F37x

in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.

●The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD.

●The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce

the power consumption if the application design ensures that VDDA is higher than or equal to VDD.

The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

2.9.3Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR), and power-down.

●The MR mode is used in the nominal regulation mode (Run)

●The LPR mode is used in Stop mode.

●The power-down mode is used in Standby mode: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The voltage regulator is always enabled after reset. It is disabled in Standby mode.

2.10Low-power modes

The STM32F37x supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

●Stop mode

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the USARTs, the I2Cs, the CEC, the USB wakeup, and the RTC alarm.

●Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

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STM32F37x	Device overview
Note:	The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
	or Standby mode.

2.11 Real-time clock (RTC) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin.The backup registers are thirty two 32-bit registers used to store 128 bytes of user application data when VDD power is not present.

They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode.

The RTC is an independent BCD timer/counter. Its main features are the following:

●Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

●Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.

●2 programmable alarms with wake up from Stop and Standby mode capability.

●Periodic wakeup unit with programmable resolution and period.

●On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

●Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy.

●3 anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection.

●Timestamp feature which can be used to save the calendar content. This function can triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.

The RTC clock sources can be:

●A 32.768 kHz external crystal

●A resonator or oscillator

●The internal low-power RC oscillator (typical frequency of 40 kHz)

●The high-speed external clock divided by 32

2.12DMA (direct memory access)

The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

The two DMAs can be used with the main peripherals: SPIs, I2Cs, USARTs, DACs, ADC, SDADCs, general-purpose timers.

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Device overview	STM32F37x

2.13GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

2.14Touch sensing controller (TSC)

The device has an embedded independent hardware controller (TSC) for controlling touch sensing acquisitions on the I/Os.

Up to 24 touch sensing electrodes can be controlled by the TSC. The touch sensing I/Os are organized in 8 acquisition groups, with up to 4 I/Os in each group.

	Table 3.	Capacitive sensing GPIOs available on STM32F37x devices
	Pin name		Capacitive sensing	Pin name	Capacitive sensing
			group name		group name
		PA0	G1_IO1	PA9	G4_IO1
		PA1	G1_IO2	PA10	G4_IO2
		PA2	G1_IO3	PA13	G4_IO3
		PA3	G1_IO4	PA14	G4_IO4
		PA4	G2_IO1	PB3	G5_IO1
		PA5	G2_IO2	PB4	G5_IO2
		PA6	G2_IO3	PB6	G5_IO3
		PA7	G2_IO4	PB7	G5_IO4
		PC4	G3_IO1	PB14	G6_IO1
		PC5	G3_IO2	PB15	G6_IO2
		PB0	G3_IO3	PD8	G6_IO3
		PB1	G3_IO4	PD9	G6_IO4
		PE2	G7_IO1	PD12	G8_IO1
		PE3	G7_IO2	PD13	G8_IO2
		PE4	G7_IO3	PD14	G8_IO3
		PE5	G7_IO4	PD15	G8_IO4

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STM32F37x					Device overview
	Table 4.	No. of capacitive sensing channels available on STM32F37x devices
	Analog I/O group		Number of capacitive sensing channels
			STM32F37xCx	STM32F37xRx	STM32F37xVx
	G1		3	3	3
	G2		2	3	3
	G3		1	3	3
	G4		3	3	3
	G5		3	3	3
	G6		2	2	3
	G7		0	0	3
	G8		0	0	3
	Number of capacitive		14	17	24
	sensing channels

2.1512-bit ADC (analog-to-digital converter)

The 12-bit analog-to-digital converter is based on a successive approximation register (SAR) architecture. It has up to 16 external channels (AIN15:0) and 3 internal channels (temperature sensor, voltage reference, VBAT voltage measurement) performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the timers (TIMx) can be internally connected to the ADC start and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

2.15.1Temperature sensor

The temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature.

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

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Device overview				STM32F37x
	Table 5.	Temperature sensor calibration values
	Calibration value name		Description	Memory address
			TS ADC raw data acquired at
	TS_CAL1		temperature of 30 °C,	0x1FFF F7B8 - 0x1FFF F7B9
			VDDA= 3.3 V
			TS ADC raw data acquired at
	TS_CAL2		temperature of 110 °C	0x1FFF F7C2 - 0x1FFF F7C3
			VDDA= 3.3 V

2.15.2Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 6.	Temperature sensor calibration values
Calibration value name		Description	Memory address
		Raw data acquired at
VREFINT_CAL		temperature of 30 °C	0x1FFF F7BA - 0x1FFF F7BB
		VDDA= 3.3 V

2.15.3VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage

using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a divider by 2.

As a consequence, the converted digital value is half the VBAT voltage.

2.1616-bit sigma delta analog-to-digital converters (SDADC)

Up to three 16-bit sigma-delta analog-to-digital converters are embedded in the STM32F37x. They have up to two separate supply voltages allowing the analog function voltage range to be independent from the STM32F37x power supply. They share up to 21 input pins which may be configured in any combination of single-ended (up to 21) or differential inputs (up to 11).

The conversion speed is up to 16.6 ksps for each SDADC when converting multiple channels and up to 50 ksps per SDADC if single channel conversion is used. There are two conversion modes: single conversion mode or continuous mode, capable of automatically scanning any number of channels. The data can be automatically stored in a system RAM buffer, reducing the software overhead.

A timer triggering system can be used in order to control the start of conversion of the three SDADCs and/or the 12-bit fast ADC. This timing control is very flexible, capable of triggering simultaneous conversions or inserting a programmable delay between the ADCs.

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Up to two external reference pins (SD_VREF+, SD_VREF-) and an internal 1.2/1.8V reference can be used in conjunction with a programmable gain (x0.5 to x32) in order to fine-tune the

input voltage range of the SDADC.

2.17DAC (digital-to-analog converter)

The devices feature up to two 12-bit buffered DACs with three output channels that can be used to convert three digital signals into three analog voltage signal outputs. The internal structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This digital Interface supports the following features:

●Up to two DAC converters with three output channels:

–DAC1 with two output channels

–DAC2 with one output channel.

●8-bit or 12-bit monotonic output

●Left or right data alignment in 12-bit mode

●Synchronized update capability

●Noise-wave generation

●triangular-wave generation

●Dual DAC channel independent or simultaneous conversions (DAC1 only)

●DMA capability for each channel

●External triggers for conversion

2.18Fast comparators

The STM32F37x embeds up to 2 comparators with rail-to-rail inputs and high-speed output. The reference voltage can be internal or external (delivered by an I/O).

The threshold can be one of the following:

●DACs channel outputs

●External I/O

●Internal reference voltage (VREFINT) or submultiple (1/4 VREFINT, 1/2 VREFINT and 3/4 VREFINT)

The comparators can be combined into a window comparator.

Both comparators can wake up the device from Stop mode and generate interrupts and breaks for the timers.

2.19Timers and watchdogs

The STM32F37x includes two 32-bit and nine 16-bit general-purpose timers, three basic timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers.

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	Device overview							STM32F37x
	Table 7.	Timer feature comparison
			Counter	Counter	Prescaler	DMA	Capture/	Complementary
	Timer type	Timer				request	compare
			resolution	type	factor			outputs
						generation	Channels
	General-	TIM2		Up, Down,	Any integer
			32-bit		between 1	Yes	4	0
	purpose	TIM5		Up/Down
					and 65536
	General-	TIM3,		Up, Down,	Any integer
		TIM4,	16-bit		between 1	Yes	4	0
	purpose			Up/Down
		TIM19			and 65536
	General-				Any integer
		TIM12	16-bit	Up	between 1	No	2	0
	purpose
					and 65536
	General-				Any integer
		TIM15	16-bit	Up	between 1	Yes	2	1
	purpose
					and 65536
	General-	TIM13,			Any integer
			16-bit	Up	between 1	No	1	0
	purpose	TIM14
					and 65536
	General-	TIM16,			Any integer
			16-bit	Up	between 1	Yes	1	1
	purpose	TIM17
					and 65536
		TIM6,			Any integer
	Basic	TIM7,	16-bit	Up	between 1	Yes	0	0
		TIM18			and 65536

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2.19.1General-purpose timers (TIM2 to TIM5, TIM12 to TIM17, TIM19)

There are eleven synchronizable general-purpose timers embedded in the STM32F37x (see Table 7 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

●TIM2, 3, 4, 5 and 19

These five timers are full-featured general-purpose timers:

–TIM2 and TIM5 have 32-bit auto-reload up/downcounters and 32-bit prescalers

–TIM3, 4, and 19 have 16-bit auto-reload up/downcounters and 16-bit prescalers.

These timers all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

●TIM12, 13, 14, 15, 16, 17

These six timers general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers.

–TIM12 has 2 channels

–TIM13 and TIM14 have 1 channel

–TIM15 has 2 channels and 1 complementary channel

–TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

2.19.2Basic timers (TIM6, TIM7, TIM18)

These timers are mainly used for DAC trigger generation. They can also be used as a

generic 16-bit time base.

2.19.3Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

2.19.4System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB1 clock (PCLK1) derived from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

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Device overview	STM32F37x

2.19.5SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

●A 24-bit down counter

●Autoreload capability

●Maskable system interrupt generation when the counter reaches 0.

●Programmable clock source

2.20Communication interfaces

2.20.1I2C bus

Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz) modes with 20 mA output drive. They support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters.

	Table 8.	Comparison of I2C analog and digital filters
			Analog filter	Digital filter
	Pulse width of		50 ns	Programmable length from 1 to 15
	suppressed spikes			I2C peripheral clocks
				1. Extra filtering capability vs.
	Benefits		Available in Stop mode	standard requirements.
				2. Stable length
	Drawbacks		Variations depending on	Disabled when Wakeup from Stop
			temperature, voltage, process	mode is enabled

In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeout verifications and ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the application to wake up the MCU from Stop mode on address match.

The I2C interfaces can be served by the DMA controller

2.20.2Universal synchronous/asynchronous receiver transmitter (USART)

The STM32F37x embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3).

All USARTs interfaces are able to communicate at speeds of up to 9 Mbit/s.

They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode, Smart Card mode (ISO 7816 compliant), autobaudrate feature and have LIN Master/Slave capability.The USART interfaces can be served by the DMA controller.

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2.20.3Serial peripheral interface (SPI)

Up to three SPIs are able to communicate at up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

The SPIs can be served by the DMA controller.

2.20.4High-definition multimedia interface (HDMI) - consumer electronics control (CEC)

The device embeds a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception.

2.20.5Inter-integrated sound (I2S)

Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

2.20.6Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.

2.20.7Universal serial bus (USB)

The STM32F37x embeds an USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

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Device overview	STM32F37x

2.21Development support

2.21.1Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

2.21.2Embedded trace macrocell™

The ARM embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F37x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

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STM32F37x	Pinouts and pin description

3 Pinouts and pin description

Figure 2. STM32F37x LQFP48 pinout

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Figure 3. STM32F37x LQFP64 pinout

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Pinouts and pin description

Figure 4.

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Pinouts and pin description

STM32F37x

Table 9.

STM32F37x BGA100 pinout

1

2

3

4

5

6

7

8

9

10

11

12

A

PE3

PE1

PB8

BOOT0

PD7

PD5

PB4

PB3

PA15

PA14

PA13

PA12

B

PE4

PE2

PB9

PB7

PB6

PD6

PD4

PD3

PD1

PC12

PC10

PA11

PC13_

C

TAMPE

PE5

PE0

VDD_1

PB5

PD2

PD0

PC11

PF6

PA10

R1-

WKUP2

PC14-

PE6-

TAMPE

D

OSC32

VSS_1

PA9

PA8

PC9

R3-

_ IN

WKUP3

PC15-

E

OSC32

VBAT

PF4

PC8

PC7

PC6

_ OUT

SDAD

PF0-

C1_SD

ADC2_

F

OSC_

PF9

VSS_3

IN

SDAD

C3_VS

S

PF1-

SDAD

C1_SD

G

OSC_

PF10

VDD_3

OUT

ADC2_

VDD

H

PC0-

NRST

VDD_2

PD15

PD14

PD13

ADC10

J

PF2

PC1

PC2

PD12

PD11

PD10

VSSA-

ADC_V

SD_

K

SS-

PC3

PA2

PA5

PC4

PD9

PD8

PB15

PB14

VREF+

ADC_

VREF-

PA0-

SDAD

ADC_

TAMPE

PB2

SD_

L

PA3

PA6

PC5

PE8

PE10

PE12

PB10

C3_

VREF+

R2-

VREF-

VDD

WKUP1

VDDA-

M

ADC_V

PA1

PA4

PA7

PB0

PB1

PE7

PE9

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PE13

PE14

PE15

DD

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STM32F37x				Pinouts and pin description
	Table 10. Legend/abbreviations used in the pinout table
	Name		Abbreviation	Definition
	Pin name		Unless otherwise specified in brackets below the pin name, the pin function
			during and after reset is the same as the actual pin name
			S	Supply pin
	Pin type		I	Input only pin
			I/O	Input / output pin
			FT	5 V tolerant I/O
			FTf	5 V tolerant I/O, FM+ capable
	I/O structure		TTa	3.3 V tolerant I/O directly connected to ADC
			TC	Standard 3.3V I/O
			B	Dedicated BOOT0 pin
			RST	Bidirectional reset pin with embedded weak pull-up resistor
	Notes		Unless otherwise specified by a note, all I/Os are set as floating inputs during
			and after reset
		Alternate	Functions selected through GPIOx_AFR registers
		functions
	Pin
	functions	Additional	Functions directly selected/enabled through peripheral registers
		functions

Table 11.			STM32F37x pin definitions
LQFP100		BGA100	LQFP64		LQFP48			structureI/O	Pin functions
	Pin numbers					Pin name
						(function	Pin
							type		Alternate function	Additional functions
						after reset)
1		B2				PE2	I/O	FT	G7_IO1, TRACECLK
2		A1				PE3	I/O	FT	G7_IO2, TRACED0
3		B1				PE4	I/O	FT	G7_IO3, TRACED1
4		C2				PE5	I/O	FT	G7_IO4, TRACED2
						PE6 -
5		D2				TAMPER3 -	I/O	TTa	TRACED3, RTC_TAMPER3	WKUP3
						WKUP3
6		E2	1		1	VBAT	S
						PC13 -				WKUP2_ALARM_OUT_
7		C1	2		2	TAMPER1 -	I/O	TTa	RTC_TAMPER1
										CALIB_OUT_TIMESTAMP
						WKUP2
8		D1	3		3	PC14 -	I/O	TC		OSC32_IN
						OSC32_IN

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	Pinouts and pin description								STM32F37x
	Table 11.		STM32F37x pin definitions (continued)
	LQFP100	BGA100	LQFP64	LQFP48			structureI/O	Pin functions
	Pin numbers				Pin name
					(function	Pin
						type		Alternate function	Additional functions
					after reset)
	9	E1	4	4	PC15 -	I/O	TC		OSC32_OUT
					OSC32_OUT
	10	F2			PF9	I/O	FT	TIM14_CH1
	11	G2			PF10	I/O	FT
	12	F1	5	5	PF0 -	I/O	FT	I2C2_SDA	OSC_IN
					OSC_IN
	13	G1	6	6	PF1 -	I/O	FT	I2C2_SCL	OSC_OUT
					OSC_OUT
	14	H2	7	7	NRST	I/O	RST
	15	H1	8		PC0	I/O	TTa	TIM5_CH1_ETR	ADC_IN10
	16	J2	9		PC1	I/O	TTa	TIM5_CH2	ADCIN11
	17	J3	10		PC2	I/O	TTa	SPI2_MISO, I2S2_MCK,	ADC_IN12
								TIM5_CH3
	18	K2	11		PC3	I/O	TTa	SPI2_MOSI, I2S2_SD,	ADC_IN13
								TIM5_CH4
	19	J1			PF2	I/O	FT	I2C2_SMBAI
					VSSA /
	20	K1	12	8	ADC_VSS /	S
					ADC_
					VREF-
					VDDA ,
				9	ADC_VDD ,	S
					ADC_
					VREF+
	21	M1	13		VDDA ,	S
					ADC_VDD
	22	L1	17		ADC_	S
					VREF+
					PA0 -			USART2_CTS,TIM2_CH1_ET,	RTC_ TAMPER2, WKUP1,
	23	L2	14	10	TAMPER2 -	I/O	TTa	TIM5_CH1_ETR,TIM19_CH1,
									ADC_IN0,COMP1_INn
					WKUP1			G1_IO1,COMP1_OUT
								SPI3_SCK_I2S3_CK,
								USART2_RTS,TIM2_CH2,
	24	M2	15	11	PA1	I/O	TTa	TIM15_CH1N,TIM5_CH2,	ADC_IN1,COMP1_INp
								TIM19_CH2,G1_IO2,
								RTC_REF_CLK_IN

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Doc ID 022691 Rev 1