ST STM32L151QD, STM32L151RD, STM32L151VD, STM32L151ZD, STM32L152QD User Manual

STM32L151xD, STM32L152xD

Ultralow power ARM-based 32-bit MCU with 384 KB Flash, RTC, LCD, USB, analog functions, 10 serial ports, memory I/F

Features

■Operating conditions

–Operating power supply range: 1.65 V to

3.6V (without BOR) or 1.8 V to 3.6 V

■Low power features

–7 modes: Sleep, Low-power run (11 µA at 32 kHz) , Low-power sleep (4.4 µA), Stop with RTC, Stop (650 nA), Standby with RTC, Standby (300 nA)

–Dynamic core voltage scaling down to 233 µA/MHz

–Ultralow leakage per I/O: 50 nA max

–Fast wakeup time from Stop: 8 µs

–Three wakeup pins

■Core: ARM 32-bit Cortex™-M3 CPU

–32 MHz maximum frequency,

33.3DMIPS peak (Dhrystone 2.1)

–Memory protection unit

■Reset and supply management

–Low power, ultrasafe BOR (brownout reset)

–Ultralow power POR/PDR

–Programmable voltage detector (PVD)

■Clock management

–1 to 24 MHz crystal oscillator

–32 kHz oscillator for RTC with calibration

–Internal 16 MHz factory-trimmed RC

–Internal 37 kHz low consumption RC

–Internal multispeed low power RC, 65 kHz to 4.2 MHz

–PLL for CPU clock and USB (48 MHz)

■Memories

–384 Kbytes of Flash memory with ECC, split into two banks allowing Read While Write

Datasheet − production data

LQFP144 (20 × 20 mm)
	UFBGA132					WLCSP64
LQFP100 (14 × 14 mm)	(7 × 7 mm)					(0.400 mm pitch)
LQFP64 (10 × 10 mm)

■Low power calendar RTC

–Alarm, periodic wakeup from Stop/Standby

■Up to 116 fast I/Os (102 of which are 5 V- tolerant)

■DMA: 12-channel DMA controller

■LCD 8 × 40 or 4 × 44 with step-up converter

■3 operational amplifiers

■12-bit ADC up to 1 Msps and 40 channels

–Operational amplifier output, temperature sensor and internal voltage reference

–Operates down to 1.8 V

■Two 12-bit DACs with output buffers

■Two ultralow power comparators

–Window mode and wakeup capability

■11 timers: one 32-bit and six 16-bit generalpurpose timers, two 16-bit basic timers, two watchdog timers (independent and window)

■Up to 12 communication interfaces

–Up to two I2C interfaces (SMBus/PMBus)

–Up to five USARTs

–Up to three SPIs (16 Mbit/s), two with I2S

–USB 2.0 full-speed interface

–SDIO interface

■Up to 34 capacitive sensing channels supporting touchkey, proximity, linear and rotary sensors

■32-bit CRC calculation unit, 96-bit unique ID

–12 Kbytes of data EEPROM with ECC

–NVM in 2 banks enabling Read While Write

–48 Kbytes of RAM

–Flexible static memory controller that supports SRAM, PSRAM and NOR Flash

Table 1. Device summary

Reference

Part number

STM32L151xx

STM32L151QD STM32L151RD

STM32L151VD STM32L151ZD

STM32L152xx

STM32L152QD STM32L152RD

STM32L152VD STM32L152ZD

June 2012

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This is information on a product in full production.

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Contents	STM32L151xD STM32L152xD

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 9
	2.1	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.2	Ultralow power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11

2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3	Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			12
	3.1	Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	3.2	ARM® Cortex™-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	3.3	Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
		3.3.1	Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
		3.3.2	Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
		3.3.3	Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
		3.3.4	Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	3.4	Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	3.5	Low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . .		19
	3.6	GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . .		19
	3.7	Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
	3.8	FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . .		20
	3.9	DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
	3.10	LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	3.11	ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
		3.11.1	Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
		3.11.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
	3.12	DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
	3.13	Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	3.14	Ultralow power comparators and reference voltage . . . . . . . . . . . . . . . . .		23
	3.15	System configuration controller and routing interface . . . . . . . . . . . . . . .		23

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3.16 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.17.1General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and

TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.18 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
3.18.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25

3.18.2Universal synchronous/asynchronous receiver transmitter (USART) . . 26

3.18.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18.5 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18.6 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

	3.19	CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . .	26
	3.20	Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
4	Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
5	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		47
6	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		48
	6.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		50
6.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		51
	6.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
	6.3.2	Embedded reset and power control block characteristics . . . . . . . . . . .	52
	6.3.3	Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . .	54
	6.3.4	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55

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6.3.5 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.6 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.7 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.8 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.9 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 89 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.19 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.21 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.22 LCD controller (STM32L152xD only) . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			115
	7.1	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		115
	7.2	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		122
		7.2.1	Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 122
8	Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			123
9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			124

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Ultralow power STM32L15xxD device features and peripheral counts . . . . . . . . . . . . . . . 10 Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 4. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6. STM32L15xQD BGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 7. STM32L15xRD WLCSP64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. STM32L15xxD pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 9. Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 10. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 11. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 12. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 13. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 14. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 52 Table 15. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 16. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 17. Current consumption in Run mode, code with data processing running from Flash. . . . . . 55 Table 18. Current consumption in Run mode, code with data processing running from RAM . . . . . . 56 Table 19. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 20. Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 21. Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 22. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 23. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 61 Table 24. Typical and maximum timings in Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 25. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 26. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 27. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 28. HSE 1-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 32. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 33. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 34. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 35. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 36. Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 76 Table 37. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 78 Table 38. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 79 Table 39. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 40. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 41. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 42. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 43. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 44. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 45. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 46. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 47. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 48. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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Table 49. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 50. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 51. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 52. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 53. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 54. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 55. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 56. SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 57. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 58. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 59. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 60. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 61. ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 62. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 63. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 64. RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 65. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 66. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 67. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 68. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 69. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 70. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 71. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 116 Table 72. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 117 Table 73. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 118 Table 74. UFBGA132 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 75. WLCSP64, 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . . 121 Table 76. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 77. STM32L15xxD ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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STM32L151xD STM32L152xD	List of figures

List of figures

Figure 1.	Ultralow power STM32L15xxD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 12
Figure 2.	Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 18
Figure 3.	STM32L15xZDLQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 29
Figure 4.	STM32L15xVD LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 30
Figure 5.	STM32L15xRD LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 30
Figure 6.	Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 47
Figure 7.	Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 8.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 9.	Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 10.	Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 11.	Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
Figure 12.	High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
Figure 13.	HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
Figure 14.	Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
Figure 15.	Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . .	77
Figure 16.	Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . .	78
Figure 17.	Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . .	79
Figure 18.	Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . .	80
Figure 19.	Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82
Figure 20.	Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	84
Figure 21.	Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . .	86
Figure 22.	Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	87
Figure 23.	I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	94
Figure 24.	Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	95
Figure 25.	I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
Figure 26.	SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	99
Figure 27.	SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	99
Figure 28.	SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	100
Figure 29.	USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . .	101
Figure 30.	ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	105
Figure 31.	Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	105
Figure 32.	Maximum dynamic current consumption on VREF+ supply pin during ADC
	conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	106
Figure 33.	Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . .	107
Figure 34.	Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . .	107
Figure 35.	12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	110
Figure 36.	LQFP144, 20 x 20 mm, 144-pin low-profile quad
	flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	116
Figure 37.	Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	116
Figure 38.	LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . .	117
Figure 39.	Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	117
Figure 40.	LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . .	118
Figure 41.	Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	118
Figure 42.	UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package outline . . . .	119
Figure 43.	WLCSP64, 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . .	120

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Introduction	STM32L151xD STM32L152xD

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32L151xD and STM32L152xD ultralow power ARM Cortex™-based microcontrollers product line.

The ultralow power STM32L15xxD family includes devices in 4 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

These features make the ultralow power STM32L15xxD microcontroller family suitable for a wide range of applications:

●Medical and handheld equipment

●Application control and user interface

●PC peripherals, gaming, GPS and sport equipment

●Alarm systems, wired and wireless sensors, Video intercom

●Utility metering

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337g.

Figure 1 shows the general block diagram of the device family.

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2 Description

The ultralow power STM32L15xxD incorporates the connectivity power of the universal serial bus (USB) with the high-performance ARM Cortex™-M3 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (Flash memory up to 384 Kbytes and RAM up to 48 Kbytes), a flexible static memory controller (FSMC) interface (for devices with packages of 100 pins and more) and an extensive range of enhanced I/Os and peripherals connected to two APB buses.

The STM32L15xxD devices offer three operational amplifiers, one 12-bit ADC, two DACs, two ultralow power comparators, one general-purpose 32-bit timer,six general-purpose 16bit timers and two basic timers, which can be used as time bases.

Moreover, the STM32L15xxD devices contain standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2S, one SDIO, three USARTs, two UARTs and a USB. Up to 34 channels are available for capacitive sensing directly driven through GPIOs and general purpose timers.

They also include a real-time clock and a set of backup registers that remain powered in Standby mode.

Finally, the integrated LCD controller has a built-in LCD voltage generator that allows you to drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.

The ultralow power STM32L15xxD operates from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. It is available in the -40 to +85 °C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications.

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Description	STM32L151xD STM32L152xD

2.1Device overview

Table 2.	Ultralow power STM32L15xxD device features and peripheral counts
Peripheral			STM32L15xRx	STM32L15xVx		STM32L15xQx		STM32L15xZx
Flash - Kbytes			384	384		384		384
Data EEPROM			12	12		12		12
RAM - Kbytes			48	48		48		48
FSMC			No	multiplexed		Yes		Yes
				only
		32 bit	1	1		1		1
Timers		General-purpose	6	6		6		6
		Basic	2	2		2		2
		SPI/(I2S)	3/(2)	3/(2)		3/(2)		3/(2)
		I2C	2	2		2		2
Communicatio
		USART	5	5		5		5
n interfaces
		USB	1	1		1		1
		SDIO	1	1		1		1
GPIOs			51	83		109		115
Operation amplifiers			3	3		3		3
12-bit synchronized ADC			1	1		1		1
Number of channels			21	25		40		40
12-bit DAC			2	2		2		2
Number of channels			2	2		2		2
LCD (1)			1	1		1		1
COM x SEG			4x32 or 8x28	4x44 or 8x40		4x44 or 8x40		4x44 or 8x40
Comparators			2	2		2		2
Capacitive sensing
No. of channels/No. of groups			23/10	23/10		33/11		34/11
CPU frequency				32 MHz
			1.8 V to 3.6 V (down to 1.65 V at power-down) with
Operating voltage				BOR option
			1.65 V to 3.6 V without BOR option
Operating temperatures			Ambient temperature: –40 to +85 °C
			Junction temperature: –40 to +105 °C
Packages			LQFP64,	LQFP100		BGA132		LQFP144
			WLCSP64
1. STM32L152xx devices only.

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STM32L151xD STM32L152xD	Description

2.2Ultralow power device continuum

	The ultralow power STM32L158V, STM32L15xxD, STM32L162xD, STM32L15xxC, and
	STM32L162xC are fully pin-to-pin, software and feature compatible. Besides the full
	compatibility within the family, the devices are part of STMicroelectronics microcontrollers
	ultralow power strategy which also includes STM8L101xx and STM8L15xx devices. The
	STM8L and STM32L families allow a continuum of performance, peripherals, system
	architecture and features.
	They are all based on STMicroelectronics 0.13 µm ultralow leakage process.
Note:	The ultralow power STM32L and general-purpose STM32Fxxxx families are pin-to-pin
	compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx
	devices. Please refer to the STM32F and STM8L documentation for more information on
	these devices.

2.2.1	Performance
	All families incorporate highly energy-efficient cores with both Harvard architecture and
	pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
	for STM32L family. In addition specific care for the design architecture has been taken to
	optimize the mA/DMIPS and mA/MHz ratios.
	This allows the ultralow power performance to range from 5 up to 33.3 DMIPs.

2.2.2 Shared peripherals

STM8L15xxx and STM32L15xxx share identical peripherals which ensure a very easy migration from one family to another:

●Analog peripherals: ADC, DAC and comparators

●Digital peripherals: RTC and some communication interfaces

2.2.3Common system strategy

To offer flexibility and optimize performance, the STM8L15xxx and STM32L15xxx families use a common architecture:

●Same power supply range from 1.65 V to 3.6 V

●Architecture optimized to reach ultralow consumption both in low power modes and Run mode

●Fast startup strategy from low power modes

●Flexible system clock

●Ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector

2.2.4Features

ST ultralow power continuum also lies in feature compatibility:

●More than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm

●Memory density ranging from 4 to 384 Kbytes

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Functional overview	STM32L151xD STM32L152xD

3 Functional overview

Figure 1. Ultralow power STM32L15xxD block diagram

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STM32L151xD STM32L152xD	Functional overview

1.Legend:

AF: alternate function

ADC: analog-to-digital converter BOR: brown out reset

DMA: direct memory access DAC: digital-to-analog converter

I²C: inter-integrated circuit multimaster interface

3.1Low power modes

The ultralow power STM32L15xxD supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply.

There are three power consumption ranges:

●Range 1 (VDD range limited to 2.0-3.6 V), with the CPU running at up to 32 MHz

●Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz

●Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated only with the multispeed internal RC oscillator clock source)

Seven low power modes are provided to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at 16 MHz is about 1 mA with all peripherals off.

●Low power run mode

This mode is achieved with the multispeed internal (MSI) RC oscillator set to the minimum clock (131 kHz), execution from SRAM or Flash memory, and internal regulator in low power mode to minimize the regulator's operating current. In Low power run mode, the clock frequency and the number of enabled peripherals are both limited.

●Low power sleep mode

This mode is achieved by entering Sleep mode with the internal voltage regulator in Low power mode to minimize the regulator’s operating current. In Low power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz.

When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on.

●Stop mode with RTC

Stop mode achieves the lowest power consumption while retaining the RAM and

register contents and real time clock. All clocks in the VCORE domain are stopped, the PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low power mode.

The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on), It can be, the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event, the RTC wakeup.

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Functional overview		STM32L151xD STM32L152xD
	● Stop mode without RTC
	Stop mode achieves the lowest power consumption while retaining the RAM and
	register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
	HSE crystal oscillators are disabled. The voltage regulator is in the low power mode.
	The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
	line source can be one of the 16 external lines. It can be the PVD output, the
	Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
	also be wakened by the USB wakeup.
	● Standby mode with RTC
	Standby mode is used to achieve the lowest power consumption and real time clock.
	The internal voltage regulator is switched off so that the entire VCORE domain is
	powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
	off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
	contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
	RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
	The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
	reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
	RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
	● Standby mode without RTC
	Standby mode is used to achieve the lowest power consumption. The internal voltage
	regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI
	RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
	entering Standby mode, the RAM and register contents are lost except for registers in
	the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
	RCC_CSR).
	The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
	edge on one of the three WKUP pin occurs.
Note:	The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
	entering Stop or Standby mode.

3.2 ARM® Cortex™-M3 core with MPU

The ARM Cortex™-M3 processor is the industry leading processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region.

Owing to its embedded ARM core, the STM32L15xxD is compatible with all ARM tools and software.

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Nested vectored interrupt controller (NVIC)

The ultralow power STM32L15xxD embeds a nested vectored interrupt controller able to handle up to 56 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

Closely coupled NVIC gives low-latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving, higher-priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

3.3Reset and supply management

3.3.1Power supply schemes

VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins.

VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs

and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively.

3.3.2Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR) that can be coupled with a brownout reset (BOR) circuitry.

The device exists in two versions:

The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

The other version without BOR at power up operates between 1.65 V and 3.6 V.

As the BOR can be activated and deactivated at run time, this distinction is important only for power-up phase.

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits the POR area.

After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently: in this case, the VDD min value at power down is 1.65 V.

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	Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
	reduce the power consumption in Stop mode, it is possible to automatically switch off the
	internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
	VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
	reset circuit.
Note:	The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
	up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
	at power-up.
	The device features an embedded programmable voltage detector (PVD) that monitors the
	VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
	levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
	interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
	VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
	a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3	Voltage regulator
	The regulator has three operation modes: main (MR), low power (LPR) and power down.
	MR is used in Run mode (nominal regulation)
	LPR is used in the Low power run, Low power sleep and Stop modes
	Power down is used in Standby mode. The regulator output is high impedance, the
	kernel circuitry is powered down, inducing zero consumption but the contents of the
	registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
	LSI, LSE crystal 32K osc, RCC_CSR).
3.3.4	Boot modes
	At startup, boot pins are used to select one of three boot options:
	Boot from Flash memory
	Boot from System memory
	Boot from embedded RAM

The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot mechanism is available through user option byte, to allow booting from bank 2 when bank 2 contains valid code. This dual boot capability can be used to easily implement a secure field software update mechanism.

The boot loader is located in System memory. It is used to reprogram the Flash memory by using USART1, USART2 or USB.

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3.4Clock management

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. It features:

Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.

Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

System clock source: three different clock sources can be used to drive the master clock SYSCLK:

–1-24 MHz high-speed external crystal (HSE), that can supply a PLL

–16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL

–Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a ±0.5% accuracy.

Auxiliary clock source: two ultralow power clock sources that can be used to drive the LCD controller and the real-time clock:

–32.768 kHz low-speed external crystal (LSE)

–37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision.

RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock.

USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface.

Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled.

Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See Figure 2 for details on the clock tree.

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Figure 2.	Clock tree
3TANDBY SUPPLIED VOLTAGE DOMAIN
			ENABLE		7ATCHDOG
		7ATCHDOG
	,3) 2#	,3) TEMPO			,3
					24##ENABLE
	,3% /3#	,3% TEMPO				24#
		,3	,3	,3	,3
	6$$#/2%									#+?,#$
		-(Z						,#$$ENABLE
	6									#+?!$#
								!$# ENABLE
	-3) 2#				CK?LSI
LEVELLSHIFTERS					CK?LSE
								-#/
	6$$#/2%
								NOTTDEEPSLEEP
										#+?072
	6
								NOT DEEPSLEEP
	(3)32#									#+?,+
								NOTT SLEEPEOR
	LEVELLSHIFTERS
								DEEPSLEEP
	6$$#/2%									#+?#05
							3YSTEM	NOTT SLEEP OR
	6
					CK?MSI		CLOCK	DEEPSLEEP
	(3%									#+?4)-393
	/3#				CK?HSI
							!("
	LEVELLSHIFTERS				CK?HSE
							PRESCALER
	6$$#/2%				6	CK?PLL
					0,,			!0"	!0"
	,3				CK?PLLIN 8			PRESCALER	PRESCALER
	6
-(Z(CLOCK
					LEVEL SHIFTERS
	DETECTOR						#LOCK
					6$$#/2%
	,3		(3% PRESENT OR NOT				SOURCE
							CONTROL
	#+?53"	USBENNAND NOT DEEPSLEEP
		CK?USB 6CO 6COOMUST BE AT -(Z
	#+?4)-4'/	TIMER EN AND NOTTDEEPSLEEP
							IF !0" PRESC X
		APB PERIPHEN AND NOTTDEEPSLEEP					ELSE	X
	#+?!0"
	#+?!0"	APB PERIPHEN AND NOT DEEPSLEEP
										-3 6

1.For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 24 MHz or 32 MHz.

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3.5Low power real-time clock and backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides two programmable alarms and programmable periodic interrupts with wakeup from Stop and Standby modes.

The programmable wakeup time ranges from 120 µs to 36 hours.

The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation.

The RTC can also be automatically corrected with a 50/60Hz stable powerline.

The RTC calendar can be updated on the fly down to sub second precision, which enables network system synchronisation.

A time stamp can record an external event occurrence, and generates an interrupt.

There are thirty-two 32-bit backup registers provided to store 128 bytes of user application data. They are cleared in case of tamper detection.

Three pins can be used to detect tamper events. A change on one of these pins can reset backup register and generate an interrupt. To prevent false tamper event, like ESD event, these three tamper inputs can be digitally filtered.

3.6GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high currentcapable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected to the 16 external interrupt lines. The 7 other lines are connected to RTC, PVD, USB or Comparator events.

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3.7Memories

The STM32L15xxD devices have the following features:

●48 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses).

●The non-volatile memory is divided into three arrays:

–384 Kbytes of embedded Flash program memory

–12 Kbytes of data EEPROM

–Options bytes

Flash program and data EEPROM are divided into two banks, this enables writing in one bank while running code or reading data in the other bank.

The options bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options:

–Level 0: no readout protection

–Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected

–Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse)

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.8FSMC (flexible static memory controller)

The FSMC supports the following modes: SRAM, PSRAM, NOR Flash.

Functionality overview:

●Up to 26 bit address bus

●Up to 16-bit data bus

●Write FIFO

●Burst mode

●Code execution from external memory

●Four chip select signals

●Up to 32 MHz external access (TBC)

3.9DMA (direct memory access)

The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, SDIO, general-purpose timers, DAC, and ADC.

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3.10LCD (liquid crystal display)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels.

●Internal step-up converter to guarantee functionality and contrast control irrespective of

VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD

●Supports static, 1/2, 1/3, 1/4 and 1/8 duty

●Supports static, 1/2, 1/3 and 1/4 bias

●Phase inversion to reduce power consumption and EMI

●Up to 8 pixels can be programmed to blink

●Unneeded segments and common pins can be used as general I/O pins

●LCD RAM can be updated at any time owing to a double-buffer

●The LCD controller can operate in Stop mode

3.11ADC (analog-to-digital converter)

A 12-bit analog-to-digital converters is embedded into STM32L15xxD devices with up to 40 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs with up to 29 external channel in a group.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers. An injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task.

The ADC includes a specific low power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC’s runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode.

3.11.1Temperature sensor

The temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature.

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

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To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

Table 3.	Temperature sensor calibration values
Calibration value name		Description	Memory address
		TS ADC raw data acquired at
TS_CAL1		temperature of 30 °C,	0x1FF8 00FA - 0x1FF8 00FB
		VDDA= 3 V
		TS ADC raw data acquired at
TS_CAL2		temperature of 110 °C	0x1FF8 00FE - 0x1FF8 00FF
		VDDA= 3 V

3.11.2Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 4.	Temperature sensor calibration values
Calibration value name		Description	Memory address
		Raw data acquired at
VREFINT_CAL		temperature of 30 °C	0x1FF8 00F8 - 0x1FF8 00F9
		VDDA= 3 V

3.12DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration.

This dual digital Interface supports the following features:

●Two DAC converters: one for each output channel

●Up to 10-bit output

●Left or right data alignment in 12-bit mode

●Synchronized update capability

●Noise-wave generation

●Triangular-wave generation

●Dual DAC channels, independent or simultaneous conversions

●DMA capability for each channel (including the underrun interrupt)

●External triggers for conversion

●Input reference voltage VREF+

Eight DAC trigger inputs are used in the STM32L15xxD. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

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3.13Operational amplifier

The STM32L15xxD embeds three operational amplifiers with external or internal follower routing capability (or even amplifier and filter capability with external components). When one operational amplifier is selected, one external ADC channel is used to enable output measurement.

The operational amplifiers feature:

●Low input bias current

●Low offset voltage

●Low power mode

●Rail-to-rail input

3.14Ultralow power comparators and reference voltage

The STM32L15xxD embeds two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O).

●One comparator with fixed threshold

●One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following:

–DAC output

–External I/O

–Internal reference voltage (VREFINT) or a submultiple (1/4, 1/2, 3/4)

Both comparators can wake up from Stop mode, and be combined into a window comparator.

The internal reference voltage is available externally via a low power / low current output buffer (driving current capability of 1 µA typical).

3.15System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate functions on different I/O ports.

The highly flexible routing interface allows the application firmware to control the routing of different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage

VREFINT.

3.16Touch sensing

The STM32L15xxD devices provide a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. In the STM32L15xxD, this acquisition is managed directly by

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the GPIOs, timers and analog I/O groups (see Section 3.15: System configuration controller and routing interface).

Reliable touch sensing solution can be quickly and easily implemented using the free STM32L1xx STMTouch firmware library.

3.17Timers and watchdogs

The ultralow power STM32L15xxD devices include seven general-purpose timers, two basic timers, and two watchdog timers.

Table 5 compares the features of the general-purpose and basic timers.

Table 5.		Timer feature comparison
Timer		Counter	Counter type	Prescaler factor	DMA request	Capture/compare	Complementary
		resolution			generation	channels	outputs
TIM2,			Up, down,	Any integer between
TIM3,		16-bit			Yes	4	No
			up/down	1 and 65536
TIM4
TIM5		32-bit	Up, down,	Any integer between	Yes	4	No
			up/down	1 and 65536
TIM9		16-bit	Up, down,	Any integer between	No	2	No
			up/down	1 and 65536
TIM10,		16-bit	Up	Any integer between	No	1	No
TIM11				1 and 65536
TIM6,		16-bit	Up	Any integer between	Yes	0	No
TIM7				1 and 65536

3.17.1General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11)

There are seven synchronizable general-purpose timers embedded in the STM32L15xxD devices (see Table 5 for differences).

TIM2, TIM3, TIM4, TIM5

TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input captures/output compares/PWMs on the largest packages.

TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10, TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

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TIM10, TIM11 and TIM9

TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers.

They can also be used as simple time bases and be clocked by the LSE clock source (32.768 kHz) to provide time bases independent from the main CPU clock.

3.17.2Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit time bases.

3.17.3SysTick timer

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0.

3.17.4Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardwareor software-configurable through the option bytes. The counter can be frozen in debug mode.

3.17.5Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.18Communication interfaces

3.18.1I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

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3.18.2Universal synchronous/asynchronous receiver transmitter (USART)

The three USART and two UART interfaces are able to communicate at speeds of up to 4 Mbit/s. They support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The three USARTs provide hardware management of the CTS and RTS signals.

All USART/UART interfaces can be served by the DMA controller.

3.18.3Serial peripheral interface (SPI)

Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

The SPIs can be served by the DMA controller.

3.18.4Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 96 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

3.18.5SDIO

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with the SD Memory Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1.

3.18.6Universal serial bus (USB)

The STM32L15xxD embeds a USB device peripheral compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated

48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

3.19CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

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Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.20Development support

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

The JTAG port can be permanently disabled with a JTAG fuse.

Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L15xxD through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

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Pin descriptions	STM32L151xD STM32L152xD

4 Pin descriptions

Table 6.

STM32L15xQD BGA132 ballout(1)

1

2

3

4

5

6

7

8

9

10

11

12

A

PE3

PE1

PB8

BOOT0

PD7

PD5

PB4

PB3

PA15

PA14

PA13

PA12

B

PE4

PE2

PB9

PB7

PB6

PD6

PD4

PD3

PD1

PC12

PC10

PA11

C

PC13-

PE5

PE0

VDD_3

PB5

PG14

PG13

PD2

PD0

PC11

PH2

PA10

WKUP2

PC14-

PE6-

D

OSC32

VSS_3

PF2

PF1

PF0

PG12

PG10

PG9

PA9

PA8

PC9

WKUP3

_IN

PC15-

E

OSC32

VLCD

VSS_6

PF3

PG5

PC8

PC7

PC6

_OUT

F

PH0

VSS_5

PF4

PF5

VSS_9

VSS_10

PG3

PG4

VSS_2

VSS_1

OSC_IN

PH1

G

OSC_

VDD_5

PF6

PF7

VDD_9

VDD_10

PG1

PG2

VDD_2

VDD_1

OUT

H

PC0

NRST

VDD_6

PF8

PG0

PD15

PD14

PD13

J

VSSA

PC1

PC2

PA4

PA7

PF9

PF12

PF14

PF15

PD12

PD11

PD10

OPAMP

K

3_

PC3

PA2

PA5

PC4

PF11

PF13

PD9

PD8

PB15

PB14

PB13

VINM

L

VREF+

PA0-

PA3

PA6

PC5

PB2

PE8

PE10

PE12

PB10

PB11

PB12

WKUP1

OPAM

OPAMP

M

VDDA

PA1

P1_

2_

PB0

PB1

PE7

PE9

PE11

PE13

PE14

PE15

VINM

VINM

1. This figure shows the package top view.

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Doc ID 022027 Rev 4

STM32L151xD STM32L152xD	Pin descriptions

Figure 3. STM32L15xZDLQFP144 pinout

0%

0%

0%

0%

0% 7+50

6,#$

0# 7+50 0# /3# ?).

0# /3# ?/54

0&

0&

0&

0&

0&

0&

633?

6$$?

0&

0&

0&

0&

0& /3#?).

/3#?/54

.234

0#

0#

0#

0#

633!

62%&

62%&

6$$!

0! 7+50

0!

0!

$$?		33?				0%			0%
6		6

0!			33?			$$? 0!
			6			6

0"

0"

"//4

0"

0"

0"

0"

0"

0'

6

6

0'

0'

0'

0'

0'

0'

$$?

33?

,1&0

0! 0! 0! 0# 0# 0" 0" 0" 0& 0&

633? 6 0& 0& 0& 0' 0'

$$?

	0$ 0$						$$?				33?		0$		0$
							6				6

0% 0% 0%										33?		$$? 0%
										6		6

	0$		0$		0$		0$		0#		0#		0#		0!		0!

0% 0% 0% 0% 0% 0" 0"														33?			$$?
														6			6

6$$?

633?

.#

0!

0!

0!

0!

0!

0!

0#

0#

0#

0#

6$$?

633?

0'

0'

0'

0'

0'

0'

0' 0$ 0$

6$$?

633?

0$

0$

0$

0$

0$

0$ 0" 0" 0" 0"

-3 6

Doc ID 022027 Rev 4

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Pin descriptions	STM32L151xD STM32L152xD

Figure 4. STM32L15xVD LQFP100 pinout

	VDD_3	VSS_3	PE1	PE0	PB9	PB8	BOOT0	PB7	PB6	PB5	PB4	PB3	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0	PC12	PC11	PC10	PA15	PA14
PE2	100	99	98	97	96	95	94	93	92	91	90	89	88	87	86	85	84	83	82	81	80	79	78	77	76
	1																								75
PE3	2																								74
PE4	3																								73
PE5	4																								72
PE6-WKUP3	5																								71
VLCD	6																								70
PC13-WKUP2	7																								69
PC14-OSC32_IN	8																								68
PC15-OSC32_OUT	9																								67
VSS_5	10																								66
VDD_5	11																								65
PH0-OSC_IN	12										LQFP100														64
PH1-OSC_OUT	13																								63
NRST	14																								62
PC0	15																								61
PC1	16																								60
PC2	17																								59
PC3	18																								58
VSSA	19																								57
VREF-	20																								56
VREF+	21																								55
VDDA	22																								54
PA0-WKUP1	23																								53
PA1	24																								52
PA2	25																								51
	26	27	28	29	30	31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50
	PA3	VSS_4	VDD_4	PA4	PA5	PA6	PA7	PC4	PC5	PB0	PB1	PB2	PE7	PE8	PE9	PE10	PE11	PE12	PE13	PE14	PE15	PB10	PB11	VSS_1	VDD_1

VDD_2 VSS_2 PH2 PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12

ai15692c

Figure 5. STM32L15xRD LQFP64 pinout

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA15

PA14

VLCD

VDD_2

PC13-WKUP2

VSS_

2

PC14-OSC32_IN

PA13

PC15-OSC32_OUT

PA12

PH0 -OSC_IN

PA11

PH1-OSC_OUT

PA10

NRST

PA9

PC0

LQFP64

PA8

PC1

PC9

PC2

PC8

PC3

PC7

VSSA

PC6

VDDA

PB15

PA0-WKUP1

PB14

PA1

PB13

PA2

PB12

PA3

VSS_4

VDD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

VSS_1

VDD_1

ai15693c

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Doc ID 022027 Rev 4