ST72361xx-Auto
8-bit MCU for automotive with Flash or ROM, 10-bit ADC, 5 timers, SPI, LINSCI™
Features
■Memories
–16 K to 60 K High Density Flash (HDFlash) or ROM with read-out protection capability. In-application programming and in-circuit programming for HDFlash devices
–1.5 to 2 K RAM
–HDFlash endurance: 100 cycles, data retention 20 years at 55 °C
■Clock, reset and supply management
–Low power crystal/ceramic resonator oscillators and bypass for external clock
–PLL for 2 x frequency multiplication
–5 power saving modes: halt, auto wake up from halt, active halt, wait and slow
■Interrupt management
–Nested interrupt controller
–14 interrupt vectors plus TRAP and RESET
–TLI top level interrupt (on 64-pin devices)
–Up to 21 external interrupt lines (on 4 vectors)
■Up to 48 I/O ports
–Up to 48 multifunctional bidirectional I/O lines
–Up to 36 alternate function lines
–Up to 6 high sink outputs
■5 timers
–16-bit timer with 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
–8-bit timer with 1 or 2 input captures, 1 or 2 output compares, PWM and pulse generator modes
–8-bit PWM auto-reload timer with 1 or 2 input captures, 2 or 4 independent PWM output channels, output compare and time base interrupt, external clock with event detector
LQFP32 7x7mm
LQFP44 10x10mm |
LQFP64 10x10mm |
–Main clock controller with real-time base and clock output
–Window watchdog timer
■Up to 3 communications interfaces
–SPI synchronous serial interface
–Master/ slave LINSCI™ asynchronous serial interface
–Master only LINSCI™ asynchronous serial interface
■Analog peripheral (low current coupling)
–10-bit A/D converter with up to 16 inputs
–Up to 9 robust ports (low current coupling)
■Instruction set
–8-bit data manipulation
–63 basic instructions
–17 main addressing modes
–8 x 8 unsigned multiply instruction
■Development tools
–Full hardware/ software development package
Table 1. Device summary
Reference |
Part number |
ST72361K4-Auto, ST72361K6-Auto,
ST72361K7-Auto, ST72361K9-Auto,
ST72361xx ST72361J4-Auto, ST72361J6-Auto,
-Auto ST72361J7-Auto, ST72361J9-Auto,
ST72361AR4-Auto, ST72361AR6-Auto,
ST72361AR7-Auto, ST72361AR9-Auto
August 2010 |
Doc ID 12468 Rev 3 |
1/279 |
www.st.com
Contents |
ST72361xx-Auto |
|
|
Contents
1 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
|
|
1.1 |
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
2 |
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
|
3 |
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
30 |
|
|
3.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
30 |
|
3.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
30 |
|
3.3 |
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
30 |
3.3.1 Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
|
3.4 |
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
|
3.5 |
ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
|
3.6 |
IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
|
3.7 |
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
|
3.8 |
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
4 |
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3.5 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 |
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . |
39 |
|
|
5.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
39 |
|
5.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
39 |
|
5.3 |
Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
39 |
|
5.4 |
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
|
5.5 |
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
41 |
5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
Contents |
|
|
5.5.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.4 Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.6 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.6.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.6.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.6.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.6.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.6.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6 |
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
|
|
6.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
|
6.2 |
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
|
6.3 |
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
51 |
|
6.4 |
Concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
51 |
|
6.5 |
Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
52 |
6.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.5.2 Interrupt software priority registers (ISPRX) . . . . . . . . . . . . . . . . . . . . . 53
6.6 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.6.1 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.6.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7 |
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
61 |
|
|
7.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
61 |
|
7.2 |
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
61 |
|
7.3 |
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
62 |
|
7.4 |
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
63 |
|
7.5 |
Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
65 |
|
7.6 |
Auto wake-up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
66 |
7.6.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8 |
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
71 |
|
|
8.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
71 |
|
8.2 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
71 |
8.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Doc ID 12468 Rev 3 |
3/279 |
Contents |
ST72361xx-Auto |
|
|
8.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.4 I/O port register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.4.1 |
Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
75 |
8.4.2 |
Interrupt ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
76 |
8.4.3 |
Pull-up input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
77 |
8.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9 |
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
80 |
|
|
9.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
80 |
|
9.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
80 |
|
9.3 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
80 |
|
9.4 |
Using halt mode with the WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
|
9.5 |
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
|
9.6 |
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
84 |
|
9.7 |
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
84 |
|
9.8 |
Using halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . |
85 |
|
9.9 |
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
85 |
|
9.10 |
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
85 |
9.10.1 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.10.2 Window Register (WDGWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10 |
Main clock controller with real time clock MCC/RTC . . . . . . . . . . . . . . |
87 |
|
|
10.1 |
Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
87 |
|
10.2 |
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
87 |
|
10.3 |
Real time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
87 |
|
10.4 |
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
|
10.5 |
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
|
10.6 |
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
|
|
10.6.1 MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
11 |
PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
91 |
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
Contents |
|
|
11.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.2.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.2.2 Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.2.3 Counter and prescaler Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.2.4 Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.2.5 Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.2.6 Output compare and Time base interrupt . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.7 External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.8 Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.9 External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12 |
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
102 |
|
|
12.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
102 |
|
12.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
102 |
|
12.3 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
103 |
12.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.3 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.5 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.3.6 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.3.7 Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3.8 One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.3.9 Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.7.1 Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.7.2 Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.7.3 Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.7.4 Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.7.5 Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.7.6 Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 120 12.7.7 Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 120
Doc ID 12468 Rev 3 |
5/279 |
Contents |
|
|
ST72361xx-Auto |
|
|
|
|
|
12.7.8 |
Output compare 2 high register (OC2HR) . . . . . . . . . . . |
. . . . . . . . . . . 120 |
|
12.7.9 |
Output compare 2 low register (OC2LR) . . . . . . . . . . . . . |
. . . . . . . . . . 121 |
|
12.7.10 |
Counter high register (CHR) . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . 121 |
|
12.7.11 |
Counter low register (CLR) . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . 121 |
|
12.7.12 |
Alternate counter high register (ACHR) . . . . . . . . . . . . . . |
. . . . . . . . . . 121 |
|
12.7.13 |
Alternate counter low register (ACLR) . . . . . . . . . . . . . . . |
. . . . . . . . . . 122 |
|
12.7.14 |
Input capture 2 high register (IC2HR) . . . . . . . . . . . . . . . |
. . . . . . . . . . 122 |
|
12.7.15 |
Input capture 2 low register (IC2LR) . . . . . . . . . . . . . . . . |
. . . . . . . . . . 122 |
13 |
8-bit timer (TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 124 |
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.3.2 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.3.3 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.3.4 Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.3.5 One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.3.6 Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
13.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
|
13.7.1 Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 137 |
|
|
13.7.2 Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
138 |
|
|
13.7.3 |
Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
139 |
|
13.7.4 Input capture 1 register (IC1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
140 |
|
|
13.7.5 Output compare 1 register (OC1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . |
140 |
|
|
13.7.6 Output compare 2 register (OC2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . |
141 |
|
|
13.7.7 |
Counter register (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
141 |
|
13.7.8 Alternate counter register (ACTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
141 |
|
|
13.7.9 Input capture 2 register (IC2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
141 |
|
|
13.8 8-bit timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
142 |
|
14 |
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
143 |
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
Contents |
|
|
14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
14.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.3.2 Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.3.3 Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.3.4 Master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.3.5 Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.3.6 Slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
14.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14.5.1 Master mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.5.2 Overrun condition (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.5.3 Write collision error (WCOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14.8.1 Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.8.2 Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.8.3 Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15 |
LINSCI serial communication interface (LIN master/slave) . . . . . . . . |
156 |
|
|
15.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
156 |
|
15.2 |
SCI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
156 |
|
15.3 |
LIN features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
157 |
|
15.4 |
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
157 |
|
15.5 |
SCI mode - functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
158 |
15.5.1 Conventional baud rate generator mode . . . . . . . . . . . . . . . . . . . . . . . 158 15.5.2 Extended prescaler mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.5.3 Serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.5.4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.5.5 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.5.6 Extended baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.5.7 Receiver muting and wake-up feature . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.5.8 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
15.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 15.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Doc ID 12468 Rev 3 |
7/279 |
Contents |
ST72361xx-Auto |
|
|
15.8 SCI mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.8.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.8.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.8.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.8.4 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.8.5 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.8.6 Extended receive prescaler division register (SCIERPR) . . . . . . . . . . 172 15.8.7 Extended transmit prescaler division register (SCIETPR) . . . . . . . . . . 173
15.9LIN mode - functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
15.9.1 |
Entering LIN mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
173 |
15.9.2 |
LIN transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
174 |
15.9.3 |
LIN reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
175 |
15.9.4 |
LIN error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
177 |
15.9.5 |
LIN baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
180 |
15.9.6 |
LIN slave baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
180 |
15.9.7 |
LINSCI clock tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
181 |
15.9.8 |
Clock deviation causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
182 |
15.9.9 |
Error due to LIN synch measurement . . . . . . . . . . . . . . . . . . . . . . . . . |
183 |
15.9.10 |
Error due to baud rate quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . |
183 |
15.9.11 |
Impact of clock deviation on maximum baud rate . . . . . . . . . . . . . . . . |
183 |
15.10 LIN mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.10.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.10.2 Control Register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.10.3 Control Register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.10.4 Control register 3 (SCICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.10.5 LIN divider registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.10.6 LIN prescaler register (LPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.10.7 LIN prescaler fraction register (LPFR) . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.10.8 LIN header length register (LHLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
16 |
LINSCI serial communication interface (LIN master only) . . . . . . . . |
193 |
|
|
16.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
193 |
|
16.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
193 |
|
16.3 |
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
194 |
|
16.4 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
195 |
|
|
16.4.1 Serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 196 |
8/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
Contents |
|
|
16.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16.4.4 Conventional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 16.4.5 Extended baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 16.4.6 Receiver muting and wake-up feature . . . . . . . . . . . . . . . . . . . . . . . . . 201 16.4.7 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
16.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.7 SCI synchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
16.8.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.8.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.8.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.8.4 Control Register 3 (SCICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.8.5 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.8.6 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.8.7 Extended receive prescaler division register (SCIERPR) . . . . . . . . . . 212 16.8.8 Extended transmit prescaler division register (SCIETPR) . . . . . . . . . . 212
17 |
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
214 |
|
|
17.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
214 |
|
17.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
214 |
|
17.3 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
214 |
17.3.1 Digital A/D conversion result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 17.3.2 A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 17.3.3 Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 17.3.4 ADCDR consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
17.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 17.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 17.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
17.6.1 Control/status register (ADCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 17.6.2 Data register (ADCDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 17.6.3 Data register (ADCDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
18 |
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
219 |
|
18.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
219 |
Doc ID 12468 Rev 3 |
9/279 |
Contents |
ST72361xx-Auto |
|
|
18.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 18.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 18.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
18.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
18.2.1 Using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
19 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
227 |
|
19.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
227 |
19.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
19.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
19.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 19.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 19.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
19.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
19.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 19.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 230 19.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 231
19.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
19.4.1 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 19.4.2 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
19.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
19.5.1 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 235 19.5.2 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
19.6 Auto wakeup from halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . 237 19.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
19.7.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 19.7.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
19.8 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
10/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
Contents |
|
|
19.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 238 19.8.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 19.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 239
19.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
19.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 19.9.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
19.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
19.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 19.10.2 ICCSEL/ VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
19.11 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 19.12 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 250
19.12.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
19.13 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
20 |
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
257 |
|
|
20.1 |
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 257 |
|
20.2 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
257 |
|
20.3 |
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
259 |
|
20.4 |
Packaging for automatic handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
259 |
21 Device configuration and ordering information . . . . . . . . . . . . . . . . . 260
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 21.2 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
21.2.1 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 21.2.2 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
21.3 Transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
22 |
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
268 |
23 |
Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
269 |
|
23.1 All devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
269 |
23.1.1 RESET pin protection with LVD enabled . . . . . . . . . . . . . . . . . . . . . . . 269 23.1.2 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 269 23.1.3 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 23.1.4 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 23.1.5 Header time-out does not prevent wake-up from mute mode . . . . . . . 272
Doc ID 12468 Rev 3 |
11/279 |
Contents ST72361xx-Auto
|
23.2 |
Flash/FastROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
273 |
|
|
23.2.1 LINSCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 273 |
|
|
23.2.2 16-bit and 8-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
275 |
|
23.3 |
ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
275 |
|
|
23.3.1 16-bit timer PWM mode buffering feature change . . . . . . . . . . . . . . . . |
275 |
24 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
276 |
12/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
List of tables |
|
|
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 4. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5. Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6. Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 7. Interrupt software priority selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 8. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 9. Effect of low power modes on SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 10. Interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 11. Reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 12. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 13. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 14. Interrupt priority bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 15. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 16. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 17. Interrupt sensitivity - ei3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 18. Interrupt sensitivity - ei2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 19. Interrupt sensitivity - ei1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 20. Interrupt sensitivity - ei0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 21. Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 22. MCC/RTC low power mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 23. AWUPR prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 24. AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 25. DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 26. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 27. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 28. Configuration of PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0, PF7:0 . . . . . . . . . . . . . . . 75 Table 29. Configuration of PA0, 2, 4, 6; PB0, 2,4; PC1; PD0,6 (with pull-up) . . . . . . . . . . . . . . . . . . 76 Table 30. Configuration of PA1, 3, 5, 7; PB1,3,5; PC2; PD1, 4, 7 (without pull-up) . . . . . . . . . . . . . . 76 Table 31. Configuration of PC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 32. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 33. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 34. I/O port interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 35. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 36. Effect of low power modes on WDG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 37. Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 38. Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 39. MCC/RTC Interrupt control wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 40. CPU clock frequency in SLOW mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 41. Time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 42. Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 43. Counter clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 44. PWM frequency vs resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 45. PWMx output level and polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 46. PWM auto-reload timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 47. Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 48. Timer interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Doc ID 12468 Rev 3 |
13/279 |
List of tables |
ST72361xx-Auto |
|
|
Table 49. Timer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 50. Clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 51. 16-bit timer register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 52. Effect of low power modes on TIM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 53. TIM8 interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 54. Timer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 55. Clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 56. Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 57. SPI interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 58. SPI master mode SCK frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 59. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 60. Character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 61. Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 62. SCI interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 63. PR prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 64. Transmitter rate divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 65. Receiver rate divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 66. LIN mode configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Table 67. LDIV mantissa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 68. LDIV fraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 69. LHL mantissa coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 70. LHL fraction coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 71. LINSCI1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 72. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Table 73. Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 74. SCI interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 75. LIN sync break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 76. SCI clock on SCLK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 77. PR prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 78. Transmitter rate divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 79. Receiver rate divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 80. Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 81. LINSCI2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 82. Effect of low power modes on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Table 83. A/D clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Table 84. ADC channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Table 85. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Table 86. Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 87. CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 88. Instructions supporting direct, indexed, indirect and indirect indexed addressing (part 1) 222 Table 89. Instructions supporting direct, indexed, indirect and indirect indexed addressing (part 2) 222 Table 90. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Table 91. Supply current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Table 92. Clock source current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Table 93. Peripheral consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Table 94. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Table 95. External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Table 96. Oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Table 97. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Table 98. AWU oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 99. RAM supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 100. Dual voltage HDFlash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
14/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
List of tables |
|
|
Table 101. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 102. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 103. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Table 104. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Table 105. I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Table 106. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Table 107. RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 108. ICCSEL/VPP pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table 109. 8-bit PWM-ART auto reload timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 110. 8-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Table 111. 16-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Table 112. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Table 113. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 114. ADC accuracy with fCPU = 8 MHz, fADC = 4 MHz RAIN < 10kW, VDD = 5V. . . . . . . . . . . . 255 Table 115. Package selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 116. Alternate function remapping 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Table 117. Alternate function remapping 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Table 118. OSCTYPE selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Table 119. OSCRANGE selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Table 120. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Doc ID 12468 Rev 3 |
15/279 |
List of figures |
ST72361xx-Auto |
|
|
List of figures
Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 2. LQFP 64-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 3. LQFP 44-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4. LQFP 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 5. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 6. Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 9. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 10. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 11. Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 12. RESET sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 13. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 14. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 15. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 16. Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 17. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 18. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 19. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 20. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 21. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 22. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 23. SLOW mode clock transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 24. WAIT mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 25. HALT timing overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 26. HALT mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 27. ACTIVE HALT timing overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 28. ACTIVE HALT mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 29. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 30. AWUF halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 31. AWUFH mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 32. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 33. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 34. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 35. Approximate timeout duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 36. Exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 37. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 38. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 39. PWM auto-reload timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 40. Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 41. PWM auto-reload timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 42. PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 43. External event detector example (3 counts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 44. Input capture timing diagram, fCOUNTER = fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 45. Input capture timing diagram, fCOUNTER = fCPU / 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 46. ART external interrupt in halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 47. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 48. 16-bit read sequence: (from counter or alternate counter register) . . . . . . . . . . . . . . . . . 104
16/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
List of figures |
|
|
Figure 49. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 50. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 51. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 52. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 53. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 54. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 55. Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 56. Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 57. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 58. Pulse width modulation mode timing example with 2 output compare functions . . . . . . . 113 Figure 59. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 60. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 61. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 62. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 63. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 64. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 65. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 66. Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 67. Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 68. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 69. Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 70. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 71. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 72. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 73. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 74. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 75. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 150 Figure 76. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 77. SCI block diagram (in conventional baud rate generator mode). . . . . . . . . . . . . . . . . . . . 158 Figure 78. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Figure 79. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Figure 80. LIN characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 81. SCI block diagram in LIN slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 82. LIN header reception timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Figure 83. LIN synch field measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Figure 84. LDIV read / write operations when LDUM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Figure 85. LDIV read / write operations when LDUM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Figure 86. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Figure 87. LSF bit set and clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Figure 88. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Figure 89. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Figure 90. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Figure 91. SCI example of synchronous and asynchronous transmission . . . . . . . . . . . . . . . . . . . . 204 Figure 92. SCI data clock timing diagram (M = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Figure 93. SCI data clock timing diagram (M = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Figure 94. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 95. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 96. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 97. fCPU maximum vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Figure 98. LVD startup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 99. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Figure 100. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Doc ID 12468 Rev 3 |
17/279 |
List of figures |
ST72361xx-Auto |
|
|
Figure 101. PLL jitter vs signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Figure 102. AWU oscillator freq. @ TA 25°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Figure 103. Connecting unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Figure 104. RPU vs VDD with VIN = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Figure 105. IPU vs VDD with VIN = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Figure 106. Typical VOL at VDD = 5V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Figure 107. Typical VOL at VDD = 5V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Figure 108. Typical VOH at VDD = 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Figure 109. Typical VOL vs VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Figure 110. Typical VOL vs VDD (high-sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Figure 111. Typical VOH vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Figure 112. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Figure 113. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Figure 114. RESET RPU vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Figure 115. Two typical applications with ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Figure 116. SPI slave timing diagram with CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Figure 117. SPI slave timing diagram with CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Figure 118. SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Figure 119. RAIN max vs fADC with CAIN = 0pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Figure 120. Recommended CAIN/RAIN values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Figure 121. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Figure 122. Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Figure 123. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Figure 124. 32-pin low profile quad flat package (7x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Figure 125. 44-pin low profile quad flat package (10x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Figure 126. 64-pin low profile quad flat package (10 x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Figure 127. pin 1 orientation in tape and reel conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Figure 128. ST72F361xx-Auto Flash commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Figure 129. ST72P361xxx-Auto FastROM commercial product structure . . . . . . . . . . . . . . . . . . . . . . 265 Figure 130. ST72361xx-Auto ROM commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Figure 131. Header reception event sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Figure 132. LINSCI interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
18/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
Description |
|
|
The ST72361xx-Auto devices are members of the ST7 microcontroller family designed for automotive mid-range applications with LIN (Local Interconnect Network) interface.
All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory.
The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
Table 2. |
Product overview |
|
|
|
|
Features |
ST72361(AR/J/K)9 |
ST7261(AR/J/K)7 |
ST72361(AR/J/K)6 |
ST72361(AR/J/K)4 |
|
|
|
|
|
|
|
Program memory - |
60K |
48K(1) |
32K |
16K |
|
bytes |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
RAM (stack) - bytes |
2K (256) |
2K (256) |
1.5K (256) |
1.5K (256) |
|
|
|
|
|
|
|
Operating supply |
|
4.5V to 5.5V |
|
||
|
|
|
|
||
CPU frequency |
|
External resonator oscillator w/ PLLx2/8 MHz |
|
||
|
|
|
|
|
|
Maximum |
|
-40°C to +125°C |
|
||
temperature range |
|
|
|||
|
|
|
|
||
|
|
||||
Packages |
LQFP64 10x10mm (AR), LQFP44 10x10mm (J), LQFP32 7x7mm (K) |
||||
|
|
|
|
|
|
1.FASTROM and ROM versions only.
Doc ID 12468 Rev 3 |
19/279 |
Description |
ST72361xx-Auto |
|
|
Figure 1. |
Device block diagram |
|
|
|
|
option |
|
|
|
OSC1 |
PLL x 2 |
|
PWM |
|
OSC2 |
OSC |
|
ART |
|
|
|
|
||
|
/2 |
|
|
|
|
|
|
8-Bit |
|
|
|
|
TIMER |
|
|
|
|
16-Bit |
|
|
|
|
TIMER |
|
|
|
|
PORT A |
PA7:0 |
VDD |
POWER |
|
(8 bits)1 |
|
VSS |
SUPPLY |
|
PORT B |
PB7:0 |
|
|
(8 bits)1 |
||
|
|
|
||
|
|
|
PORT C |
PC7:0 |
|
|
ADDRESS |
(8 bits)1 |
|
RESET |
CONTROL |
PORT D |
PD7:0 |
|
TLI1 |
|
(8 bits)1 |
||
|
8-BIT CORE |
AND |
PORT E |
PE7:0 |
|
(8 bits)1 |
|||
|
ALU |
DATA |
|
(8 bits)1 |
|
|
|
PORT F |
PF7:0 |
|
|
|
|
|
|
PROGRAM |
BUS |
|
|
|
|
SPI |
|
|
|
MEMORY |
|
|
|
|
(16 - 60 Kbytes) |
|
LINSCI2 |
|
|
|
|
(LIN master) |
|
|
RAM |
|
LINSCI1 |
|
|
(1.5 - 2 Kbytes) |
|
|
|
|
|
(LIN master/slave) |
|
|
|
|
|
WINDOW |
|
|
MCC |
|
WATCHDOG |
|
|
|
|
|
|
|
(Clock Control) |
|
|
|
1. On some devices only (see Table 2: Product overview)
20/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
Description |
|
|
Figure 2. LQFP 64-pin package pinout
OSC1
OSC2 ARTIC1 / PA0 PWM0 / PA1
PWM1 / (HS) PA2 PWM2 / PA3
PWM3 / PA4 VSS_3
VDD_3
ARTCLK / (HS)PA5 ARTIC2 / (HS) PA6 T8_OCMP2 / PA7 T8_ICAP2 / PB0 T8_OCMP1 / PB1 T8_ICAP1 / PB2 MCO / PB3
PF7 |
PF6 |
/PD7AIN11 |
/PD6AIN10 |
|
RESET |
/PD5LINSCI2 TDO |
V |
V |
V |
V |
/PD4LINSCI2 RDI |
(HS)/PD3 LINSCI2 SCK |
PF5 |
TLI |
PF4 |
/PF3AIN9 |
|
||||||||||||||||
|
|
|
|
|
|
|
DD0 |
DDA |
SS 0 |
SSA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ei3 |
|
|
|
ei3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ei3 |
|
|
ei0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ei1 |
|
|
|
|
ei1 |
|
|
|
|
ei2 |
|
|
|
||
|
|
ei1 |
|
|
|
|
|
|
|
|
|
|||||
AIN12 / PE0 |
AIN13 / PE1 |
ICCCLK / AIN0 / PB4 |
AIN14 / PE2 |
|
AIN15 / PE3 |
ICCDATA / AIN1 / PB5 |
(*)T16 OCMP1 / AIN2 / PB6 |
SS2 |
DD2 |
(*)T16 OCMP2 / AIN3 / PB7 |
(*)T16 ICAP1 / AIN4 / PC0 |
(*)T16 ICAP2 / (HS) PC1 |
T16 EXTCLK / (HS) PC2 |
PE4 |
NC |
PP |
|
V |
V |
ICCSEL/V |
PD2 / LINSCI1_TDO
PD1 / LINSCI1_RDI
PF2 / AIN8
PF1 / AIN7
PF0
PE7
PD0 / SPI_SS / AIN6
VDD_1
VSS_1
PC7 / SPI_SCK
PC6 / SPI_MOSI
PC5 / SPI_MISO
PE6 / AIN5
PE5
PC4
PC3
(HS) 20mA high sink capability
eix associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
Doc ID 12468 Rev 3 |
21/279 |
Description |
ST72361xx-Auto |
|
|
Figure 3. LQFP 44-pin package pinout
|
|
|
1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SCK |
|
|
|
|
||||||||
|
|
|
/PD7AIN11 /PD6AIN10 |
|
RESET /PD5LINSCI2 TDO V |
V |
V |
V /PD4LINSCI2 RDI |
(HS)PD3 / LINSCI2_ |
PF5 |
|
|||||||||||||||||||||
|
|
|
|
|
||||||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
DD0 |
|
DDA |
|
SS 0 |
|
SSA |
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
OSC1 |
44 43 42 41 40 39 38 37 36 35 34 |
|
||||||||||||||||||||||||||||||
|
1 |
|
ei3 |
|
|
|
|
|
|
|
|
|
|
ei3 |
|
|
33 |
|
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||||
OSC2 |
|
2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ei3 |
32 |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
PWM0 / PA1 |
|
3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
31 |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
PWM1 / (HS) PA2 |
|
4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
30 |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
PWM2 / PA3 |
|
5 |
|
ei0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
ei3 |
29 |
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||
PWM3 / PA4 |
|
6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
28 |
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
ARTCLK / (HS)PA5 |
|
7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
27 |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
ARTIC2 / (HS) PA6 |
|
8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
26 |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
T8_OCMP1 / PB1 |
|
9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
25 |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
T8_ICAP1 / PB2 |
|
10 |
|
ei1 |
|
|
|
|
|
|
|
|
ei2 |
|
|
24 |
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||||||
MCO / PB3 |
|
11 |
|
|
ei1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
23 |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||
|
12 13 14 15 16 17 18 19 20 21 22 |
|
||||||||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD2 / LINSCI1_TDO PD1 / LINSCI1_RDI PF2 / AIN8
PF1 / AIN7
PD0 / SPI_SS / AIN6 PC7 / SPI_SCK PC6 / SPI_MOSI PC5 / SPI_MISO PE6 / AIN5
PC4
PC3
|
|
|
SS2 |
DD2 |
|
ICCCLK / AIN0PB4/ |
ICCDATA / AIN1PB5/ |
(*)T16 OCMP1 / AIN2PB6/ |
V |
V (*)T16 OCMP2 / AIN3PB7/ (*)T16 ICAP1 / AIN4PC0/ (*)T16 ICAP2 / (HS)PC1 T16 EXTCLK / (HS)PC2 PE4 |
ICCSEL/VPP |
(HS) 20mA high sink capability
eix associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
22/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
Description |
|
|
Figure 4. LQFP 32-pin package pinout
|
|
|
|
|
|
|
1 |
|
|
|
PD5/ LINSCI2 TDO V |
|
|
V PD4/ LINSCI2 RDI |
SCK |
|
|
RESET |
V |
V |
PD3(HS) / LINSCI2_ |
||
|
|
|
DD0 |
DDA |
SS0 |
SSA |
|
OSC1 |
|
32 31 30 29 28 27 26 25 |
|||||
1 |
|
|
|
|
ei3 |
24 |
|
OSC2 |
2 |
|
|
|
|
23 |
|
|
|
|
|
ei3 |
|||
PWM0 / PA1 |
3 |
|
|
|
|
22 |
|
|
|
|
|
|
|||
PWM1 / (HS) PA2 |
4 |
|
ei0 |
|
|
|
21 |
ARTCLK / (HS) PA5 |
5 |
|
|
|
|
|
20 |
T8_OCMP1 / PB1 |
6 |
|
|
|
|
|
19 |
T8_ICAP1 / PB2 |
7 |
ei1 |
|
|
ei2 |
18 |
|
MCO / PB3 |
8 |
|
ei1 |
|
|
17 |
|
|
|
|
|
|
|||
|
|
9 |
10 11 12 13 14 15 16 |
PD2 / LINSCI1_TDO PD1 / LINSCI1_RDI PD0 / SPI_SS / AIN6 PC7 / SPI_SCK PC6 / SPI_MOSI PC5 / SPI_MISO PC4
PC3
ICCCLK / AIN0 / PB4 ICCDATA / AIN1 / PB5 T16 OCMP1 / AIN2 / PB6 T16 OCMP2 / AIN3 / PB7 T16 ICAP1 / AIN4 / PC0 |
T16 ICAP2 / (HS) PC1 |
T16 EXTCLK / (HS) PC2 |
PP |
ICCSEL/V |
(HS) 20mA high sink capability
eix associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
For external pin connection guidelines, refer to Chapter 20: Electrical characteristics.
Doc ID 12468 Rev 3 |
23/279 |
Description |
ST72361xx-Auto |
|
|
List of abbreviations used in Table 3 |
|
Type: |
I = input, O = output, S = supply |
In/Output level: |
CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger |
|
TT= TTL 0.8V / 2V with Schmitt trigger |
Output level: |
HS = 20mA high sink (on N-buffer only) |
|
Port and control configuration: |
Input: |
float = floating, wpu = weak pull-up, int = interrupt, ana = analog, |
|
RB = robust |
Output: |
OD = open drain, PP = push-pull |
Refer to Chapter 8: I/O ports for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 3. |
|
Device pin description |
|
|
|
|
|
|
|
|
|
|
|
||||
|
Pin n° |
|
|
|
Level |
|
|
Port |
|
|
Main |
|
|
||||
|
|
|
|
|
|
Type |
|
|
|
|
|
|
|
|
|
|
|
LQFP64 |
|
LQFP44 |
|
LQFP32 |
Pin name |
Input |
Output |
float |
Input(1) |
ana |
Output |
function |
Alternate function |
||||
|
|
|
wpu int |
OD |
PP |
(after |
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
reset) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
|
1 |
|
1 |
OSC1(2) |
I |
|
|
|
|
|
|
|
|
External clock input or resonator |
||
|
|
|
|
|
|
|
|
|
|
oscillator inverter input |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
2 |
|
2 |
|
2 |
OSC2(2) |
I/O |
|
|
|
|
|
|
|
|
Resonator oscillator inverter output |
||
3 |
|
- |
|
- |
PA0 / ARTIC1 |
I/O |
CT |
|
X |
ei0 |
|
X |
X |
Port A0 |
ART input capture 1 |
||
4 |
|
3 |
|
3 |
PA1 / PWM0 |
I/O |
CT |
|
X |
|
ei0 |
|
X |
X |
Port A1 |
ART PWM output 0 |
|
5 |
|
4 |
|
4 |
PA2 (HS) / PWM1 |
I/O |
CT |
HS |
X |
ei0 |
|
X |
X |
Port A2 |
ART PWM output 1 |
||
6 |
|
5 |
|
- |
PA3 / PWM2 |
I/O |
CT |
|
X |
|
ei0 |
|
X |
X |
Port A3 |
ART PWM output 2 |
|
7 |
|
6 |
|
- |
PA4 / PWM3 |
I/O |
CT |
|
X |
ei0 |
|
X |
X |
Port A4 |
ART PWM output 3 |
||
8 |
|
- |
|
- |
VSS_3 |
S |
|
|
|
|
|
|
|
|
Digital ground voltage |
|
|
9 |
|
- |
|
- |
VDD_3 |
S |
|
|
|
|
|
|
|
|
Digital main supply voltage |
||
10 |
|
7 |
|
5 |
PA5 (HS) / ARTCLK |
I/O |
CT |
HS |
X |
|
ei0 |
|
X |
X |
Port A5 |
ART external clock |
|
11 |
|
8 |
|
- |
PA6 (HS) / ARTIC2 |
I/O |
CT |
HS |
X |
ei0 |
|
X |
X |
Port A6 |
ART input capture 2 |
||
12 |
|
- |
|
- |
PA7 / T8_OCMP2 |
I/O |
CT |
|
X |
|
ei0 |
|
X |
X |
Port A7 |
TIM8 output capture 2 |
|
13 |
|
- |
|
- |
PB0 /T8_ICAP2 |
I/O |
CT |
|
X |
ei1 |
|
X |
X |
Port B0 |
TIM8 input capture 2 |
||
14 |
|
9 |
|
6 |
PB1 /T8_OCMP1 |
I/O |
CT |
|
X |
|
ei1 |
|
X |
X |
Port B1 |
TIM8 output capture 1 |
|
15 |
|
10 |
|
7 |
PB2 / T8_ICAP1 |
I/O |
CT |
|
X |
ei1 |
|
X |
X |
Port B2 |
TIM8 input capture 1 |
||
16 |
|
11 |
|
8 |
PB3 / MCO |
I/O |
CT |
|
X |
|
ei1 |
|
X |
X |
Port B3 |
Main clock out (fOSC2) |
|
17 |
|
- |
|
- |
PE0 / AIN12 |
I/O |
TT |
|
X |
X |
|
RB |
X |
X |
Port E0 |
ADC analog input 12 |
|
18 |
|
- |
|
- |
PE1 / AIN13 |
I/O |
TT |
|
X |
X |
|
RB |
X |
X |
Port E1 |
ADC analog input 13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ICC clock |
ADC |
19 |
|
12 |
|
9 |
PB4 / AIN0 / ICCCLK |
I/O |
CT |
|
X |
ei1 |
RB |
X |
X |
Port B4 |
analog |
||
|
|
|
input |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
input 0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
24/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
|
|
|
|
|
|
|
|
|
|
|
Description |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 3. |
|
Device pin description (continued) |
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin n° |
|
|
|
|
|
Level |
|
|
Port |
|
|
Main |
|
|
|
||||
|
|
|
|
|
|
|
|
Type |
|
|
|
|
|
|
|
|
|
|
|
|
LQFP64 |
|
LQFP44 |
|
LQFP32 |
Pin name |
Input |
Output |
float |
Input(1) |
ana |
Output |
function |
Alternate function |
|||||||
|
|
|
|
|
wpu |
int |
OD |
PP |
(after |
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
reset) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
20 |
|
- |
|
- |
PE2 / AIN14 |
I/O |
TT |
|
X |
X |
|
RB |
X |
X |
Port E2 |
ADC analog input 14 |
||||
21 |
|
- |
|
- |
PE3 / AIN15 |
I/O |
TT |
|
X |
X |
|
RB |
X |
X |
Port E3 |
ADC analog input 15 |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ICC data |
|
ADC |
22 |
|
13 |
|
10 |
PB5 / AIN1 / ICCDATA |
I/O |
C |
|
X |
|
ei1 |
RB |
X |
X |
Port B5 |
|
analog |
|||
|
|
|
|
|
|
|
|
|
T |
|
|
|
|
|
|
|
|
input |
|
input 1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB6 / AIN2 / |
|
|
|
|
|
|
|
|
|
|
TIM16 |
|
ADC |
||
23 |
|
14 |
|
11 |
I/O |
C |
|
X |
X |
|
RB |
X |
X |
Port B6 |
output |
|
analog |
|||
|
|
|
|
|
T16_OCMP1 |
|
T |
|
|
|
|
|
|
|
|
compare 1 |
|
input 2 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
24 |
|
15 |
|
- |
VSS_2 |
S |
|
|
|
|
|
|
|
|
Digital ground voltage |
|||||
25 |
|
16 |
|
- |
VDD_2 |
S |
|
|
|
|
|
|
|
|
Digital main supply voltage |
|||||
|
|
|
|
|
PB7 /AIN3 / |
|
|
|
|
|
|
|
|
|
|
TIM16 |
|
ADC |
||
26 |
|
17 |
|
12 |
I/O |
C |
|
X |
X |
|
RB |
X |
X |
Port B7 |
output |
|
analog |
|||
|
|
|
|
|
T16_OCMP2 |
|
T |
|
|
|
|
|
|
|
|
compare 2 |
|
input 3 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC0 / AIN4 / |
|
|
|
|
|
|
|
|
|
|
TIM16 |
|
ADC |
||
27 |
|
18 |
|
13 |
I/O |
C |
|
X |
X |
|
RB |
X |
X |
Port C0 |
input |
|
analog |
|||
|
|
|
|
|
T16_ICAP1 |
|
T |
|
|
|
|
|
|
|
|
capture 1 |
|
input 4 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
28 |
|
19 |
|
14 |
PC1 (HS) / |
I/O |
C |
HS |
X |
ei2 |
|
X |
X |
Port C1 |
TIM16 input capture 2 |
|||||
|
|
|
|
|
T16_ICAP2 |
|
T |
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
29 |
|
20 |
|
15 |
PC2 (HS) / |
I/O |
C |
HS |
X |
|
ei2 |
|
X |
X |
Port C2 |
TIM16 external clock |
||||
|
|
|
|
|
T16_EXTCLK |
|
T |
|
|
|
|
|
|
|
|
input |
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
30 |
|
21 |
|
- |
PE4 |
I/O |
TT |
|
X |
X |
|
|
X |
X |
|
Port E4 |
|
|
||
31 |
|
- |
|
- |
NC |
|
|
|
|
|
|
Not Connected |
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
32 |
|
22 |
|
16 |
VPP |
I |
|
|
|
|
|
|
|
|
Flash programming voltage.Must |
|||||
|
|
|
|
|
|
|
|
|
|
be tied low in user mode |
||||||||||
33 |
|
23 |
|
17 |
PC3 |
I/O |
CT |
|
X |
X |
|
|
X |
X |
Port C3 |
|
|
|
||
34 |
|
24 |
|
18 |
PC4 |
I/O |
C |
|
X |
|
|
|
|
X(3) |
Port C4 |
|
|
|
||
|
|
|
|
|
|
|
|
|
T |
|
|
|
|
|
|
|
|
|
|
|
35 |
|
- |
|
- |
PE5 |
I/O |
TT |
|
X |
X |
|
|
X |
X |
|
Port E5 |
|
|
||
36 |
|
25 |
|
- |
PE6 / AIN5 |
I/O |
TT |
|
X |
X |
|
X |
X |
X |
Port E6 |
ADC analog input 5 |
||||
37 |
|
26 |
|
19 |
PC5 /MISO |
I/O |
CT |
|
X |
X |
|
|
X |
X |
Port C5 |
SPI master in/slave out |
||||
38 |
|
27 |
|
20 |
PC6 / MOSI |
I/O |
CT |
|
X |
X |
|
|
X |
X |
Port C6 |
SPI master out/slave in |
||||
39 |
|
28 |
|
21 |
PC7 /SCK |
I/O |
CT |
|
X |
X |
|
|
X |
X |
Port C7 |
SPI serial clock |
||||
40 |
|
- |
|
- |
VSS_1 |
S |
|
|
|
|
|
|
|
|
Digital ground voltage |
|
|
|||
41 |
|
- |
|
- |
VDD_1 |
S |
|
|
|
|
|
|
|
|
Digital main supply voltage |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SPI slave |
|
ADC |
42 |
|
29 |
|
22 |
PD0 / |
SS/ |
AIN6 |
I/O |
C |
|
X |
ei3 |
X |
X |
X |
Port D0 |
|
analog |
||
|
|
|
|
|
|
|
|
|
T |
|
|
|
|
|
|
|
|
select |
|
input 6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
43 |
|
- |
|
- |
PE7 |
I/O |
TT |
|
X |
X |
|
|
X |
X |
|
Port E7 |
|
|
Doc ID 12468 Rev 3 |
25/279 |
Description |
|
|
|
|
|
|
|
|
|
|
|
ST72361xx-Auto |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 3. |
|
|
Device pin description (continued) |
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin n° |
|
|
|
|
Level |
|
|
Port |
|
|
Main |
|
||||
|
|
|
|
|
|
|
Type |
|
|
|
|
|
|
|
|
|
|
LQFP64 |
|
LQFP44 |
|
LQFP32 |
|
Pin name |
Input |
Output |
float |
Input(1) |
ana |
Output |
function |
Alternate function |
|||
|
|
|
|
wpu |
int |
OD |
PP |
(after |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
reset) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
44 |
|
- |
|
- |
|
PF0 |
I/O |
TT |
|
X |
X |
|
|
X |
X |
|
Port F0 |
45 |
|
30 |
|
- |
|
PF1 / AIN7 |
I/O |
TT |
|
X |
X |
|
X |
X |
X |
Port F1 |
ADC analog input 7 |
46 |
|
31 |
|
- |
|
PF2 / AIN8 |
I/O |
TT |
|
X |
X |
|
X |
X |
X |
Port F2 |
ADC analog input 8 |
47 |
|
32 |
|
23 |
|
PD1 / SCI1_RDI |
I/O |
CT |
|
X |
|
ei3 |
|
X |
X |
Port D1 |
LINSCI1 receive data |
|
|
|
|
|
|
input |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
48 |
|
33 |
|
24 |
|
PD2 / SCI1_TDO |
I/O |
CT |
|
X |
X |
|
|
X |
X |
Port D2 |
LINSCI1 transmit data |
|
|
|
|
|
|
output |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
49 |
|
- |
|
- |
|
PF3 / AIN9 |
I/O |
TT |
|
X |
X |
|
X |
X |
X |
Port F3 |
ADC analog input 9 |
50 |
|
- |
|
- |
|
PF4 |
I/O |
TT |
|
X |
X |
|
|
X |
X |
|
Port F4 |
51 |
|
- |
|
- |
|
TLI |
I |
CT |
|
X |
|
X |
|
|
|
Top level interrupt input pin |
|
52 |
|
34 |
|
- |
|
PF5 |
I/O |
TT |
|
X |
X |
|
|
X |
X |
|
Port F5 |
53 |
|
35 |
|
25 |
|
PD3 (HS) / SCI2_SCK |
I/O |
C |
HS |
X |
X |
|
|
X |
X |
Port D3 |
LINSCI2 serial clock |
|
|
|
|
|
|
|
|
T |
|
|
|
|
|
|
|
|
output |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
54 |
|
36 |
|
26 |
|
PD4 / SCI2_RDI |
I/O |
CT |
|
X |
|
ei3 |
|
X |
X |
Port D4 |
LINSCI2 receive data |
|
|
|
|
|
|
input |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
55 |
|
37 |
|
27 |
|
VSSA |
S |
|
|
|
|
|
|
|
|
Analog ground voltage |
|
56 |
|
38 |
|
28 |
|
VSS_0 |
S |
|
|
|
|
|
|
|
|
Digital ground voltage |
|
57 |
|
39 |
|
29 |
|
VDDA |
I |
|
|
|
|
|
|
|
|
Analog reference voltage for ADC |
|
58 |
|
40 |
|
30 |
|
VDD_0 |
S |
|
|
|
|
|
|
|
|
Digital main supply voltage |
|
59 |
|
41 |
|
31 |
|
PD5 / SCI2_TDO |
I/O |
CT |
|
X |
X |
|
|
X |
X |
Port D5 |
LINSCI2 transmit data |
|
|
|
|
|
|
output |
|||||||||||
60 |
|
42 |
|
32 |
|
RESET |
I/O |
CT |
|
|
|
|
|
|
|
Top priority non maskable |
|
|
|
|
|
|
|
|
|
|
|
interrupt. |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
61 |
|
43 |
|
- |
|
PD6 / AIN10 |
I/O |
CT |
|
X |
ei3 |
X |
X |
X |
Port D6 |
ADC analog input 10 |
|
62 |
|
44 |
|
- |
|
PD7 / AIN11 |
I/O |
CT |
|
X |
|
ei3 |
X |
X |
X |
Port D7 |
ADC analog input 11 |
63 |
|
- |
|
- |
|
PF6 |
I/O |
TT |
|
X |
X |
|
|
X |
X |
|
Port F6 |
64 |
|
- |
|
- |
|
PF7 |
I/O |
TT |
|
X |
X |
|
|
X |
X |
|
Port F7 |
1.In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.
2.OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Chapter 1: Description and Section 20.5: Clock and timing characteristics for more details.
3.Input mode can be used for general purpose I/O, output mode cannot be used.
On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
26/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
Register and memory map |
|
|
As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.
The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of RAM and up to 60 Kbytes of user program memory.
The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.The highest address bytes contain the user reset and interrupt vectors.
Caution: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
Figure 5. |
Memory map |
|
|
|
|
|
|
|
|
|
0000h |
|
0080h |
|
|
|
|
|
|
|
|
HW Registers |
Short Addressing |
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
||
|
(see Table 4) |
|
|
|
|
|
|
|
|
|
007Fh |
00FFh |
RAM (zero page) |
|
|
|
|
|
|
|
|
0080h |
|
|
|
|
|
|
|
|
|
|
|
RAM |
0100h |
256 bytes Stack |
1000h |
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|||
|
(2048/1536 bytes) |
01FFh |
|
|
|
60 Kbytes |
|
|||
087Fh |
|
0200h |
16-bit Addressing |
4000h |
|
|
|
|
|
|
|
|
48 Kbytes |
|
|
||||||
0880h |
|
|
||||||||
Reserved |
|
RAM |
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
||
0FFFh |
067Fh |
|
|
|
|
|
|
|
|
|
|
|
8000h |
|
|
|
|
|
|
||
1000h |
Program Memory |
or 087Fh |
|
|
32 Kbytes |
|
|
|
||
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
FFDFh |
(60K, 48K, 32K, 16K) |
|
|
C000h |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
FFE0h |
Interrupt & Reset Vectors |
|
|
|
|
16 Kbytes |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
FFFFh |
(see Table 16) |
|
|
FFDFh |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
Table 4. |
Hardware register map |
|
|
|
||
Address |
Block |
Register |
Register name |
Reset |
Remarks(1) |
|
label |
status |
|||||
|
|
|
|
|||
|
|
|
|
|
|
|
0000h |
|
PADR |
Port A Data Register |
00h(2) |
R/W(3) |
|
0001h |
Port A |
PADDR |
Port A Data Direction Register |
00h |
R/W(3) |
|
0002h |
|
PAOR |
Port A Option Register |
00h |
R/W(3) |
|
0003h |
|
PBDR |
Port B Data Register |
00h(2) |
R/W(3) |
|
0004h |
Port B |
PBDDR |
Port B Data Direction Register |
00h |
R/W(3) |
|
0005h |
|
PBOR |
Port B Option Register |
00h |
R/W(3) |
|
0006h |
|
PCDR |
Port C Data Register |
00h(2) |
R/W(3) |
|
0007h |
Port C |
PCDDR |
Port C Data Direction Register |
00h |
R/W(3) |
|
0008h |
|
PCOR |
Port C Option Register |
00h |
R/W(3) |
|
0009h |
|
PDDR |
Port D Data Register |
00h(2) |
R/W(3) |
|
000Ah |
Port D |
PDDDR |
Port D Data Direction Register |
00h |
R/W(3) |
|
000Bh |
|
PDOR |
Port D Option Register |
00h |
R/W(3) |
|
000Ch |
|
PEDR |
Port E Data Register |
00h(2) |
R/W(3) |
|
000Dh |
Port E |
PEDDR |
Port E Data Direction Register |
00h |
R/W(3) |
|
000Eh |
|
PEOR |
Port E Option Register |
00h |
R/W(3) |
Doc ID 12468 Rev 3 |
27/279 |
Register and memory map |
|
ST72361xx-Auto |
||||
|
|
|
|
|
|
|
Table 4. |
Hardware register map (continued) |
|
|
|||
|
|
|
|
|
|
|
Address |
Block |
Register |
Register name |
Reset |
Remarks(1) |
|
label |
status |
|||||
|
|
|
|
|||
|
|
|
|
|
|
|
000Fh |
|
PFDR |
Port F Data Register |
00h(2) |
R/W(3) |
|
0010h |
Port F |
PFDDR |
Port F Data Direction Register |
00h |
R/W(3) |
|
0011h |
|
PFOR |
Port F Option Register |
00h |
R/W(3) |
|
0012h |
|
|
|
|
|
|
to |
Reserved Area (15 bytes) |
|
|
|
||
0020h |
|
|
|
|
|
|
|
|
|
|
|
|
|
0021h |
|
SPIDR |
SPI Data I/O Register |
xxh |
R/W |
|
0022h |
SPI |
SPICR |
SPI Control Register |
0xh |
R/W |
|
0023h |
|
SPICSR |
SPI Control/Status Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0024h |
FLASH |
FCSR |
Flash Control/Status Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0025h |
|
ISPR0 |
Interrupt Software Priority Register 0 |
FFh |
R/W |
|
0026h |
|
ISPR1 |
Interrupt Software Priority Register 1 |
FFh |
R/W |
|
0027h |
ITC |
ISPR2 |
Interrupt Software Priority Register 2 |
FFh |
R/W |
|
0028h |
ISPR3 |
Interrupt Software Priority Register 3 |
FFh |
R/W |
||
|
||||||
0029h |
|
EICR0 |
External Interrupt Control Register 0 |
00h |
R/W |
|
002Ah |
|
EICR1 |
External Interrupt Control Register 1 |
00h |
R/W |
|
|
|
|
|
|
|
|
002Bh |
AWU |
AWUCSR |
Auto Wake up f. Halt Control/Status Register |
00h |
R/W |
|
002Ch |
AWUPR |
Auto Wake Up From Halt Prescaler |
FFh |
R/W |
||
|
||||||
|
|
|
|
|
|
|
002Dh |
CKCTRL |
SICSR |
System Integrity Control / Status Register |
0xh |
R/W |
|
002Eh |
MCCSR |
Main Clock Control / Status Register |
00h |
R/W |
||
|
||||||
|
|
|
|
|
|
|
002Fh |
WWDG |
WDGCR |
Watchdog Control Register |
7Fh |
R/W |
|
0030h |
WDGWR |
Watchdog Window Register |
7Fh |
R/W |
||
|
||||||
|
|
|
|
|
|
|
0031h |
|
PWMDCR3 |
Pulse Width Modulator Duty Cycle Register |
00h |
R/W |
|
|
3 |
|||||
0032h |
|
PWMDCR2 |
00h |
R/W |
||
|
PWM Duty Cycle Register 2 |
|||||
0033h |
|
PWMDCR1 |
00h |
R/W |
||
|
PWM Duty Cycle Register 1 |
|||||
0034h |
|
PWMDCR0 |
00h |
R/W |
||
|
PWM Duty Cycle Register 0 |
|||||
0035h |
PWM |
PWMCR |
00h |
R/W |
||
PWM Control register |
||||||
0036h |
ARTCSR |
00h |
R/W |
|||
ART |
Auto-Reload Timer Control/Status Register |
|||||
0037h |
ARTCAR |
00h |
R/W |
|||
|
Auto-Reload Timer Counter Access Register |
|||||
0038h |
|
ARTARR |
00h |
R/W |
||
|
Auto-Reload Timer Auto-Reload Register |
|||||
0039h |
|
ARTICCSR |
00h |
R/W |
||
|
ART Input Capture Control/Status Register |
|||||
003Ah |
|
ARTICR1 |
00h |
Read Only |
||
|
ART Input Capture Register 1 |
|||||
003Bh |
|
ARTICR2 |
00h |
Read Only |
||
|
ART Input Capture register 2 |
|||||
|
|
|
|
|
||
|
|
|
|
|
|
|
003Ch |
|
T8CR2 |
Timer Control Register 2 |
00h |
R/W |
|
003Dh |
|
T8CR1 |
Timer Control Register 1 |
00h |
R/W |
|
003Eh |
|
T8CSR |
Timer Control/Status Register |
00h |
Read Only |
|
003Fh |
8-BIT |
T8IC1R |
Timer Input Capture 1 Register |
xxh |
Read Only |
|
0040h |
T8OC1R |
Timer Output Compare 1 Register |
00h |
R/W |
||
TIMER |
||||||
0041h |
T8CTR |
Timer Counter Register |
FCh |
Read Only |
||
|
||||||
0042h |
|
T8ACTR |
Timer Alternate Counter Register |
FCh |
Read Only |
|
0043h |
|
T8IC2R |
Timer Input Capture 2 Register |
xxh |
Read Only |
|
0044h |
|
T8OC2R |
Timer Output Compare 2 Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0045h |
|
ADCCSR |
Control/Status Register |
00h |
R/W |
|
0046h |
ADC |
ADCDRH |
Data High Register |
00h |
Read Only |
|
0047h |
|
ADCDRL |
Data Low Register |
00h |
Read Only |
|
|
|
|
|
|
|
28/279 |
Doc ID 12468 Rev 3 |
ST72361xx-Auto |
|
Register and memory map |
||||
|
|
|
|
|
|
|
Table 4. |
Hardware register map (continued) |
|
|
|||
|
|
|
|
|
|
|
Address |
Block |
Register |
Register name |
Reset |
Remarks(1) |
|
label |
status |
|||||
|
|
|
|
|||
|
|
|
|
|
|
|
0048h |
|
SCI1ISR |
SCI1 Status Register |
C0h |
Read Only |
|
0049h |
|
SCI1DR |
SCI1 Data Register |
xxh |
R/W |
|
004Ah |
LINSCI1 |
SCI1BRR |
SCI1 Baud Rate Register |
00h |
R/W |
|
004Bh |
SCI1CR1 |
SCI1 Control Register 1 |
xxh |
R/W |
||
(LIN |
||||||
004Ch |
SCI1CR2 |
SCI1 Control Register 2 |
00h |
R/W |
||
Master/Slave) |
||||||
004Dh |
SCI1CR3 |
SCI1Control Register 3 |
00h |
R/W |
||
004Eh |
|
SCI1ERPR |
SCI1 Extended Receive Prescaler Register |
00h |
R/W |
|
004Fh |
|
SCI1ETPR |
SCI1 Extended Transmit Prescaler Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0050h |
|
|
Reserved Area (1 byte) |
|
|
|
|
|
|
|
|
|
|
0051h |
|
T16CR2 |
Timer Control Register 2 |
00h |
R/W |
|
0052h |
|
T16CR1 |
Timer Control Register 1 |
00h |
R/W |
|
0053h |
|
T16CSR |
Timer Control/Status Register |
00h |
R/W |
|
0054h |
|
T16IC1HR |
Timer Input Capture 1 High Register |
xxh |
Read Only |
|
0055h |
|
T16IC1LR |
Timer Input Capture 1 Low Register |
xxh |
Read Only |
|
0056h |
|
T16OC1HR |
Timer Output Compare 1 High Register |
80h |
R/W |
|
0057h |
16-BIT |
T16OC1LR |
Timer Output Compare 1 Low Register |
00h |
R/W |
|
0058h |
T16CHR |
Timer Counter High Register |
FFh |
Read Only |
||
TIMER |
||||||
0059h |
T16CLR |
Timer Counter Low Register |
FCh |
Read Only |
||
|
||||||
005Ah |
|
T16ACHR |
Timer Alternate Counter High Register |
FFh |
Read Only |
|
005Bh |
|
T16ACLR |
Timer Alternate Counter Low Register |
FCh |
Read Only |
|
005Ch |
|
T16IC2HR |
Timer Input Capture 2 High Register |
xxh |
Read Only |
|
005Dh |
|
T16IC2LR |
Timer Input Capture 2 Low Register |
xxh |
Read Only |
|
005Eh |
|
T16OC2HR |
Timer Output Compare 2 High Register |
80h |
R/W |
|
005Fh |
|
T16OC2LR |
Timer Output Compare 2 Low Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0060h |
|
SCI2SR |
SCI2 Status Register |
C0h |
Read Only |
|
0061h |
|
SCI2DR |
SCI2 Data Register |
xxh |
R/W |
|
0062h |
LINSCI2 |
SCI2BRR |
SCI2 Baud Rate Register |
00h |
R/W |
|
0063h |
SCI2CR1 |
SCI2 Control Register 1 |
xxh |
R/W |
||
0064h |
(LIN Master) |
SCI2CR2 |
SCI2 Control Register 2 |
00h |
R/W |
|
0065h |
|
SCI2CR3 |
SCI2 Control Register 3 |
00h |
R/W |
|
0066h |
|
SCI2ERPR |
SCI2 Extended Receive Prescaler Register |
00h |
R/W |
|
0067h |
|
SCI2ETPR |
SCI2 Extended Transmit Prescaler Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0068h |
|
|
|
|
|
|
to |
|
|
Reserved area (24 bytes) |
|
|
|
007Fh |
|
|
|
|
|
|
|
|
|
|
|
|
1.x = undefined, R/W = read/write
2.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
3.The bits associated with unavailable pins must always keep their reset value.
Doc ID 12468 Rev 3 |
29/279 |
Flash program memory |
ST72361xx-Auto |
|
|
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by- Byte basis using an external VPP supply.
The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).
The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.
●3 Flash programming modes:
–Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased.
–ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board.
–IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.
●ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM
●Read-out protection
●Register Access Security System (RASS) to prevent accidental programming or erasing
The Flash memory is organized in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 5). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 6). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).
Table 5. |
Sectors available in Flash devices |
|
|
|
Flash size (bytes) |
|
Available sectors |
|
|
|
|
|
4K |
|
Sector 0 |
|
|
|
|
|
8K |
|
Sectors 0,1 |
|
|
|
|
|
> 8K |
|
Sectors 0,1, 2 |
|
|
|
|
30/279 |
Doc ID 12468 Rev 3 |