ST ST72321BAR9, ST72321BR9, ST72321BJ9, ST72321BAR7, ST72321BR7 User Manual

ST72321BRx, ST72321BARx

ST72321BJx, ST72321BKx

64/44-pin 8-bit MCU with 32 to 60K Flash/ROM, ADC, five timers, SPI, SCI, I2C interface

Features

■Memories

–32K to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash devices

–1K to 2K RAM

–HDFlash endurance: 100 cycles, data retention: 40 years at 85°C

■Clock, Reset And Supply Management

–Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability

–Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock

–PLL for 2x frequency multiplication

–Four Power Saving Modes: Halt, Active-Halt, Wait and Slow

■Interrupt Management

–Nested interrupt controller

–14 interrupt vectors plus TRAP and RESET

–Top Level Interrupt (TLI) pin on 64-pin devices

–15/9 external interrupt lines (on 4 vectors)

■Up to 48 I/O Ports

–48/32/24 multifunctional bidirectional I/O lines

–34/22/17 alternate function lines

–16/12/10 high sink outputs

■5 Timers

–Main Clock Controller with: Real time base, Beep and Clock-out capabilities

–Configurable watchdog timer

–Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes

Table 1. Device Summary

LQFP64	LQFP32
14 x 14	7 x 7

LQFP64	LQFP44
10 x 10	10 x 10

–8-bit PWM Auto-reload timer with: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

■3 Communications Interfaces

–SPI synchronous serial interface

–SCI asynchronous serial interface

–I2C multimaster interface

■1 Analog peripheral (low current coupling)

–10-bit ADC with up to 16 robust input ports

■Instruction Set

–8-bit Data Manipulation

–63 Basic Instructions

–17 main Addressing Modes

–8 x 8 Unsigned Multiply Instruction

■Development Tools

–Full hardware/software development package

–In-Circuit Testing capability

	Features	ST72321BAR9/ ST72321BR9/	ST72321BAR7/ ST72321BR7/	ST72321BAR6/ ST72321BR6/
		ST72321BJ9	ST72321BJ7	ST72321BJ6/ST72321BK6
	Program memory -	FLASH/ROM 60K	FLASH/ROM 48K	FLASH/ROM 32K
	bytes
	RAM (stack) - bytes	2048 (256)	1536 (256)	1024 (256)
	Operating Voltage		3.8V to 5.5V
	Temp. Range		up to -40°C to +125°C
	Package	LQFP64 10x10 (AR),LQFP64 14x14 (R), LQFP44 10x10 (J), LQFP32 7x7 (K)

October 2008

Rev 5

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1

Table of Contents

1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
5.2	MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
5.3	CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1	PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24
6.2	MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
6.3	RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26
	6.3.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26
	6.3.3	External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	6.3.5	Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
6.4	SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
	6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
	6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		29
	6.4.3	Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	6.4.4	Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			32
7.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
7.2	MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
7.3	INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		34
7.4	CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		34
7.5	INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		35
7.6	EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		37
	7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		37
7.7	EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . . .		39
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			41
8.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
8.2	SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
8.3	WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		42
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8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

46

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 55 10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . . 57

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.3.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
10.3.2	Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
10.3.3	Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		69
10.4.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
10.4.2	Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
10.4.3	Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
10.4.4	Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
10.4.5	Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
10.4.6 Summary of Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		81
10.4.7	Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82
10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		88
10.5.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	88
10.5.2	Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	88
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10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.5.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.5.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

10.5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10.5.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

10.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

10.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

10.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

10.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

10.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

10.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

10.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

10.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

10.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		132
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		132
11.1.1	Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	133
11.1.2	Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	133
11.1.3	Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	133
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		133
11.1.5	Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	133
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		134
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		134
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		135

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

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12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 141 12.3.3 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.3.4 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12.4.1	CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	142
12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		143
12.4.3	On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	144
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		145
12.5.1	General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	145
12.5.2	External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	145
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		146
12.5.4	RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	149
12.5.5	PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	150
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		151
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		151
12.6.2	FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	151
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		152

12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 152 12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . 154 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

12.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

12.10.1 8-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 162

12.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	162
12.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	164
12.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	166

12.12.1 Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.12.2 General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.12.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

14 ST72321B DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . 174

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14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	174
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 176
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	178
14.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	178
14.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	178
14.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	178
14.3.4 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	179
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	180

15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

15.1 ALL DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

183

15.1.1 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . 184 15.1.4 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1.5 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1.7 I2C Multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1.8 Pull-up always active on PE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1.9 ADC accuracy 32K Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

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1 DESCRIPTION

The ST72F321B Flash and ST72321B ROM devices are members of the ST7 microcontroller family designed for mid-range applications.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code.

Figure 1. Device Block Diagram

The on-chip peripherals include an A/D converter, a PWM Autoreload timer, 2 general purpose timers, I2C bus, SPI interface and an SCI interface.

For power economy, microcontroller can switch dynamically into WAIT, SLOW, ACTIVE-HALT or HALT mode when the application is in idle or stand-by state.

Typical applications are consumer, home, office and industrial products.

Related Documentation

AN1131: Migrating applications from ST72511/ 311/314 to ST72521/321/324

	8-BIT CORE		PROGRAM
	ALU		MEMORY
			(32K - 60K Bytes)
RESET	CONTROL
VPP
			RAM
TLI
			(1024 - 2048 Bytes)
VSS
	LVD
VDD
EVD	AVD		WATCHDOG
OSC1
	OSC
OSC2
			I2C
		ADDRESS		PA7:0
	MCC/RTC/BEEP
				(8-bits)
			PORT A
	PORT F	AND	PORT B
PF7:0				PB7:0
(8-bits)		DATA	PWM ART
	TIMER A			(8-bits)
	BEEP	BUS	PORT C
	PORT E		TIMER B	PC7:0
PE7:0
				(8-bits)
(8-bits)
	SCI		SPI
	PORT D
PD7:0
(8-bits)	10-BIT ADC
VAREF
VSSA

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2 PIN DESCRIPTION

Figure 2. 64-Pin LQFP 14x14 and 10x10 Package Pinout

PE0/ TDO

/ ICCSEL

SCLI

SDAI

PE3

PE2

PE1RDI/

2

OSC1

OSC2

2

TLI

EVD

RESET

PA7(HS)/

PA6(HS)/ PA5(HS)

PA4(HS)

V

V

V

DD

SS

PP

(HS) PE4

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VSS_1

1

48

(HS) PE5

2

47

VDD_1

(HS) PE6

3

46

PA3 (HS)

(HS) PE7

4

ei0

45

PA2

PWM3 / PB0

5

44

PA1

PWM2 / PB1

6

ei2

43

PA0

PWM1 / PB2

7

42

PC7 /

SS

/ AIN15

PWM0 / PB3

8

41

PC6 / SCK / ICCCLK

ARTCLK / (HS) PB4

9

40

PC5 / MOSI / AIN14

ARTIC1 / PB5

10

ei3

39

PC4 / MISO / ICCDATA

ARTIC2 / PB6

11

38

PC3 (HS) / ICAP1_B

PB7

12

37

PC2 (HS) / ICAP2_B

AIN0 / PD0

13

36

PC1 / OCMP1_B / AIN13

AIN1 / PD1

14

35

PC0 / OCMP2_B / AIN12

AIN2 / PD2

15

ei1

34

VSS_0

AIN3 / PD3

16

33

VDD_0

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

AIN4 / PD4

AIN5 / PD5

AIN6 / PD6

AIN7 / PD7

V

V

V

V

MCO/ AIN8 / PF0

BEEP/ (HS) PF1

(HS) PF2

AOCMP2/ AIN9 / PF3

/AOCMP1AIN10 / PF4

/AICAP2AIN11 / PF5 AICAP1/ (HS) PF6

AEXTCLK/ (HS) PF7

AREF

SSA

DD3

SS3

(HS)

20mA high sink capability

eix

associated external interrupt vector

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Figure 3. 44-Pin LQFP Package Pinout

TDO/PE0

V

OSC1

OSC2

V

RESET

V

SCLI(HS)/PA7

SDAI/(HS)PA6

(HS)PA5

(HS)PA4

2

2

/ ICCSEL

DD

SS

PP

RDI / PE1

44 43 42 41 40 39 38 37 36 35 34

VSS_1

1

33

PB0

2

32

VDD_1

PB1

3

ei2

ei0

31

PA3 (HS)

PB2

4

30

PC7 / SS / AIN15

PB3

5

29

PC6 / SCK / ICCCLK

(HS) PB4

6

ei3

28

PC5 / MOSI / AIN14

AIN0 / PD0

7

27

PC4 / MISO / ICCDATA

AIN1 / PD1

8

26

PC3 (HS) / ICAP1_B

AIN2 / PD2

9

25

PC2 (HS) / ICAP2_B

AIN3 / PD3

10

ei1

24

PC1 / OCMP1_B / AIN13

AIN4 / PD4

11

23

PC0 / OCMP2_B / AIN12

12 13 14 15 16 17 18 19 20 21 22

AIN5 / PD5

AREF

SSA

MCO/ AIN8 / PF0

BEEP/ (HS) PF1

(HS) PF2

OCMP1A / AIN10 / PF4

ICAP1A / (HS) PF6

EXTCLKA / (HS) PF7

DD 0

SS 0

V

V

V

V

(HS) 20mA high sink capability

eix

associated external interrupt vector

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Figure 4. 32-Pin LQFP Package Pinout

	/ AIN1	/ AIN0	(HS)	/ RDI	/ TDO	2
	PD1	PD0	PB4	PB3 PB0 PE1	PE0	V
						DD
VAREF	32 31 30 29 28 27 26 25						OSC1
	1		ei3	ei2		24
VSSA	2					23	OSC2
MCO / AIN8 / PF0	3					22	VSS_2
BEEP / (HS) PF1	ei1					21
	4						RESET
OCMP1_A / AIN10 / PF4	5					20	VPP / ICCSEL
ICAP1_A / (HS) PF6	6					19	PA7 (HS) / SCLI
EXTCLK_A / (HS) PF7	7					18	PA6 (HS) / SDAI
AIN12 / OCMP2_B / PC0	8				ei0 17		PA4 (HS)
	9	10 11 12 13 14 15 16

AIN13 / OCMP1 B / PC1	ICAP2 B / (HS) PC2	ICAP1 B / (HS) PC3	ICCDATA / MISO / PC4	AIN14 / MOSI / PC5	ICCCLK / SCK / PC6		AIN15 / SS / PC7	(HS) PA3

(HS) 20mA high sink capability

eix associated external interrupt vector

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PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 138.

Legend / Abbreviations for Table 2 :

Type:		I = input, O = output, S = supply
Input level:		A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD
		CT= CMOS 0.3VDD/0.7VDD with input trigger
		TT= TTL 0.8V / 2V with Schmitt trigger
Output level:		HS = 20mA high sink (on N-buffer only)
Port and control configuration:
–	Input:	float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
–	Output:	OD = open drain 2), PP = push-pull

Refer to “I/O PORTS” on page 46 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.

Table 2. Device Pin Description

Pin n°

Level

Port

Main

Type

LQFP64

LQFP44

LQFP32

Pin Name

Input

Output

float

Input

ana

Output

function

Alternate function

wpu

int

OD

PP

(after

reset)

1

-

-

PE4 (HS)

I/O

CT

HS

X

X

X

X

Port E4

2

-

-

PE5 (HS)

I/O

CT

HS

X

X

X

X

Port E5

3

-

-

PE6 (HS)

I/O

CT

HS

X

X

X

X

Port E6

4

-

-

PE7 (HS)

I/O

CT

HS

X

X

X

X

Port E7

5

2

28

PB0/PWM3

I/O

CT

X

ei2

X

X

Port B0

PWM Output 3

6

3

-

PB1/PWM2

I/O

CT

X

ei2

X

X

Port B1

PWM Output 2

7

4

-

PB2/PWM1

I/O

CT

X

ei2

X

X

Port B2

PWM Output 1

8

5

29

PB3/PWM0

I/O

CT

X

ei2

X

X

Port B3

PWM Output 0

9

6

30

PB4 (HS)/ARTCLK

I/O

CT

HS

X

ei3

X

X

Port B4

PWM-ART External Clock

10

-

-

PB5 / ARTIC1

I/O

CT

X

ei3

X

X

Port B5

PWM-ART Input Capture 1

11

-

-

PB6 / ARTIC2

I/O

CT

X

ei3

X

X

Port B6

PWM-ART Input Capture 2

12

-

-

PB7

I/O

CT

X

ei3

X

X

Port B7

13

7

31

PD0/AIN0

I/O

CT

X

X

X

X

X

Port D0

ADC Analog Input 0

14

8

32

PD1/AIN1

I/O

CT

X

X

X

X

X

Port D1

ADC Analog Input 1

15

9

-

PD2/AIN2

I/O

CT

X

X

X

X

X

Port D2

ADC Analog Input 2

16

10

-

PD3/AIN3

I/O

CT

X

X

X

X

X

Port D3

ADC Analog Input 3

17

11

-

PD4/AIN4

I/O

CT

X

X

X

X

X

Port D4

ADC Analog Input 4

18

12

-

PD5/AIN5

I/O

CT

X

X

X

X

X

Port D5

ADC Analog Input 5

19

-

-

PD6/AIN6

I/O

CT

X

X

X

X

X

Port D6

ADC Analog Input 6

20

-

-

PD7/AIN7

I/O

CT

X

X

X

X

X

Port D7

ADC Analog Input 7

21

13

1

VAREF

I

Analog Reference Voltage for ADC

22

14

2

VSSA

S

Analog Ground Voltage

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ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx

Pin n°

Level

Port

Main

Type

LQFP64

LQFP44

LQFP32

Pin Name

Input

Output

float

Input

ana

Output

function

Alternate function

wpu

int

OD

PP

(after

reset)

23

-

-

VDD_3

S

Digital Main Supply Voltage

24

-

-

VSS_3

S

Digital Ground Voltage

Main clock

ADC Ana-

25

15

3

PF0/MCO/AIN8

I/O

CT

X

ei1

X

X

X

Port F0

log

out (fOSC/2)

Input 8

26

16

4

PF1 (HS)/BEEP

I/O

CT

HS

X

ei1

X

X

Port F1

Beep signal output

27

17

-

PF2 (HS)

I/O

CT

HS

X

ei1

X

X

Port F2

Timer A Out-

ADC Ana-

28

-

-

PF3/OCMP2_A/AIN9

I/O

CT

X

X

X

X

X

Port F3

put Compare

log

2

Input 9

PF4/OCMP1_A/

Timer A Out-

ADC Ana-

29

18

5

I/O

CT

X

X

X

X

X

Port F4

put Compare

log

AIN10

1

Input 10

X

Timer A Input

ADC Ana-

30

-

-

PF5/ICAP2_A/AIN11

I/O

CT

X

X

X

X

Port F5

Capture 2

log

Input 11

31

19

6

PF6 (HS)/ICAP1_A

I/O

CT

HS

X

X

X

X

Port F6

Timer A Input Capture 1

32

20

7

PF7 (HS)/EXTCLK_A

I/O

CT

HS

X

X

X

X

Port F7

Timer A External Clock

Source

33

21

-

VDD_0

S

Digital Main Supply Voltage

34

22

-

VSS_0

S

Digital Ground Voltage

PC0/OCMP2_B/

Timer B Out-

ADC Ana-

35

23

8

I/O

CT

X

X

X

X

X

Port C0

put Compare

log

AIN12

2

Input 12

PC1/OCMP1_B/

Timer B Out-

ADC Ana-

36

24

9

I/O

CT

X

X

X

X

X

Port C1

put Compare

log

AIN13

1

Input 13

37

25

10

PC2 (HS)/ICAP2_B

I/O

CT

HS

X

X

X

X

Port C2

Timer B Input Capture 2

38

26

11

PC3 (HS)/ICAP1_B

I/O

CT

HS

X

X

X

X

Port C3

Timer B Input Capture 1

39

27

12

PC4/MISO/ICCDATA

I/O

CT

X

SPI Master In

ICC Data

X

X

X

Port C4

/ Slave Out

Input

Data

SPI Master

ADC Ana-

40

28

13

PC5/MOSI/AIN14

I/O

CT

X

X

X

X

X

Port C5

Out / Slave In

log

Data

Input 14

41

29

14

PC6/SCK/ICCCLK

I/O

CT

X

X

X

X

Port C6

SPI Serial

ICC Clock

Clock

Output

SPI Slave Se-

ADC Ana-

42

30

15

PC7/SS/AIN15

I/O

CT

X

X

X

X

X

Port C7

lect (active

log

low)

Input 15

43

-

-

PA0

I/O

CT

X

ei0

X

X

Port A0

44

-

-

PA1

I/O

CT

X

ei0

X

X

Port A1

45

-

-

PA2

I/O

CT

X

ei0

X

X

Port A2

46

31

16

PA3 (HS)

I/O

CT

HS

X

ei0

X

X

Port A3

47

32

-

VDD_1

S

Digital Main Supply Voltage

12/187

ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx

Pin n°

Level

Port

Main

Type

LQFP64

LQFP44

LQFP32

Pin Name

Input

Output

float

Input

ana

Output

function

Alternate function

wpu

int

OD

PP

(after

reset)

48

33

-

VSS_1

S

Digital Ground Voltage

49

34

17

PA4 (HS)

I/O

CT

HS

X

X

X

X

Port A4

50

35

-

PA5 (HS)

I/O

CT

HS

X

X

X

X

Port A5

51

36

18

PA6 (HS)/SDAI

I/O

CT

HS

X

T

Port A6

I2C Data 1)

52

37

19

PA7 (HS)/SCLI

I/O

CT

HS

X

T

Port A7

I2C Clock 1)

Must be tied low. In flash program-

ming mode, this pin acts as the pro-

53

38

20

VPP/ ICCSEL

I

gramming voltage input VPP. See

Section 12.9.2 for more details. High

voltage must not be applied to ROM

devices

54

39

21

I/O

CT

Top priority non maskable interrupt.

RESET

55

-

-

EVD

External voltage detector

56

-

-

TLI

I

CT

X

Top level interrupt input pin

57

40

22

VSS_2

S

Digital Ground Voltage

58

41

23

OSC23)

I/O

Resonator oscillator inverter output

59

42

24

OSC13)

I

External clock input or Resonator os-

cillator inverter input

60

43

25

VDD_2

S

Digital Main Supply Voltage

61

44

26

PE0/TDO

I/O

CT

X

X

X

X

Port E0

SCI Transmit Data Out

62

1

27

PE1/RDI

I/O

CT

X

X

X

X

Port E1

SCI Receive Data In

63

-

-

PE2

I/O

CT

X

X5)

X5)

Port E2

64

-

-

PE3

I/O

CT

X

X

X

X

Port E3

Notes:

1.In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2.In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See See “I/O PORTS” on page 46. and Section 12.8 I/O PORT PIN CHARACTERISTICS for more details.

3.OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1 DESCRIPTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details.

4.On the chip, each I/O port may have up to 8 pads:

– Pads that are not bonded to external pins are forced by hardware in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

5.Pull-up always activated on PE2 see limitation Section 15.1.8.

6.It is mandatory to connect all available VDD and VREF pins to the supply voltage and all VSS and VSSA pins to ground.

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3 REGISTER & MEMORY MAP

As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 2Kbytes of RAM and up to 60Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

The highest address bytes contain the user reset and interrupt vectors.

Figure 5. Memory Map

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.

Related Documentation

AN 985: Executing Code in ST7 RAM

0000h		0080h
	HW Registers		Short Addressing
	(see Table 3)
007Fh			RAM (zero page)
		00FFh
0080h
	RAM	0100h	256 Bytes Stack
	(2048, 1536 or 1024 Bytes)
		01FFh
				1000h
087Fh		0200h	16-bit Addressing		60 KBytes
0880h
	Reserved	or 047Fh	RAM	4000h
0FFFh					48 KBytes
		or 067Fh
1000h				8000h
	Program Memory	or 087Fh			32 KBytes
	(60K, 48K or 32K)
FFDFh
FFE0h	Interrupt & Reset Vectors
FFFFh	(see Table 8)			FFFFh

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Table 3. Hardware Register Map

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	0000h	Port A 2)	PADR	Port A Data Register	00h1)	R/W
	0001h		PADDR	Port A Data Direction Register	00h	R/W
	0002h		PAOR	Port A Option Register	00h	R/W
	0003h	Port B 2)	PBDR	Port B Data Register	00h1)	R/W
	0004h		PBDDR	Port B Data Direction Register	00h	R/W
	0005h		PBOR	Port B Option Register	00h	R/W
	0006h		PCDR	Port C Data Register	00h1)	R/W
	0007h	Port C	PCDDR	Port C Data Direction Register	00h	R/W
	0008h		PCOR	Port C Option Register	00h	R/W
	0009h	Port D 2)	PDDR	Port D Data Register	00h1)	R/W
	000Ah		PDDDR	Port D Data Direction Register	00h	R/W
	000Bh		PDOR	Port D Option Register	00h	R/W
	000Ch		PEDR	Port E Data Register	00h1)	R/W
	000Dh	Port E 2)	PEDDR	Port E Data Direction Register	00h	R/W2)
	000Eh		PEOR	Port E Option Register	00h	R/W2)
	000Fh	Port F 2)	PFDR	Port F Data Register	00h1)	R/W
	0010h		PFDDR	Port F Data Direction Register	00h	R/W
	0011h		PFOR	Port F Option Register	00h	R/W
	0012h
	to			Reserved Area (6 Bytes)
	0017h
	0018h		I2CCR	I2C Control Register	00h	R/W
	0019h		I2CSR1	I2C Status Register 1	00h	Read Only
	001Ah		I2CSR2	I2C Status Register 2	00h	Read Only
	001Bh	I2C	I2CCCR	I2C Clock Control Register	00h	R/W
	001Ch		I2COAR1	I2C Own Address Register 1	00h	R/W
	001Dh		I2COAR2	I2C Own Address Register2	00h	R/W
	001Eh		I2CDR	I2C Data Register	00h	R/W
	001Fh			Reserved Area (2 Bytes)
	0020h
	0021h		SPIDR	SPI Data I/O Register	xxh	R/W
	0022h	SPI	SPICR	SPI Control Register	0xh	R/W
	0023h		SPICSR	SPI Control/Status Register	00h	R/W
	0024h		ISPR0	Interrupt Software Priority Register 0	FFh	R/W
	0025h		ISPR1	Interrupt Software Priority Register 1	FFh	R/W
	0026h	ITC	ISPR2	Interrupt Software Priority Register 2	FFh	R/W
	0027h		ISPR3	Interrupt Software Priority Register 3	FFh	R/W
	0028h		EICR	External Interrupt Control Register	00h	R/W
	0029h	FLASH	FCSR	Flash Control/Status Register	00h	R/W

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ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	002Ah	WATCHDOG	WDGCR	Watchdog Control Register	7Fh	R/W
	002Bh		SICSR	System Integrity Control/Status Register	000x 000x b	R/W
	002Ch	MCC	MCCSR	Main Clock Control / Status Register	00h	R/W
	002Dh		MCCBCR	Main Clock Controller: Beep Control Register	00h	R/W
	002Eh
	to			Reserved Area (3 Bytes)
	0030h
	0031h		TACR2	Timer A Control Register 2	00h	R/W
	0032h		TACR1	Timer A Control Register 1	00h	R/W
	0033h		TACSR	Timer A Control/Status Register	xxxx x0xx b	R/W
	0034h		TAIC1HR	Timer A Input Capture 1 High Register	xxh	Read Only
	0035h		TAIC1LR	Timer A Input Capture 1 Low Register	xxh	Read Only
	0036h		TAOC1HR	Timer A Output Compare 1 High Register	80h	R/W
	0037h		TAOC1LR	Timer A Output Compare 1 Low Register	00h	R/W
	0038h	TIMER A	TACHR	Timer A Counter High Register	FFh	Read Only
	0039h		TACLR	Timer A Counter Low Register	FCh	Read Only
	003Ah		TAACHR	Timer A Alternate Counter High Register	FFh	Read Only
	003Bh		TAACLR	Timer A Alternate Counter Low Register	FCh	Read Only
	003Ch		TAIC2HR	Timer A Input Capture 2 High Register	xxh	Read Only
	003Dh		TAIC2LR	Timer A Input Capture 2 Low Register	xxh	Read Only
	003Eh		TAOC2HR	Timer A Output Compare 2 High Register	80h	R/W
	003Fh		TAOC2LR	Timer A Output Compare 2 Low Register	00h	R/W
	0040h			Reserved Area (1 Byte)
	0041h		TBCR2	Timer B Control Register 2	00h	R/W
	0042h		TBCR1	Timer B Control Register 1	00h	R/W
	0043h		TBCSR	Timer B Control/Status Register	xxxx x0xx b	R/W
	0044h		TBIC1HR	Timer B Input Capture 1 High Register	xxh	Read Only
	0045h		TBIC1LR	Timer B Input Capture 1 Low Register	xxh	Read Only
	0046h		TBOC1HR	Timer B Output Compare 1 High Register	80h	R/W
	0047h		TBOC1LR	Timer B Output Compare 1 Low Register	00h	R/W
	0048h	TIMER B	TBCHR	Timer B Counter High Register	FFh	Read Only
	0049h		TBCLR	Timer B Counter Low Register	FCh	Read Only
	004Ah		TBACHR	Timer B Alternate Counter High Register	FFh	Read Only
	004Bh		TBACLR	Timer B Alternate Counter Low Register	FCh	Read Only
	004Ch		TBIC2HR	Timer B Input Capture 2 High Register	xxh	Read Only
	004Dh		TBIC2LR	Timer B Input Capture 2 Low Register	xxh	Read Only
	004Eh		TBOC2HR	Timer B Output Compare 2 High Register	80h	R/W
	004Fh		TBOC2LR	Timer B Output Compare 2 Low Register	00h	R/W
	0050h		SCISR	SCI Status Register	C0h	Read Only
	0051h		SCIDR	SCI Data Register	xxh	R/W
	0052h		SCIBRR	SCI Baud Rate Register	00h	R/W
	0053h	SCI	SCICR1	SCI Control Register 1	x000 0000b	R/W
	0054h		SCICR2	SCI Control Register 2	00h	R/W
	0055h		SCIERPR	SCI Extended Receive Prescaler Register	00h	R/W
	0056h			Reserved area	---
	0057h		SCIETPR	SCI Extended Transmit Prescaler Register	00h	R/W

16/187

ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	0058h
	to			Reserved Area (24 Bytes)
	006Fh
	0070h		ADCCSR	Control/Status Register	00h	R/W
	0071h	ADC	ADCDRH	Data High Register	00h	Read Only
	0072h		ADCDRL	Data Low Register	00h	Read Only
	0073h		PWMDCR3	PWM AR Timer Duty Cycle Register 3	00h	R/W
	0074h		PWMDCR2	PWM AR Timer Duty Cycle Register 2	00h	R/W
	0075h		PWMDCR1	PWM AR Timer Duty Cycle Register 1	00h	R/W
	0076h		PWMDCR0	PWM AR Timer Duty Cycle Register 0	00h	R/W
	0077h		PWMCR	PWM AR Timer Control Register	00h	R/W
	0078h	PWM ART	ARTCSR	Auto-Reload Timer Control/Status Register	00h	R/W
	0079h		ARTCAR	Auto-Reload Timer Counter Access Register	00h	R/W
	007Ah		ARTARR	Auto-Reload Timer Auto-Reload Register	00h	R/W
	007Bh		ARTICCSR	AR Timer Input Capture Control/Status Reg.	00h	R/W
	007Ch		ARTICR1	AR Timer Input Capture Register 1	00h	Read Only
	007Dh		ARTICR2	AR Timer Input Capture Register 1	00h	Read Only
	007Eh			Reserved Area (2 Bytes)
	007Fh

Legend: x=undefined, R/W=read/write

Notes:

1.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2.The bits associated with unavailable pins must always keep their reset value.

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ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply.

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■Three Flash programming modes:

–Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased.

–ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board.

–IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.

■ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM

■Read-out protection

■Register Access Security System (RASS) to prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can be used for both code and data storage.

Figure 6. Memory Map and Sector Address

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 4). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 6). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 4. Sectors available in Flash devices

Flash Size (bytes)	Available Sectors
4K	Sector 0
8K	Sectors 0,1
> 8K	Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed.

Read-out protection selection depends on the device type:

–In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

–In ROM devices it is enabled by mask option specified in the Option List.

4K

8K

10K

16K

24K

32K

48K

60K

FLASH

MEMORY SIZE

1000h

3FFFh

7FFFh

9FFFh

SECTOR 2

BFFFh

D7FFh

52 Kbytes

DFFFh

2 Kbytes

8 Kbytes

16 Kbytes

24 Kbytes

40 Kbytes

EFFFh

4 Kbytes

SECTOR 1

FFFFh

4 Kbytes

SECTOR 0

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ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 7). These pins are:

–RESET: device reset

–VSS: device power supply ground

–ICCCLK: ICC output serial clock pin

–ICCDATA: ICC input/output serial data pin

–ICCSEL/VPP: programming voltage

–OSC1(or OSCIN): main clock input for external source (optional)

–VDD: application board power supply (optional, see Figure 7, Note 3)

Figure 7. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

APPLICATION BOARD

(See Note 3)

APPLICATION CL2

POWER SUPPLY

		OSC2
V
DD

		OPTIONAL
		(See Note 4)										9				7			5			3			1
													10			8			6			4			2
										10kΩ
					CL1
									SS							ICCSEL/VPP			RESET			ICCCLK			ICCDATA
					ST7
OSC1								V

ICC CONNECTOR

HE10 CONNECTOR TYPE

APPLICATION

RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

Notes:

1.If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2.During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-

agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3.The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4.Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

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FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 7). For more details on the pin locations, refer to the device pinout description.

4.6 IAP (In-Application Programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is

possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.

4.7.1 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 0000 0000 (00h)

7							0
0	0	0	0	0	0	0	0

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

Figure 8. Flash Control/Status Register Address and Reset Value

	Address	Register	7	6	5	4	3	2	1	0
	(Hex.)	Label
	0029h	FCSR
		Reset Value	0	0	0	0	0	0	0	0

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5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■Enable executing 63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes (with indirect addressing mode)

■Two 8-bit index registers

■16-bit stack pointer

■Low power HALT and WAIT modes

■Priority maskable hardware interrupts

■Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The six CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Figure 9. CPU Registers

											7											0
																									ACCUMULATOR
														RESET VALUE = XXh
											7											0
																									X INDEX REGISTER
													RESET VALUE = XXh
											7											0
																									Y INDEX REGISTER
													RESET VALUE = XXh
					PCH			8					7				PCL					0			PROGRAM COUNTER
	15
	RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
											7											0
														1	1	I1	H	I0	N		Z	C			CONDITION CODE REGISTER
				RESET VALUE = 1											1	1 X		1 X			X	X
		15						8														0			STACK POINTER
												7
	RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

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CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write

Reset Value: 111x1xxx

7							0
1	1	I1	H	I0	N	Z	C

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0:No half carry has occurred.

1:A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7th bit.

0:The result of the last operation is positive or null.

1:The result of the last operation is negative (that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

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Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0:The result of the last operation is different from zero.

1:The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0:No overflow or underflow has occurred.

1:An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

Interrupt Software Priority		I1	I0
Level 0	(main)	1	0
Level 1		0	1
Level 2		0	0
Level 3	(= interrupt disable)	1	1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

15							8
0	0	0	0	0	0	0	1
7							0
SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 2).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

Figure 10. Stack Manipulation Example

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 2.

–When an interrupt is received, the SP is decremented and the context is pushed on the stack.

–On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

CALL	Interrupt	PUSH Y	POP Y	IRET	RET
Subroutine	Event				or RSP

@ 0100h

SP

SP

SP

Y

CC

CC

CC

A

A

A

X

X

X

SP

PCH

PCH

PCH

SP

PCL

PCL

PCL

PCH

PCH

PCH

PCH

PCH

SP

@ 01FFh PCL

PCL

PCL

PCL

PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

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6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 12.

For more details, refer to dedicated parametric section.

Main features

■Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator)

■Reset Sequence Manager (RSM)

■Multi-Oscillator Clock Management (MO)

–5 Crystal/Ceramic resonator oscillators

–1 Internal RC oscillator

■System Integrity Management (SI)

–Main supply Low voltage detection (LVD)

–Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply or the EVD pin

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply

the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL

is disabled, then fOSC2 = fOSC/2.

Caution: The PLL is not recommended for applications where timing accuracy is required. See “PLL Characteristics” on page 150.

Figure 11. PLL Block Diagram

fOSC			PLL x 2		0			fOSC2
			/ 2		1

PLL OPTION BIT

Figure 12. Clock, Reset and Supply Block Diagram

OSC2

MULTI-

fOSC

fOSC2

PLL

OSCILLATOR

OSC1

(MO)

(option)

SYSTEM INTEGRITY MANAGEMENT

RESET SEQUENCE

AVD Interrupt Request

RESET

MANAGER

SICSR

(RSM)

AVD AVD AVD LVD

0 0 0

WDG

S IE F RF

RF

VSS

LOW VOLTAGE

DETECTOR

VDD

(LVD)

0

AUXILIARY VOLTAGE

EVD

1

DETECTOR

(AVD)

MAIN CLOCK	fCPU
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)

WATCHDOG

TIMER (WDG)

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6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by three different source types coming from the multioscillator block:

■an external source

■4 crystal or ceramic resonator oscillators

■an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 5. Refer to the electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 14.1 on page 174 for more details on the frequency ranges). In this mode of the multi-oscil- lator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing.

In this mode, the two oscillator pins have to be tied to ground.

Table 5. ST7 Clock Sources

	Hardware Configuration
External Clock	ST7
	OSC1	OSC2
	EXTERNAL
	SOURCE
Resonators	ST7
	OSC1	OSC2
Crystal/Ceramic	CL1	CL2
	LOAD
	CAPACITORS
Internal RC Oscillator	ST7
	OSC1	OSC2

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6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

Figure 13. RESET Sequence Phases

The reset sequence manager includes three RESET sources as shown in Figure 14:

■External RESET source pulse

■Internal LVD RESET (Low Voltage Detection)

■Internal WATCHDOG RESET

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases as shown in Figure 13:

■Active Phase depending on the RESET source

■256 or 4096 CPU clock cycle delay (selected by option byte)

■RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see section 14.1 on page 174).

The RESET vector fetch phase duration is 2 clock cycles.

Figure 14. Reset Block Diagram

RESET

	Active Phase	INTERNAL RESET	FETCH
		256 or 4096 CLOCK CYCLES	VECTOR

Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed.

For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior.

6.3.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See “CONTROL PIN CHARACTERISTICS” on page 158 for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 15). This de-

tection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

VDD

RON

Filter

INTERNAL

RESET

RESET

PULSE

WATCHDOG RESET

GENERATOR

LVD RESET

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RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

If the external RESET pulse is shorter than

tw(RSTL)out (see short ext. Reset in Figure 15), the signal on the RESET pin may be stretched. Other-

wise the delay will not be applied (see long ext. Reset in Figure 15). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least

tw(RSTL)out.

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. (see “OPERATING CONDITIONS” on page 140)

Figure 15. RESET Sequences

A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin.

6.3.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■Power-On RESET

■Voltage Drop RESET

The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT- (falling edge) as shown in Figure 15.

The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 15.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

VDD

VIT+(LVD)

VIT-(LVD)

	LVD	SHORT EXT.
	RESET	RESET
	RUN	RUN
	ACTIVE	ACTIVE
		PHASE

LONG EXT.		WATCHDOG
RESET		RESET
RUN	RUN	RUN
ACTIVE		ACTIVE
PHASE		PHASE

tw(RSTL)out		tw(RSTL)out
th(RSTL)in		th(RSTL)in		tw(RSTL)out

DELAY

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

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6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains the Low Voltage Detector (LVD), Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when VDD is below:

–VIT+ when VDD is rising

–VIT- when VDD is falling

The LVD function is illustrated in Figure 16.

The voltage threshold can be configured by option byte to be low, medium or high.

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes:

–under full software control

–in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Notes:

The LVD allows the device to be used without any external RESET circuitry.

If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed.

The LVD is an optional function which can be selected by option byte.

It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.

Figure 16. Low Voltage Detector vs Reset

VDD

Vhys

VIT+

VIT-

RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and

VIT+(AVD) reference value and the VDD main supply or the external EVD pin voltage level (VEVD). The VIT- reference value for falling voltage is lower

than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only.

Caution: The AVD function is active only if the LVD is enabled through the option byte.

6.4.2.1 Monitoring the VDD Main Supply

This mode is selected by clearing the AVDS bit in the SICSR register.

The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see section 14.1 on page 174).

If the AVD interrupt is enabled, an interrupt is gen-

erated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles).

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 17.

The interrupt on the rising edge is used to inform the application that the VDD warning state is over.

If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.

If trv is greater than 256 or 4096 cycles then:

– If the AVD interrupt is enabled before the

VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE

bit is set, and the second when the threshold is reached.

–If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur.

Figure 17. Using the AVD to Monitor VDD (AVDS bit=0)

VDD		Early Warning Interrupt
		(Power has dropped, MCU
		not yet in reset)
VIT+(AVD)		Vhyst
VIT-(AVD)
VIT+(LVD)
VIT-(LVD)				RISE TIME
AVDF bit	0	1	1	0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
		INTERRUPT PROCESS		INTERRUPT PROCESS
LVD RESET
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ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2.2 Monitoring a Voltage on the EVD pin

This mode is selected by setting the AVDS bit in the SICSR register.

The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set. This interrupt is generated on the rising and falling edges

of the comparator output. This means it is generated when either one of these two events occur:

–VEVD rises up to VIT+(EVD)

–VEVD falls down to VIT-(EVD)

The EVD function is illustrated in Figure 18.

For more details, refer to the Electrical Characteristics section.

Figure 18. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)

VEVD

Vhyst

VIT+(EVD)

VIT-(EVD)

AVDF

0

1

0

AVD INTERRUPT

REQUEST

IF AVDIE = 1

INTERRUPT PROCESS

INTERRUPT PROCESS

6.4.3 Low Power Modes

	Mode	Description
	WAIT	No effect on SI. AVD interrupts cause the
		device to exit from Wait mode.
	HALT	The SICSR register is frozen.

6.4.3.1 Interrupts

The AVD interrupt event generate an interrupt if the corresponding Enable Control Bit (AVDIE) is

set and the interrupt mask in the CC register is reset (RIM instruction).

Interrupt Event	Event	Enable	Exit	Exit
	Flag	Control	from	from
		Bit	Wait	Halt
AVD event	AVDF	AVDIE	Yes	No

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