BECKHOFF PHY User Manual

0 (0)

Version 2.3

Date: 2014-02-03

Application Note

Slave Controller

Section I – Technology

(Online at http://www.beckhoff.com)

Section II – Register Description

(Online at http://www.beckhoff.com)

Section III – Hardware Description

(Online at http://www.beckhoff.com)

Application Note – PHY Selection Guide

Requirements to Ethernet PHYs used for EtherCAT

Ethernet PHY Examples

EtherCAT over optical links (FX)

DOCUMENT ORGANIZATION

Slave Controller – Application Note PHY Selection Guide II

DOCUMENT ORGANIZATION

The Beckhoff EtherCAT Slave Controller (ESC) documentation covers the following Beckhoff ESCs:

 ET1200

 ET1100

 EtherCAT IP Core for Altera

FPGAs

 EtherCAT IP Core for Xilinx

FPGAs

 ESC20

The documentation is organized in three sections. Section I and section II are common for all Beckhoff ESCs,

Section III is specific for each ESC variant.

The latest documentation is available at the Beckhoff homepage (http://www.beckhoff.com).

Section I – Technology (All ESCs)

Section I deals with the basic EtherCAT technology. Starting with the EtherCAT protocol itself, the frame

processing inside EtherCAT slaves is described. The features and interfaces of the physical layer with its two

alternatives Ethernet and EBUS are explained afterwards. Finally, the details of the functional units of an ESC

like FMMU, SyncManager, Distributed Clocks, Slave Information Interface, Interrupts, Watchdogs, and so on,

are described.

Since Section I is common for all Beckhoff ESCs, it might describe features which are not available in a specific

ESC. Refer to the feature details overview in Section III of a specific ESC to find out which features are

available.

Section II – Register Description (All ESCs)

Section II contains detailed information about all ESC registers. This section is also common for all Beckhoff

ESCs, thus registers, register bits, or features are described which might not be available in a specific ESC.

Refer to the register overview and to the feature details overview in Section III of a specific ESC to find out

which registers and features are available.

Section III – Hardware Description (Specific ESC)

Section III is ESC specific and contains detailed information about the ESC features, implemented registers,

configuration, interfaces, pinout, usage, electrical and mechanical specification, and so on. Especially the

Process Data Interfaces (PDI) supported by the ESC are part of this section.

Additional Documentation

Application notes and utilities like pinout configuration tools for ET1100/ET1200 can also be found at the

Beckhoff homepage.

DOCUMENT HISTORY

Version

Comment

1.1pre

First preliminary release

1.2

 Ethernet PHY requirements revised (e.g., link loss reaction time)

 Added Micrel KSZ8001L

 Added National Semiconductor DP83848, DP83849, and DP83640

 Editorial changes

1.3

 Added restriction to enhanced link configuration: RX_ER has to be asserted

outside of frames (IEEE802 optional feature)

 Removed National Semiconductor DP83848 and DP83849 temporarily for

further examination

1.4

 Updated/clarified PHY requirements, PHY link loss reaction time is mandatory

 Added National Semiconductor DP83848, DP83849 with comments

 Added PHYs which require Enhanced Link detection to be activated

 Editorial changes

1.5

 PHY startup should not rely on MDC clocking

 Added Micrel KSZ8041NL/TL Rev. A4 to list of example Ethernet PHYs for

EtherCAT with Enhanced Link Detection requirement

 ESD tolerance and baseline wander compensation recommendations added

 Editorial changes

1.6

 Completely revised and enhanced compatibility table

 Editorial changes

1.7

 Added restrictions for ET1100/ET1200 and PHYs which require Enhanced Link

Detection: PHY address offset must be 0

 PHY address offset for Teridian PHYs and Micrel KSZ8041 corrected

1.8

 Added Micrel KSZ8051 PHYs

 Link loss reaction time of Broadcom BCM5241is higher than data sheet reports

 Clarified suitability of some Micrel/National Semiconductor PHYs for ET1100,

ET1200

 Changed footnote: Microchip PIC10 is expected to be not suitable for

management address conversion during an access (PIC10 remains suitable for

adding an extra MCLK cycle)

2.0

 Micrel KSZ8051: update to rev. A2

 Micrel KSZ8721: LED1 speed behavior comments added

 Texas Instruments (formerly National Semiconductor) DP83848/DP83849

comment on clock supply added

 Renesas µPD60610, µPD60611, µPD60620, µPD60621 added

 SMSC LAN8700 added

 STMicroelectronics STE802RT1A/B PHYs added

 Texas Instruments DP83620/ DP83630 added

 Added chapter about EtherCAT over optical links

 Added chapter about Gigabit Ethernet PHYs

 Enhanced recommendations for Ethernet PHYs

 Added recommendations to FX transceivers used for EtherCAT

2.1

 Added Texas Instruments TLK105, TLK106, and TLK110

 Added Micrel KSZ8081MNX,KSZ8081 MLX

 Removed Micrel KSZ8721: not recommended for new designs by Micrel (Micrel

recommends KSZ8051 or KSZ8081 instead)

 Renesas µPD60610, µPD60611, µPD60620, µPD60621 updated

 Added IC Plus Corp. IP101G

 IEEE802.3az Energy Efficient Ethernet must not be used

 Added required PHY signals table

 Updated to ET1100-0003/ET1200 -0003

Trademarks

Beckhoff

, TwinCAT

, EtherCAT

, Safety over EtherCAT

, TwinSAFE

and XFC

are registered trademarks of and licensed by

Beckhoff Automation GmbH. Other designations used in this publication may be trademarks whose use by third parties for their

own purposes could violate the rights of the owners.

Patent Pending

The EtherCAT Technology is covered, including but not limited to the following German patent applications and patents:

DE10304637, DE102004044764, DE102005009224, DE102007017835 with corresponding applications or registrations in

various other countries.

Disclaimer

The documentation has been prepared with care. The products described are, however, constantly under development. For that

reason the documentation is not in every case checked for consistency with performance data, standards or other

characteristics. In the event that it contains technical or editorial errors, we retain the right to make alterations at any time and

without warning. No claims for the modification of products that have already been supplied may be made on the basis of the

data, diagrams and descriptions in this documentation.

The reproduction, distribution and utilization of this document as well as the communication of its contents to others without

the grant of a patent, utility model or design.

CONTENTS

Slave Controller – Application Note PHY Selection Guide III

Version

Comment

2.2

 Update to EtherCAT IP Core V3.0.2/V3.00c with FX support

 RX_ER is required for EtherCAT

 Editorial changes

2.3

 Renesas µPD60610/µPD60611: Auto-TX-Shift required (data sheet was

updated)

 Renesas µPD60610/µPD60611/ µPD60620/µPD60621: MI link detection and

configuration can only be enabled with certain IP Core versions

 Texas Instruments TLK105/TLK106/TLK110: MI link detection and configuration

must not be enabled

 Micrel PHYs: added notes for an internal pull-up resistor at MCLK pin

 Added note for PHYs with Enhanced link detection recommendation

 Editorial changes

1 Overview 1

2 Ethernet PHY Requirements 2

3 PHY Connection 3

3.1 Required Ethernet PHY signals 3

4 Example Ethernet PHYs 4

4.1 Enhanced Link Detection 4

4.2 Auto TX Shift 4

4.3 Example Ethernet PHYs 5

4.4 Examples of Ethernet PHYs assumed to be incompatible with EtherCAT requirements

5 EtherCAT over Optical Links (FX) 7

5.1 ESCs with native FX support 7

5.2 ESCs without native FX support 7

5.2.1 Standard Link Detection 7

5.2.1.1 Issue: Temporary Enhanced Link Detection while EEPROM is loading

5.2.1.2 Minimum solutions with Standard Link Detection 8

5.2.2 Enhanced FX Link Detection 8

5.2.2.1 Proposed solutions with Enhanced Link Detection 9

6 Gigabit Ethernet PHYs 9

7 Appendix 9

7.1 Support and Service 9

7.1.1 Beckhoff’s branch offices and representatives 9

7.2 Beckhoff Headquarters 9

Overview

Slave Controller – Application Note PHY Selection Guide 1

1 Overview

An EtherCAT Slave Controller (ESC) takes care of the EtherCAT communication as an interface between the

EtherCAT fieldbus (Ethernet) and the slave application. EtherCAT uses standard Fast Ethernet. Transmission

speed for EtherCAT is fixed to 100 Mbit/s with Full Duplex communication. EtherCAT Slave Controllers process

Ethernet frames on the fly.

This application note provides an overview of the requirements to Ethernet PHYs used for EtherCAT devices.

An example list of Ethernet PHYs currently expected to be suitable for EtherCAT is also provided.

This application note applies to the following Beckhoff EtherCAT Slave Controllers:

 ET1200-0003

 ET1100-0003

 EtherCAT IP Core for Altera

/Xilinx

FPGAs V3.0.2/V3.00c and later

 ESC10/20

Refer to the ESC data sheets for further information. The ESC data sheets are available from the Beckhoff

homepage (http://www.beckhoff.com).

DVI

IPC

DVI

IPC

DVI

IPC

EtherCAT Segment (Slaves)Master

vom Masterfrom Master

to Master

Figure 1: EtherCAT Segment

+ 8 hidden pages