Samsung KM416V254DTL-7, KM416V254DTL-6, KM416V254DT-6, KM416V254DT-5, KM416V254DJL-5 Datasheet

KM416C254D, KM416V254D

CMOS DRAM

256K x 16Bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 262,144 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Power supply voltage(+5.0V or +3.3V), Access time (-5,-6 or -7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RASonly refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.

FEATURES

•Part Identification

-KM416C254D/DL (5V, 512 Ref.)

-KM416V254D/DL (3.3V, 512 Ref.)

•Active Power Dissipation

		Unit : mW
Speed	3.3V(512 Ref.)	5V(512 Ref.)
-5	-	605
-6	255	495
-7	235	440

• Refresh Cycles

•Extended Data Out Mode operation

•2 CAS Byte/Wrod Read/Write operation

•CAS-before-RAS refresh capability

•RAS-only and Hidden refresh capability

•Self-refresh capability (L-ver only)

•TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

•Early Write or output enable controlled write

•JEDEC Standard pinout

•Available in 40-pin SOJ 400mil and 44(40)-pin packages

•Triple +5V±10% power supply (5V product)

•Triple +3.3V±0.3V power supply (3.3V product)

FUNCTIONAL BLOCK DIAGRAM

Part

VCC

Refresh

Refresh period

NO.

cycle

Normal

L-ver

C254D

5V

512

8ms

128ms

V254D

3.3V

• Performance Range

Speed

tRAC

tCAC

tRC

tHPC

Remark

-5

50ns

15ns

84ns

20ns

5V only

-6

60ns

15ns

104ns

25ns

5V/3.3V

-7

70ns

20ns

124ns

30ns

5V/3.3V

RAS

Control

Vcc

UCAS

Vss

LCAS

Clocks

VBB Generator

W

			Lower
	Row Decoder		Data in	DQ0
Refresh Timer			Buffer
				to
		I/O	Lower	DQ7
Refresh Control			Data out
		&
	Memory Array		Buffer
		Amps
				OE
Refresh Counter	262,144 x16		Upper
	Cells	Sense	Data in
Row Address Buffer			Buffer	DQ8
A0~A8			Upper	to
			Data out	DQ15
Col. Address Buffer	Column Decoder
			Buffer

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

KM416C254D, KM416V254D

CMOS DRAM

PIN CONFIGURATION (Top Views)

					•KM416C/V254DJ																			•KM416C/V254DT
		VCC				1	40							VSS					VCC						1	40					VSS
		DQ0				2	39							DQ15					DQ0						2	39					DQ15
		DQ1				3	38							DQ14					DQ1						3	38					DQ14
		DQ2				4	37							DQ13					DQ2						4	37					DQ13
		DQ3				5	36							DQ12					DQ3						5	36					DQ12
		VCC				6	35							VSS					VCC						6	35					VSS
		DQ4				7	34							DQ11					DQ4						7	34					DQ11
		DQ5				8	33							DQ10					DQ5						8	33					DQ10
		DQ6				9	32							DQ9					DQ6						9	32					DQ9
		DQ7				10	31							DQ8					DQ7						10	31					DQ8
		N.C				11	30							N.C					N.C						11	30					N.C
		N.C				12	29							LCAS					N.C						12	29					LCAS
			W			13	28							UCAS						W					13	28					UCAS
		RAS				14	27							OE					RAS						14	27					OE
		N.C				15	26							A8					N.C						15	26					A8
		A0				16	25							A7					A0						16	25					A7
		A1				17	24							A6					A1						17	24					A6
		A2				18	23							A5					A2						18	23					A5
		A3				19	22							A4					A3						19	22					A4
		VCC				20	21							VSS					VCC						20	21					VSS
							(SOJ)																		(TSOP-II)
								Pin Name										Pin Function
								A0 - A8										Address Inputs
								DQ0 - 15										Data In/Out
										VSS								Ground
																		Row Address Strobe
										RAS
																		Upper Column Address Strobe
									UCAS
																		Lower Column Address Strobe
									LCAS
																		Read/Write Input
												W
																		Data Output Enable
											OE
										VCC								Power(+5V)
																		Power(+3.3V)
										N.C								No Connection

KM416C254D, KM416V254D								CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter		Symbol				Rating				Units
				3.3V				5V
Voltage on any pin relative to VSS		VIN,VOUT	-0.5	to	+4.6		-1.0	to	+7.0	V
Voltage on VCC supply relative to VSS		VCC	-0.5	to	+4.6		-1.0	to	+7.0	V
Storage Temperature		Tstg	-55 to +150				-55 to +150			°C
Power Dissipation		PD		1				1		W
Short Circuit Output Current		IOS		50				50		mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

	Parameter	Symbol		3.3V				5V		Units
			Min	Typ		Max	Min	Typ	Max
Supply Voltage		VCC	3.0	3.3		3.6	4.5	5.0	5.5	V
Ground		VSS	0	0		0	0	0	0	V
Input High Voltage		VIH	2.0	-		VCC+0.3*1	2.4	-	VCC+1.0*1	V
Input Low Voltage		VIL	-0.3*2	-		0.8	-1.0*2	-	0.8	V
*1	: VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2	: -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

	Max		Parameter	Symbol	Min	Max	Units
		Input Leakage Current (Any input 0≤VIN≤VIN+0.3V,		II(L)	-5	5	uA
		all other input pins not under test=0 Volt)
	3.3V	Output Leakage Current		IO(L)	-5	5	uA
		(Data out is disabled, 0V≤VOUT≤VCC)
		Output High Voltage Level(IOH=-2mA)		VOH	2.4	-	V
		Output Low Voltage Level(IOL=2mA)		VOL	-	0.4	V
		Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,		II(L)	-5	5	uA
		all other input pins not under test=0 Volt)
	5V	Output Leakage Current		IO(L)	-5	5	uA
		(Data out is disabled, 0V≤VOUT≤VCC)
		Output High Voltage Level(IOH=-5mA)		VOH	2.4	-	V
		Output Low Voltage Level(IOL=4.2mA)		VOL	-	0.4	V

KM416C254D, KM416V254D							CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol	Power	Speed			Max			Units
				KM416V254D		KM416C254D
		-5		-		110		mA
ICC1	Don′t care	-6		70		90		mA
		-7		65		80		mA
ICC2	Don′t care	Don′t care		1		2		mA
		-5		-		110		mA
ICC3	Don′t care	-6		70		90		mA
		-7		65		80		mA
		-5		-		90		mA
ICC4	Don′t care	-6		60		80		mA
		-7		55		70		mA
ICC5	Normal	Don′t care		0.5		1		mA
	L			100		150		uA
		-5		-		110		mA
ICC6	Don′t care	-6		70		90		mA
		-7		65		80		mA
ICC7	L	Don′t care		200		300		uA
ICCS	L	Don′t care		100		200		uA

ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)

ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)

ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)

ICC4* : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.)

ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min.)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V,

DQ=Don′t care, TRC=125us, TRAS=TRASmin~300ns

ICCS : Self Refresh Current

RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A8=VCC-0.2V or 0.2V,

DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3, ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Hyper page mode cycle time, tHPC.

KM416C254D, KM416V254D																																							CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
								Parameter																					Symbol					Min					Max			Units
	Input capacitance [A0 ~ A8]																												CIN1					-				5				pF
	Input capacitance																												CIN2					-				7				pF
							[RAS,						UCAS,		LCAS,				W,				OE]
	Output capacitance [DQ0 - DQ15]																												CDQ					-				7				pF
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
				Parameter																							Symbol		-5*1					-6				-7		Units		Notes
																													Min		Max			Min		Max	Min		Max
	Random read or write cycle time																										tRC		84					104			124			ns
	Read-modify-write cycle time																										tRWC		116					138			163			ns
	Access time from																										tRAC				50					60			70	ns		3,4,10
					RAS
	Access time from																										tCAC				15					15			20	ns		3,4,5
					CAS
	Access time from column address																										tAA				25					30			35	ns		3,10
		to output in Low-Z																									tCLZ		3					3			3			ns		3
	CAS
	Output buffer turn-off delay from																										tCEZ		3		13			3		13	3		18	ns		6,12
																CAS
	Transition time (rise and fall)																										tT		2		50			2		50	2		50	ns		2
		precharge time																									tRP		30					40			50			ns
	RAS
		pulse width																									tRAS		50		10K			60		10K	70		10K	ns
	RAS
		hold time																									tRSH		15					15			20			ns
	RAS
		hold time																									tCSH		40					50			60			ns
	CAS
		pulse width																									tCAS		8		10K			10		10K	15		10K	ns
	CAS
		to		delay time																							tRCD		20		35			20		45	20		50	ns		4
	RAS		CAS
		to column address delay time																									tRAD		15		25			15		30	15		35	ns		10
	RAS
		to		precharge time																							tCRP		5					5			5			ns
	CAS		RAS
	Row address set-up time																										tASR		0					0			0			ns
	Row address hold time																										tRAH		10					10			10			ns
	Column address set-up time																										tASC		0					0			0			ns		13
	Column address hold time																										tCAH		8					10			15			ns		13
	Column address to											lead time															tRAL		25					30			35			ns
								RAS
	Read command set-up time																										tRCS		0					0			0			ns
	Read command hold time referenced to																										tRCH		0					0			0			ns		8
																					CAS
	Read command hold time referenced to																										tRRH		0					0			0			ns		8
																				RAS
	Write command set-up time																										tWCS		0					0			0			ns		7
	Write command hold time																										tWCH		10					10			10			ns
	Write command pulse width																										tWP		10					10			10			ns
	Write command to									lead time																	tRWL		13					15			15			ns
						RAS
	Write command to									lead time																	tCWL		8					10			15			ns		16
						CAS

Note) *1 : 5V only

	KM416C254D, KM416V254D																																																						CMOS DRAM
	AC CHARACTERISTICS (Continued)
														Parameter																																Symbol		-5*1			-6			-7		Units	Notes
																																															Min		Max	Min		Max	Min		Max
		Data set-up time																																												tDS	0			0			0			ns	9,19
		Data hold time																																												tDH	8			10			15			ns	9,19
		Refresh period (Normal)																																												tREF			8			8			8	ms
		Refresh period (L-ver)																																												tREF			128			128			128	ms
						to			delay time																																					tCWD	32			32			42			ns	7,15
		CAS						W
						to			delay time																																					tRWD	67			77			92			ns	7
		RAS						W
		Column address to																								delay time																				tAWD	42			47			57			ns	7
																			W
						precharge to																	delay time																							tCPWD	45			52			62			ns	7
			CAS															W
						set-up time																							-before-													refresh)				tCSR	5			5			5			ns	17
		CAS													(CAS																							RAS
						hold time																	-before-																	refresh)						tCHR	10			10			10			ns	18
		CAS										(CAS																									RAS
						to					precharge time																																			tRPC	5			5			5			ns
		RAS						CAS
																														-B-						counter test cycle)										tCPT	20			20			25			ns
		CAS				precharge time (C																											R
		Access time from																											precharge																	tCPA			28			35			40	ns	3
																CAS
		Hyper Page mode cycle time																																												tHPC	20			25			30			ns	11
		Hyper Page read-modify-write cycle time																																												tHPRWC	57			66			81			ns	11
						precharge time (Hyper Page cycle)																																								tCP	8			10			10			ns	14
		CAS
						pulse width (Hyper Page cycle)																																								tRASP	50		100K	60		100K	70		100K	ns
		RAS
						hold time from																										precharge														tRHCP	30			35			40			ns
		RAS																		CAS
					access time																																									tOEA			15			15			20	ns	3
		OE
					to data delay																																									tOED	13			13			18			ns
		OE
		Output buffer turn off delay time from																																												tOEZ	3		13	3		13	3		18	ns	6
																																												OE
					command hold time																																									tOEH	15			15			20			ns
			OE
		Output data hold time																																												tDOH	5			5			5			ns
		Output buffer turn off delay from																																												tREZ	3		15	3		15	3		20	ns	6,12
																																							RAS
		Output buffer turn off delay from																																												tWEZ	3		13	3		13	3		18	ns	6
																																							W
				to data delay																																										tWED	13			13			18			ns
			W
					to					hold time																																				tOCH	5			5			5			ns
		OE					CAS
						hold time to																																								tCHO	5			5			5			ns
		CAS												OE
					precharge time																																									tOEP	5			5			5			ns
		OE
				pulse width (Hyper Page Cycle)																																										tWPE	5			5			5			ns
		W
																			-B-													self refresh)														tRASS	100			100			100			us	20,21,22
		RAS				pulse width (C																						R
																															-B-					self refresh)										tRPS	90			110			130			ns	20,21,22
		RAS				precharge time (C																												R
																																														tCHS	-50			-50			-50			ns	20,21,22
		CAS				hold time (C							-B-R self refresh)
		Note) *1 : 5V only

KM416C254D, KM416V254D

CMOS DRAM

NOTES

1.An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved.

2.VIH(min) and VIL(max) are reference levels for measuring timing of input signals.

Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.

3.Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 50pF.

4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.

5.Assumes that tRCD³tRCD(max).

6.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

7.tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS³tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD³tCWD(min), tRWD³tRWD(min), tAWD³tAWD(min) and tCPWD³tCPWD(min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate.

8.Either tRCH or tRRH must be satisfied for a read cycle.

9.These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles.

10.Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

11.tASC³6ns, Assume tT = 2.0ns

12.If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS going.

KM416C/V254D/DL Truth Table

RAS

LCAS

UCAS

W

OE

DQ0 - DQ7

DQ8-DQ15

STATE

H

H

H

H

H

Hi-Z

Hi-Z

Standby

L

H

H

H

H

Hi-Z

Hi-Z

Refresh

L

L

H

H

L

DQ-OUT

Hi-Z

Byte Read

L

H

L

H

L

Hi-Z

DQ-OUT

Byte Read

L

L

L

H

L

DQ-OUT

DQ-OUT

Word Read

L

L

H

L

H

DQ-IN

-

Byte Write

L

H

L

L

H

-

DQ-IN

Byte Write

L

L

L

L

H

DQ-IN

DQ-IN

Word Write

L

L

L

H

H

Hi-Z

Hi-Z

-

KM416C254D, KM416V254D

CMOS DRAM

13.tASC, tCAH are referenced to the earlier CAS rising edge.

14.tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.

15.tCWD is referenced to the later CAS falling edge at word red-modify-write cycle.

16.tCWL is specified from W falling edge to the earlier CAS rising edge.

17.tCSR is referenced to earlier CAS falling low before RAS transition low.

18.tCHR is referenced to the later CAS rising high after RAS transition low.

RAS

LCAS

UCAS

tCSR

tCHR

19. tDS, tDH are specified for the earlier CAS falling low.

LCAS

UCAS

tDS tDH

DQ0 ~ DQ15	Din

W

20.f tRASS³100us, then RAS precharge time must use tRPS instead of tRP.

21.For RAS-only refresh and burst CAS-before-RAS refresh mode, 512(512K) cycle of burst refresh must be executed within 8ms before and after self refresh, in order to meet refresh specification.

22.For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.

KM416C254D, KM416V254D

CMOS DRAM

WORD READ CYCLE

				tRC	tRP
VIH -				tRAS
RAS VIL -
	tCRP			tCSH	tCRP
			tRCD	tRSH
VIH -				tCAS
UCAS
VIL -
	tCRP			tCSH	tCRP
			tRCD	tRSH
VIH -				tCAS
LCAS
VIL -			tRAD
				tRAL
	tASR	tRAH	tASC
				tCAH
VIH -
	ROW			COLUMN
A
	ADDRESS			ADDRESS
VIL -
			tRCS		tRCH
					tRRH
VIH -
W VIL -
				tAA
VIH -				tOLZ
				tOEA
OE
VIL -				tCAC	tCEZ
DQ0 ~ DQ7			tRAC	tCLZ	tOEZ
VOH -		OPEN			DATA-OUT
VOL -
				tCAC	tCEZ
DQ8 ~ DQ15			tRAC	tCLZ	tOEZ
VOH -
		OPEN			DATA-OUT
VOL -

Don′t care

Undefined

KM416C254D, KM416V254D

CMOS DRAM

LOWER BYTE READ CYCLE

NOTE : DIN = OPEN

				tRC	tRP
VIH -				tRAS
RAS
VIL -
	tCRP				tRPC
VIH -
UCAS VIL -
	tCRP			tCSH
			tRCD	tRSH
VIH -				tCAS
LCAS
VIL -			tRAD
	tASR	tRAH	tASC	tRAL
				tCAH
VIH -
	ROW			COLUMN
A
	ADDRESS			ADDRESS
VIL -
			tRCS		tRCH
					tRRH
VIH -
W VIL -					tCEZ
				tAA
					tOEZ
VIH -				tOEA
OE
VIL -				tCAC
DQ0 ~ DQ7			tRAC	tCLZ
VOH -		OPEN			DATA-OUT
VOL -

tOLZ

DQ8 ~ DQ15

VOH -

OPEN

VOL -

Don′t care

Undefined

KM416C254D, KM416V254D

CMOS DRAM

UPPER BYTE READ CYCLE

NOTE : DIN = OPEN

				tRC
VIH -				tRAS	tRP
RAS VIL -				tCSH
	tCRP				tCRP
			tRCD	tRSH
VIH -				tCAS
UCAS
VIL -
	tCRP				tRPC
VIH -
LCAS			tRAD
VIL -
	tASR	tRAH	tASC	tRAL
				tCAH
VIH -
	ROW			COLUMN
A
	ADDRESS			ADDRESS
VIL -
			tRCS		tRCH
					tRRH
VIH -
W
VIL -					tCEZ
				tAA
					tOEZ
VIH -				tOEA
OE
VIL -
DQ0 ~ DQ7				tOLZ
VOH -				OPEN
VOL -
				tCAC
DQ8 ~ DQ15			tRAC	tCLZ
VOH -		OPEN			DATA-OUT
VOL -

Don′t care

Undefined