Samsung KM44S3203BT-G-FA, KM44S3203BT-G-F8, KM44S3203BT-G-F10, KM44S3203BT-G-FL, KM44S3203BT-G-FH Datasheet

KM44S32030B

CMOS SDRAM

128Mbit SDRAM

8M x 4Bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 0.1

June 1999

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.1 Jun. 1999

KM44S32030B

CMOS SDRAM

Revision History

Revision 0.0 (May 15, 1999)

• Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.

• Skip ICC4 value of CL=2 in DC characteristics in datasheet.

• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.

• Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.

• Symbol Change Notice

		Before						After
	IIL	Input leakage current (inputs)			ILI		Input leakage current
	IIL	Input leakage current (I/O pins)
	IOL	Output open @ DC characteristic table			Io		Output open @ DC characteristic table
• Test Condition in DC CHARACTERISTIC Change Notice
	Symbol			Before					After
	ICC2P , ICC3P	CKE £ VIL(max), tCC = 15ns				CKE £ VIL(max), tCC = 10ns
	ICC2N , ICC3N	CKE ³ VIH(min),	CS	³ VIH(min), tCC = 15ns		CKE ³ VIH(min),		CS	³ VIH(min), tCC = 10ns
		Input signals are changed one time during 30ns				Input signals are changed one time during 20ns
	ICC4	2 Banks activated				4 Banks activated

Revision 0.1 (Jun 28, 1999)

• Added Notes @OPERATING AC PARAMETER

Notes : 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .

SAMSUNG recommands tRDL=2CLK and tDAL=2CLK + 20ns.

• Added -10 bining product.

Rev. 0.1 Jun. 1999

KM44S32030B

CMOS SDRAM

8M x 4Bit x 4 Banks Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

•

JEDEC standard 3.3V power supply

The KM44S32030B is 134,217,728 bits synchronous high

•

LVTTL compatible with multiplexed address

data rate Dynamic RAM organized as 4 x 8,388,608 words by 4

•

Four banks operation

bits, fabricated with SAMSUNG′s high performance CMOS

•

MRS cycle with address key programs

technology. Synchronous design allows precise cycle control

-. CAS latency (2 & 3)

with the use of system clock I/O transactions are possible on

-. Burst length (1, 2, 4, 8 Page )

every clock cycle. Range of operating frequencies, programma-

-. Burst type (Sequential & Interleave)

ble burst length and programmable latencies allow the same

• All inputs are sampled at the positive going edge of the system

device to be useful for a variety of high bandwidth, high perfor-

clock.

mance memory system applications.

•

Burst read single-bit write operation

ORDERING INFORMATION

•

DQM for masking

•

Auto & self refresh

Part No.

Max Freq.

Interface

Package

•

64ms refresh period (4K Cycle)

KM44S32030BT-G/FA

133MHz(CL=3)

KM44S32030BT-G/F8

125MHz(CL=3)

54

KM44S32030BT-G/FH

100MHz(CL=2)

LVTTL

TSOP(II)

KM44S32030BT-G/FL

100MHz(CL=3)

FUNCTIONAL BLOCK DIAGRAM

KM44S32030BT-G/F10

66MHz(CL=2 &3)

I/O

LWE

Data Input Register

Control

LDQM

Bank Select

	Address		CounterRefresh	BufferRow	DecoderRow			8M x 4	AMPSense	BufferOutput
								8M x 4			DQi
								8M x 4
CLK								8M x 4
	Register		LRAS	LCBR	Buffer.Col
ADD
							Column Decoder
							Latency & Burst Length
	LCKE						Programming Register
		LRAS	LCBR		LWE	LCAS		LWCBR		LDQM
					Timing Register
	CLK	CKE		CS	RAS	CAS	WE	DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.1 Jun. 1999

KM44S32030B

CMOS SDRAM

PIN CONFIGURATION (Top view)

VDD

1

54

VSS

N.C

2

53

N.C

VDDQ

3

52

VSSQ

N.C

4

51

N.C

DQ0

5

50

DQ3

VSSQ

6

49

VDDQ

N.C

7

48

N.C

N.C

8

47

N.C

VDDQ

9

46

VSSQ

N.C

10

45

N.C

DQ1

11

44

DQ2

VSSQ

12

43

VDDQ

N.C

13

42

N.C

VDD

14

41

VSS

N.C

15

40

N.C/RFU

WE

16

39

DQM

CAS

17

38

CLK

RAS

18

37

CKE

CS

19

36

N.C

BA0

20

35

A11

BA1

21

34

A9

A10/AP

22

33

A8

A0

23

32

A7

A1

24

31

A6

A2

25

30

A5

54Pin TSOP (II)

A3

26

29

A4

(400mil x 875mil)

VDD

27

28

VSS

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CS

Chip select

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE

Clock enable

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A11

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA9, CA11

BA0 ~ BA1

Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

RAS

Row address strobe

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

CAS

Column address strobe

Enables column access.

Enables write operation and row precharge.

WE

Write enable

Latches data in starting from CAS, WE active.

DQM

Data input/output mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQ0 ~ 3

Data input/output

Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

Power supply/ground

Power and ground for the input buffers and the core logic.

VDDQ/VSSQ

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU

No connection

This pin is recommended to be left No Connection on the device.

/reserved for future use

Rev. 0.1 Jun. 1999