Samsung KM48V2100BSL-7, KM48V2100BSL-6, KM48V2100BSL-5, KM48V2100BS-7, KM48V2100BS-5 Datasheet

KM48C2000B, KM48C2100B	CMOS DRAM
KM48V2000B, KM48V2100B
2M x 8Bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-5,-6 or -7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS- before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.

This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability.

It may be used as graphic memory unit for microcomputer, personal computer and portable machines.

FEATURES

¡Ü Part Identification

-KM48C2000B/B-L (5V, 4K Ref.)

-KM48C2100B/B-L (5V, 2K Ref.)

-KM48V2000B/B-L (3.3V, 4K Ref.)

-KM48V2100B/B-L (3.3V, 2K Ref.)

¡Ü	Active Power Dissipation
						Unit : mW
	Speed		3.3V			5V
		4K		2K	4K		2K
	-5	324		396	495		605
	-6	288		360	440		550
	-7	252		324	385		495

¡Ü Refresh Cycles

¡Ü Fast Page Mode operation

¡Ü Byte/Word Read/Write operation

¡Ü CAS-before-RAS refresh capability

¡Ü RAS-only and Hidden refresh capability

¡Ü Self-refresh capability (L-ver only)

¡Ü Fast parallel test mode capability

¡Ü TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

¡Ü Early Write or output enable controlled write

¡Ü JEDEC Standard pinout

¡Ü Available in Plastic SOJ and TSOP(II) packages

¡Ü Single +5V¡¾10% power supply (5V product)

¡Ü Single +3.3V¡¾0.3V power supply (3.3V product)

FUNCTIONAL BLOCK DIAGRAM

Part

VCC

Refresh

Refresh period

NO.

cycle

Normal

L-ver

C2000B

5V

4K

64ms

V2000B

3.3V

128ms

C2100B

5V

2K

32ms

V2100B

3.3V

¡Ü

Performance Range

Speed

tRAC

tCAC

tRC

tPC

Remark

-5

50ns

13ns

90ns

35ns

5V/3.3V

-6

60ns

15ns

110ns

40ns

5V/3.3V

-7

70ns

20ns

130ns

45ns

5V/3.3V

RAS

Control

Vcc

CAS

Vss

W

Clocks

VBB Generator

				Data in
	Refresh Timer	Row Decoder		Buffer
	Refresh Control		I/O
		Memory Array	&		DQ0
			Amps
					to
	Refresh Counter	2,097,152 x 8
					DQ7
		Cells
A0-A11	Row Address Buffer		Sense
(A0 - A10)*1				Data out
A0 - A8
	Col. Address Buffer	Column Decoder		Buffer	OE
(A0 - A9)*1
Note) *1 : 2K Refresh

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

KM48C2000B, KM48C2100B	CMOS DRAM
KM48V2000B, KM48V2100B

PIN CONFIGURATION (Top Views)

¡Ü		KM48C/V20(1)00BK							¡Ü			KM48C/V20(1)00BS
	VCC							VSS		VCC			1		28			VSS
				1	¡Û	28								¡Û
DQ0				2		27		DQ7		DQ0			2		27			DQ7
DQ1				3		26		DQ6		DQ1			3		26			DQ6
DQ2				4		25		DQ5		DQ2			4		25			DQ5
DQ3				5		24		DQ4		DQ3			5		24			DQ4
	W			6		23		CAS		W			6		23			CAS
	RAS			7		22		OE		RAS			7		22			OE
*A11(N.C)				8		21		A9	*A11(N.C)				8		21			A9
	A10			9		20		A8		A10			9		20			A8
	A0			10		19		A7		A0			10		19			A7
	A1			11		18		A6		A1			11		18			A6
	A2			12		17		A5		A2			12		17			A5
	A3			13		16		A4		A3			13		16			A4
	VCC			14		15		VSS		VCC			14		15			VSS

*A11 is N.C for KM48C/V2100B(5V/3.3V, 2K Ref. product)

K : 300mil 28 SOJ

S : 300mil 28 TSOP II

Pin Name

Pin Function

A0 - A11

Address Inputs (4K Product)

A0 - A10

Address Inputs (2K Product)

DQ0 - 7

Data In/Out

VSS

Ground

Row Address Strobe

RAS

Column Address Strobe

CAS

Read/Write Input

W

Data Output Enable

OE

VCC

Power(+5V)

Power(+3.3V)

N.C

No Connection (2K Ref. product)

KM48C2000B, KM48C2100B								CMOS DRAM
KM48V2000B, KM48V2100B
ABSOLUTE MAXIMUM RATINGS
Parameter		Symbol				Rating				Units
				3.3V				5V
Voltage on any pin relative to VSS		VIN,VOUT	-0.5	to	+4.6		-1.0	to	+7.0	V
Voltage on VCC supply relative to VSS		VCC	-0.5	to	+4.6		-1.0	to	+7.0	V
Storage Temperature		Tstg	-55	to	+150		-55 to +150			¡É
Power Dissipation		PD		1				1		W
Short Circuit Output Current		IOS		50				50		mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70¡É)

	Parameter	Symbol		3.3V				5V		Units
			Min	Typ		Max	Min	Typ	Max
Supply Voltage		VCC	3.0	3.3		3.6	4.5	5.0	5.5	V
Ground		VSS	0	0		0	0	0	0	V
Input High Voltage		VIH	2.0	-		VCC+0.3*1	2.4	-	VCC+1.0*1	V
Input Low Voltage		VIL	-0.3*2	-		0.8	-1.0*2	-	0.8	V
*1	: VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2	: -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

	Max		Parameter	Symbol	Min	Max	Units
		Input Leakage Current (Any input 0¡ÂVIN¡ÂVIN+0.3V,		II(L)	-5	5	uA
		all other input pins not under test=0 Volt)
	3.3V	Output Leakage Current		IO(L)	-5	5	uA
		(Data out is disabled, 0V¡ÂVOUT¡ÂVCC)
		Output High Voltage Level(IOH=-2mA)		VOH	2.4	-	V
		Output Low Voltage Level(IOL=2mA)		VOL	-	0.4	V
		Input Leakage Current (Any input 0¡ÂVIN¡ÂVIN+0.5V,		II(L)	-5	5	uA
		all other input pins not under test=0 Volt)
	5V	Output Leakage Current		IO(L)	-5	5	uA
		(Data out is disabled, 0V¡ÂVOUT¡ÂVCC)
		Output High Voltage Level(IOH=-5mA)		VOH	2.4	-	V
		Output Low Voltage Level(IOL=4.2mA)		VOL	-	0.4	V