KS57C4104/P4104/C4204/P4204/C4304/P4304 |
PRODUCT OVERVIEW |
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1 PRODUCT OVERVIEW
OVERVIEW
The KS57C4104/KS57C4204/KS57C4304 single-chip CMOS microcontroller has been designed for very high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontroller).
With an A/D converter, LED direct drive pins, an 8-bit serial I/O interface, and an 8-bit timer/counter, the KS57C4104/KS57C4204/KS57C4304 offers you an excellent design solution for a wide variety of home appliance applications — electric fans, cookers, boilers, and air conditioners, for example.
Up to 35 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events.
In addition, the KS57C4104/KS57C4204/KS57C4304's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
OTP
The KS57C4104/KS57C4204/KS57C4304 microcontroller is also available in OTP (One Time Programmable) version, KS57P4104/KS57P4204/KS57P4304. KS57P4104/KS57P4204/KS57P4304 microcontroller has an onchip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The KS57P4104/KS57P4204/KS57P4304 is comparable to KS57C4104/KS57C4204/KS57C4304, in function, in D.C. electrical characteristics and in pin configuration.
DEVELOPMENT SUPPORT
The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for KS57-series microcontrollers that is powerful, reliable, and portable. In addition to its window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction timing, and performance measurement applications.
The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard hex files that also contain program control data for SMDS compatibility.
1-1
PRODUCT OVERVIEW |
KS57C4104/P4104/C4204/P4204/C4304/P4304 |
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FEATURES SUMMARY
Memory
•256 × 4-bit RAM
•4,096 × 8-bit ROM
35 I/O Pins
•I/O: 31 pins including 8 LED direct drive pins (KS57C4104/C4304)
18 pins including 8 LED direct drive pins (KS57C4204)
•Input only: 4 pins
A/D Converter
•6-channel with 8-bit resolution
•22.89 µs conversion speed at 4.19 MHz
Basic Timer
•One 8-bit basic timer
•Watchdog timer functions
•Four interval clock selection
Timer/Counters
•Two 8-bit timer/counter (TC0, TC1)
•Programmable 8-bit timer
•External event counter
•Arbitrary clock frequency output
•PWM output mode (TC1)
Watch Timer
•One watch timer 8-bit
•Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz
•Four frequency outputs to BUZ pin
8-bit Serial I/O Interface
•8-bit transmit/receive mode
•8-bit receive mode
•LSB-first or MSB-first transmission selectable
•Internal or external clock source
Built-in reset circuit (KS57C4304 only)
•Built-in power-on reset circuit
Interrupts
•Five internal vectored interrupts (INTB, INTT0, INTT1, INTS, INTAD)
•Three external vectored interrupts (INT0, INT1, INT4)
•Two quasi-interrupts (INT2, INTW)
Bit Sequential Carrier
•Supports 16-bit serial data transfer in arbitrary format
Memory-Mapped I/O Structure
•Data memory bank 15
Two Power-Down Modes
•Idle mode (only CPU clock stops)
•Stop mode (system oscillation stops)
Oscillation Sources
•Crystal, Ceramic, or RC for system clock
•Crystal, Ceramic: 0.4–6.0 MHz
•RC: 4 MHz (typ)
•CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
•0.95, 1.91, 15.3 µs at 4.19 MHz
•0.67, 1.33, 10.7 µs at 6.0 MHz
Operating Temperature
•– 40 °C to 85 °C
Operating Voltage Range
• 1.8 V to 5.5 V (KS57C4104/C4204)
•2.5 V to 5.5 V (KS57C4304)
Package Type
•42-pin SDIP, 44-pin QFP (KS57C4104/C4304)
30-pin SDIP, 28-pin SOP (KS57C4204)
1-2
KS57C4104/P4104/C4204/P4204/C4304/P4304 |
ELECTRICAL DATA |
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14 ELECTRICAL DATA
OVERVIEW
In this section, information on KS57C4104/C4204/C4304 electrical characteristics is presented as tables and graphics. The information is arranged in the following order:
Standard Electrical Characteristics
—Absolute maximum ratings
—D.C. electrical characteristics
—System clock oscillator characteristics
—Operating voltage range
—A.C. electrical characteristics
—A/D converter electrical characteristics
—I/O capacitance
Stop Mode Characteristics and Timing Waveforms
—RAM data retention supply voltage in stop mode
—Stop mode release timing when initiated by RESET
—Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
—A.C timing measurement points (except for XIN)
—Clock timing measurement at XIN
—TCL0/1 timing
—Input timing for RESET signal
—Input timing for external interrupts and quasi-interrupts
—KS57C4304 power-on RESET timing
—Serial data transfer timing
14-1
ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304
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Table 14-1. KS57C4104/C4204 Absolute Maximum Ratings |
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(T |
A |
= 25 °C) |
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Parameter |
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Symbol |
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Conditions |
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Rating |
Units |
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Supply Voltage |
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VDD |
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– |
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– 0.3 |
to + 6.5 |
V |
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Input Voltage |
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VI |
All I/O ports |
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– 0.3 |
to |
VDD + 0.3 |
V |
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Output Voltage |
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VO |
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– |
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– 0.3 |
to |
VDD + 0.3 |
V |
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Output Current High |
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IOH |
One pin |
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– 15 |
mA |
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All output pins |
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– 35 |
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Output Current Low |
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IOL |
One pin |
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peak value (note) |
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+ 30 |
mA |
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rms value |
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+ 15 |
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All pins |
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peak value (note) |
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+ 100 |
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rms value |
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+ 60 |
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Operating Temperature |
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TA |
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– |
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– 40 to + 85 |
°C |
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Storage Temperature |
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Tstg |
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– |
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– 65 to + 150 |
°C |
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NOTE: The values for Output Current Low (IOL) are calculated as Peak Value × |
Duty . |
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14-2
KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA
Table 14-2. KS57C4104/C4204 D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter |
Symbol |
Conditions |
Min |
Typ |
Max |
Units |
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Input High |
VIH1 |
All input pins except those specified |
0.7 VDD |
– |
VDD |
V |
Voltage |
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below for VIH2–VIH3 |
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VIH2 |
Ports 0, 1, 3, 6 and RESET |
0.8 VDD |
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VDD |
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VIH3 |
XIN, XOUT |
VDD – 0.1 |
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VDD |
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Input Low |
VIL1 |
All input pins except those specified |
– |
– |
0.3 VDD |
V |
Voltage |
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below for VIL2–VIL3 |
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VIL2 |
Ports 0, 1, 3, 6 and RESET |
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0.2 VDD |
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VIL3 |
XIN, XOUT |
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0.1 |
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Output High |
VOH |
VDD = 4.5 V to 5.5 V |
VDD – 1.0 |
– |
– |
V |
Voltage |
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IOH = – 1 mA |
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Ports 0, 2–8 |
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Output Low |
VOL |
VDD = 4.5 V to 5.5 V |
– |
0.4 |
2 |
V |
Voltage |
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IOL = 15 mA |
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Ports 4 and 5 only |
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IOL = 4 mA |
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0.2 |
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All output ports except ports 4 and 5 |
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Input High |
ILIH1 |
VI = VDD |
– |
– |
3 |
µA |
Leakage Current |
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All input pins except those specified |
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below for ILIH2 |
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ILIH2 |
VI = VDD |
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20 |
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XIN and XOUT only |
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Input Low |
ILIL1 |
VI = 0 V |
– |
– |
– 3 |
µA |
Leakage Current |
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All input pins except XIN and XOUT, |
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RESET |
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ILIL2 |
VI = 0 V |
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– 20 |
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XIN and XOUT only |
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Output High |
ILOH |
VO = VDD |
– |
– |
3 |
µA |
Leakage Current |
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All output pins |
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Output Low |
ILOL |
VO = 0 V |
– |
– |
– 3 |
µA |
Leakage Current |
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All output pins |
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Pull-up Resistor |
RL1 |
VI = 0 V; VDD = 5 V except RESET |
25 |
50 |
100 |
kΩ |
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VI = 0 V; VDD = 3 V except RESET |
50 |
100 |
200 |
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Pull-up Resistor |
RL2 |
VI = 0 V; VDD = 5 V; RESET |
100 |
250 |
400 |
kΩ |
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VI = 0 V; VDD = 3 V; RESET |
200 |
500 |
800 |
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14-3
ELECTRICAL DATA |
KS57C4104/P4104/C4204/P4204/C4304/P4304 |
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Table 14-2. KS57C4104/C4204 D.C. Electrical Characteristics (Continued) |
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(TA = – 40 °C to + 85 °C, VDD = 1.8 V to |
5.5 |
V) |
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Parameter |
Symbol |
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Conditions |
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Min |
Typ |
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Max |
Units |
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Supply |
IDD1 |
Run mode; VDD = 5.0 V ± 10% |
6.0MHz |
– |
3.0 |
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8.0 |
mA |
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Current (1) |
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Crystal oscillator; C1=C2=22pF |
4.19MHz |
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2.3 |
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5.5 |
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VDD = 3 V ± 10% |
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6.0MHz |
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1.4 |
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4.0 |
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4.19MHz |
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1.1 |
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3.0 |
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IDD2 |
Idle mode; VDD = 5.0 V ± 10% |
6.0MHz |
– |
1.1 |
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2.5 |
mA |
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Crystal oscillator; C1=C2=22pF |
4.19MHz |
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1.0 |
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1.8 |
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VDD = 3 V ± 10% |
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6.0MHz |
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0.5 |
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1.5 |
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4.19MHz |
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0.4 |
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1.0 |
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IDD3 |
Stop mode; VDD = 5.0 |
V ± 10% |
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– |
0.1 |
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5.0 |
μA |
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Stop mode; VDD = 3.0 |
V ± 10% |
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0.1 |
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3.0 |
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NOTES:
1.D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers, output port drive currents and ADC.
2.The supply current assumes a CPU clock of fx/4.
14-4
KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA
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Table 14-3. KS57C4104/C4204 System Clock Oscillator Characteristics |
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(TA = – 40 °C to + 85 °C, VDD = |
1.8 V to 5.5 V) |
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Oscillator |
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Clock |
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Parameter |
Test Condition |
Min |
Typ |
Max |
Units |
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Configuration |
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Ceramic |
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Xin |
Xout |
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Oscillation frequency (1) |
VDD = 2.7 V |
to |
5.5 V |
0.4 |
– |
6.0 |
MHz |
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Oscillator |
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C1 |
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C2 |
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VDD = 2.0 V |
to |
5.5 V |
0.4 |
– |
4.2 |
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VDD = 1.8 V |
to |
5.5 V |
0.4 |
– |
3.0 |
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Stabilization time (2) |
VDD = 3.0 V |
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– |
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4 |
ms |
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Crystal |
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Xin |
Xout |
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Oscillation frequency (1) |
VDD = 2.7 V |
to |
5.5 V |
0.4 |
– |
6.0 |
MHz |
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C1 |
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VDD = 2.0 V |
to |
5.5 V |
0.4 |
– |
4.2 |
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VDD = 1.8 V |
to |
5.5 V |
0.4 |
– |
3.0 |
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Stabilization time (2) |
VDD = 3.0 V |
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10 |
ms |
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External |
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Xin |
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Xout |
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X |
input frequency (1) |
VDD = 2.7 V |
to |
5.5 V |
0.4 |
– |
6.0 |
MHz |
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Clock |
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IN |
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VDD = 2.0 V |
to |
5.5 V |
0.4 |
– |
4.2 |
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VDD = 1.8 V |
to |
5.5 V |
0.4 |
– |
3.0 |
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XIN input high and low |
– |
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83.3 |
– |
1250 |
ns |
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level width (tXH, tXL) |
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RC |
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Xin Xout |
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Oscillation frequency |
VDD = 5 V |
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– |
4 |
– |
MHz |
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Oscillator |
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limitation |
R = 8.2 KΩ |
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R |
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NOTES:
1.Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2.Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
14-5
ELECTRICAL DATA |
KS57C4104/P4104/C4204/P4204/C4304/P4304 |
|
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CPU CLOCK
1.5 MHz
1.05 MHz
0.75MHz
15.6kHz
1 |
2 |
3 |
4 |
5 |
6 |
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1.8 |
2.7 |
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5.5 |
Main Oscillator Frequency (Divided by 4)
6 MHz
4.2 MHz
3 MHz
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. KS57C4104/C4204 Standard Operating Voltage Range
Table 14-4. KS57C4104/C4204 A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter |
Symbol |
Conditions |
|
Min |
Typ |
Max |
Units |
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Instruction Cycle |
tCY |
VDD = 2.7 V |
to |
5.5 |
V |
0.67 |
– |
64 |
μs |
Time |
|
VDD = 1.8 V |
to |
5.5 |
V |
1.33 |
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TCL0/1 Input |
fTI |
VDD = 2.7 V |
to |
5.5 |
V |
0 |
– |
1.5 |
MHz |
Frequency |
|
VDD = 1.8 V to 5.5 V |
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0.75 |
MHz |
|||
TCL0/1 Input High, |
tTIH, tTIL |
VDD = 2.7 V |
to |
5.5 |
V |
0.48 |
– |
– |
μs |
Low Width |
|
VDD = 1.8 V to 5.5 V |
1.8 |
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SCK Cycle Time |
tKCY |
VDD = 2.7 V to 5.5 V |
800 |
– |
– |
ns |
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External SCK source |
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Internal SCK source |
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670 |
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VDD = 1.8 V to 5.5 V |
3200 |
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External SCK source |
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Internal SCK source |
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3800 |
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14-6
KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA
Table 14-4. KS57C4104/C4204 A.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter |
Symbol |
Conditions |
Min |
Typ |
Max |
Units |
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SCK High, Low |
tKH, tKL |
VDD = 2.7 V to 5.5 V |
335 |
– |
– |
ns |
Width |
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External SCK source |
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Internal SCK source |
tKCY/2 – 50 |
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VDD = 1.8 V to 5.5 V |
1600 |
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External SCK source |
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Internal SCK source |
tKCY/2 – 150 |
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SI Setup Time to |
tSIK |
VDD = 2.7 V to 5.5 V |
100 |
– |
– |
ns |
SCK High |
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External SCK source |
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Internal SCK source |
150 |
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VDD = 1.8 V to 5.5 V |
150 |
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External SCK source |
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Internal SCK source |
500 |
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SI Hold Time to |
tKSI |
VDD = 2.7 V to 5.5 V |
400 |
– |
– |
ns |
SCK High |
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External SCK source |
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Internal SCK source |
400 |
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VDD = 1.8 V to 5.5 V |
600 |
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External SCK source |
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Internal SCK source |
500 |
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Output Delay for |
tKSO (1) |
VDD = 2.7 V to 5.5 V |
– |
– |
300 |
ns |
SCK to SO |
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External SCK source |
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Internal SCK source |
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250 |
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VDD = 1.8 V to 5.5 V |
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1000 |
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External SCK source |
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Internal SCK source |
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1000 |
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Interrupt Input |
tINTH, |
INT0 |
(2) |
– |
– |
μs |
High, Low Width |
tINTL |
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INT1, INT2, INT4, KS0–KS3 |
10 |
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RESET Input Low |
tRSL |
Input |
10 |
– |
– |
μs |
Width |
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NOTES:
1.R(1KΩ) and C (100pF) are the load resistance and load capacitance of the SO output line.
2.Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
14-7
ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304
|
|
|
Table 14-5. KS57C4304 Absolute Maximum Ratings |
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(T |
A |
= 25 °C) |
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Parameter |
Symbol |
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Conditions |
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Rating |
Units |
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Supply Voltage |
VDD |
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– |
|
– 0.3 |
to + 6.5 |
V |
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Input Voltage |
VI |
All I/O ports |
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– 0.3 |
to |
VDD + 0.3 |
V |
||
Output Voltage |
VO |
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– |
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– 0.3 |
to |
VDD + 0.3 |
V |
||
Output Current High |
IOH |
One pin |
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– 15 |
mA |
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All output pins |
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– 35 |
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Output Current Low |
IOL |
One pin |
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peak value (note) |
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+ 30 |
mA |
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rms value |
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+ 15 |
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All pins |
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peak value (note) |
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+ 100 |
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rms value |
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+ 60 |
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Operating Temperature |
TA |
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– |
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– 40 to + 85 |
°C |
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Storage Temperature |
Tstg |
|
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– |
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– 65 to + 150 |
°C |
||||
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value × |
Duty . |
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14-8
KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA
Table 14-6. KS57C4304 D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)
Parameter |
Symbol |
Conditions |
Min |
Typ |
Max |
Units |
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|
Input High |
VIH1 |
All input pins except those specified |
0.7 VDD |
– |
VDD |
V |
Voltage |
|
below for VIH2–VIH3 |
|
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|
VIH2 |
Ports 0, 1, 3, 6 and RESET |
0.8 VDD |
|
VDD |
|
|
VIH3 |
XIN, XOUT |
VDD – 0.1 |
|
VDD |
|
Input Low |
VIL1 |
All input pins except those specified |
– |
– |
0.3 VDD |
V |
Voltage |
|
below for VIL2–VIL3 |
|
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VIL2 |
Ports 0, 1, 3, 6 and RESET |
|
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0.2 VDD |
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VIL3 |
XIN, XOUT |
|
|
0.1 |
|
Output High |
VOH |
VDD = 4.5 V to 5.5 V |
VDD – 1.0 |
– |
– |
V |
Voltage |
|
IOH = – 1 mA |
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Ports 0, 2–8 |
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Output Low |
VOL |
VDD = 3.5 V |
– |
0.4 |
2 |
V |
Voltage |
|
IOL = 15 mA |
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Ports 4 and 5 only |
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IOL = 4 mA |
|
0.2 |
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All output ports except ports 4 and 5 |
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Input High |
ILIH1 |
VI = VDD |
– |
– |
3 |
µA |
Leakage Current |
|
All input pins except those specified |
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below for ILIH2 |
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ILIH2 |
VI = VDD |
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20 |
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XIN and XOUT only |
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Input Low |
ILIL1 |
VI = 0 V |
– |
– |
– 3 |
µA |
Leakage Current |
|
All input pins except XIN and XOUT, |
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RESET |
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ILIL2 |
VI = 0 V |
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– 20 |
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XIN and XOUT only |
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|
Output High |
ILOH |
VO = VDD |
– |
– |
3 |
µA |
Leakage Current |
|
All output pins |
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|
Output Low |
ILOL |
VO = 0 V |
– |
– |
– 3 |
µA |
Leakage Current |
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All output pins |
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Pull-Up Resistor |
RL1 |
VI = 0 V; VDD = 5 V except RESET |
25 |
50 |
100 |
kΩ |
|
|
VI = 0 V; VDD = 3 V except RESET |
50 |
100 |
200 |
|
Pull-Up Resistor |
RL2 |
VI = 0 V; VDD = 5 V; RESET |
100 |
250 |
400 |
kΩ |
|
|
VI = 0 V; VDD = 3 V; RESET |
200 |
500 |
800 |
|
14-9
ELECTRICAL DATA |
KS57C4104/P4104/C4204/P4204/C4304/P4304 |
|
|
|
Table 14-6. KS57C4304 D.C. Electrical Characteristics (Continued) |
|
|
||||||
(TA = – 40 °C to + 85 °C, VDD = |
2.5 V |
to 5.5 V) |
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Parameter |
Symbol |
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Conditions |
|
Min |
Typ |
Max |
Units |
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Supply |
IDD1 |
Run mode; V |
= 5.0 V ± 10% |
6.0MHz |
– |
3.1 |
8.0 |
mA |
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DD |
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Current (1) |
|
Crystal oscillator; C1 = C2 = 22pF |
4.19MHz |
|
2.4 |
5.5 |
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||
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VDD = 3 |
V ± 10% |
6.0MHz |
|
1.5 |
4.0 |
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4.19MHz |
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1.2 |
3.0 |
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IDD2 |
Idle mode; VDD = 5.0 V ± 10% |
6.0MHz |
– |
1.2 |
2.5 |
mA |
||
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Crystal oscillator; C1 = C2 = 22pF |
4.19MHz |
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1.1 |
1.8 |
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VDD = 3 |
V ± 10% |
6.0MHz |
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0.6 |
1.5 |
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4.19MHz |
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0.5 |
1.0 |
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||
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IDD3 |
Stop mode; VDD = 5.0 V ± 10% |
|
– |
120 |
200 |
μA |
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Stop mode; VDD = 3.0 V ± 10% |
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100 |
150 |
|
NOTES:
1.D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers, output port drive currents and ADC.
2.The supply current assumes a CPU clock of fx/4.
Table 14-7. KS57C4304 Power-On Reset Circuit Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)
Parameter |
Symbol |
Conditions |
Min |
Typ |
Max |
Units |
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Power-On Reset |
VDDH |
|
2.5 |
|
5.5 |
V |
Voltage High |
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Power-On Reset |
VDDL |
|
0 |
2.0 |
2.2 |
V |
Voltage Low |
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Power Supply |
tr |
|
10 |
|
(1) |
us |
Voltage Rise Time |
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Power Supply |
toff |
|
0.5 |
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|
s |
Voltage Off Time |
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|
|
Power-On Reset Circuit |
IDDPR |
VDD = 5 V ± 10% |
|
120 |
200 |
uA |
Cunsumption Current (2) |
|
VDD = 3 V ± 10% |
|
100 |
150 |
uA |
NOTES:
1.217/fx (= 31.3 ms at fx = 4.19 MHz)
2.Current consumed when power-on reset circuit is provided internally.
14-10
KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA
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|
|
Table 14-8. KS57C4304 System Clock Oscillator Characteristics |
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|||||||||||||||
(TA = – 40 °C to + 85 °C, VDD = |
2.5 V to 5.5 V) |
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Oscillator |
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Clock |
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Parameter |
Test Condition |
Min |
Typ |
Max |
Units |
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Configuration |
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Ceramic |
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Xin |
Xout |
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|
Oscillation frequency (1) |
VDD = 2.7 V |
to |
5.5 V |
0.4 |
– |
6.0 |
MHz |
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Oscillator |
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VDD = 2.5 V |
to |
5.5 V |
0.4 |
– |
4.2 |
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Stabilization time (2) |
VDD = 3.0 V |
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– |
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4 |
ms |
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Crystal |
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Xin |
Xout |
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Oscillation frequency (1) |
VDD = 2.7 V |
to |
5.5 V |
0.4 |
– |
6.0 |
MHz |
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VDD = 2.5 V |
to |
5.5 V |
0.4 |
– |
4.2 |
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Stabilization time (2) |
VDD = 3.0 V |
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– |
– |
10 |
ms |
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External |
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Xin |
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Xout |
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X |
input frequency (1) |
VDD = 2.7 V |
to |
5.5 V |
0.4 |
– |
6.0 |
MHz |
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Clock |
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IN |
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VDD = 2.5 V to 5.5 V |
0.4 |
– |
4.2 |
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XIN input high and low |
– |
83.3 |
– |
1250 |
ns |
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level width (tXH, tXL) |
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RC |
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Xin Xout |
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Oscillation frequency |
VDD = 5 V |
– |
4 |
– |
MHz |
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Oscillator |
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limitation |
R = 8.2 KΩ |
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R |
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NOTES:
1.Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2.Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
14-11
ELECTRICAL DATA |
KS57C4104/P4104/C4204/P4204/C4304/P4304 |
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CPU CLOCK
1.5 MHz
1.05 MHz
0.75MHz
15.6kHz
1 |
2 |
3 |
4 |
5 |
6 |
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1.8 |
2.7 |
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5.5 |
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2.5 |
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Main Oscillator Frequency (Divided by 4)
6 MHz
4.2 MHz
3 MHz
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-2. KS57C4304 Standard Operating Voltage Range
14-12
KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA
|
Table 14-9. KS57C4304 A.C. Electrical Characteristics |
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(TA = – 40 °C to + 85 °C, VDD = |
2.5 V to |
5.5 V) |
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Parameter |
Symbol |
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Conditions |
Min |
Typ |
Max |
Units |
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Instruction Cycle |
tCY |
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VDD = 2.7 |
V |
to |
5.5 V |
0.67 |
– |
64 |
µs |
Time |
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TCL0/1 Input |
fTI0 |
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VDD = 2.7 |
V |
to |
5.5 V |
0 |
– |
1.5 |
MHz |
Frequency |
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TCL0/1 Input |
tTIH0, tTIL0 |
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VDD = 2.7 V |
to |
5.5 V |
0.48 |
– |
– |
µs |
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High, Low Width |
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SCK Cycle Time |
tKCY |
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VDD = 2.7 |
V to 5.5 V |
800 |
– |
– |
ns |
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External SCK source |
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Internal SCK source |
670 |
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SCK High, Low |
tKH, tKL |
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VDD = 2.7 |
V |
to |
5.5 V |
325 |
– |
– |
ns |
Width |
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External SCK source |
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Internal SCK source |
tKCY/2 – 50 |
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SI Setup Time to |
tSIK |
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VDD = 2.7 |
V |
to |
5.5 V |
100 |
– |
– |
ns |
SCK High |
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External SCK source |
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Internal SCK source |
150 |
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SI Hold Time to |
tKSI |
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VDD = 2.7 V |
to |
5.5 V |
400 |
– |
– |
ns |
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SCK High |
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External SCK source |
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Internal SCK source |
400 |
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Output Delay for |
tKSO |
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VDD = 2.7 |
V |
to |
5.5 V |
– |
– |
300 |
ns |
SCK to SO |
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External SCK source |
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Internal SCK source |
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250 |
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Interrupt Input |
tINTH, |
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INT0 |
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(NOTE) |
– |
– |
µs |
High, Low Width |
tINTL |
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INT1, INT2, INT4, KS0–KS3 |
10 |
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RESET Input |
tRSL |
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Input |
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10 |
– |
– |
µs |
Low Width |
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NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
14-13
ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304
Table 14-10. A/D Converter Electrical Characteristics
(TA = – 10 °C to + 70 °C, VDD = 3.5 V to 5.5 V, VSS = AVSS = 0 V)
Parameter |
Symbol |
Condition |
Min |
Typ |
Max |
Units |
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Resolution |
– |
– |
8 |
8 |
8 |
bit |
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Absolute accuracy (1) |
– |
2.5 V < AVREF < VDD |
– |
– |
± 1.5 |
LSB |
Conversion time (2) |
tCON |
– |
– |
96/fx (3) |
– |
µs |
Analog input voltage |
VIAN |
– |
AVSS |
– |
AVREF |
V |
Analog input impedance |
RAN |
– |
– |
1000 |
– |
MΩ |
NOTES:
1.Absolute accuracy does not include the quantization error (± 1/2 LSB).
2.Conversion time is the time required from the moment a conversion operation starts until it ends (EOC = 0).
3.fx' is the abbreviation for system clock.
Table 14-11. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter |
Symbol |
Condition |
Min |
Typ |
Max |
Units |
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Input |
CIN |
f = 1 MHz; Unmeasured pins |
– |
– |
15 |
pF |
Capacitance |
|
are returned to VSS |
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Output |
COUT |
|
– |
– |
15 |
pF |
Capacitance |
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I/O Capacitance |
CIO |
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– |
– |
15 |
pF |
Table 14-12. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter |
Symbol |
Conditions |
Min |
Typ |
Max |
Unit |
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Data retention supply voltage |
VDDDR |
– |
1.8 |
– |
5.5 |
V |
Data retention supply current |
IDDDR |
– |
– |
0.1 |
10 |
µA |
Release signal set time |
tSREL |
– |
0 |
– |
– |
ms |
Oscillation stabilization time (1) |
tWAIT |
When released by |
– |
217/fx |
– |
ms |
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RESET |
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When released by |
– |
(2) |
– |
ms |
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interrupt |
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NOTES:
1.During oscillation stabilization time, CPU operation must be stopped to avoid unstable operation upon oscillation start.
2.The basic timer causes a delay of 217/fx after a reset.
14-14