Samsung KM48V8104CSL-5, KM48V8104CSL-45, KM48V8104CS-6, KM48V8104CS-5, KM48V8104CS-45 Datasheet

KM48V8004C,KM48V8104C	CMOS DRAM

8M x 8bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

FEATURES

•Part Identification

-KM48V8004C/C-L(3.3V, 8K Ref.)

-KM48V8104C/C-L(3.3V, 4K Ref.)

•Active Power Dissipation

		Unit : mW
Speed	8K	4K
-45	324	432
-5	288	396
-6	252	360

• Refresh Cycles

	Part	Refresh	Refresh time
	NO.	cycle	Normal	L-ver
	KM48V8004C*	8K	64ms	128ms
	KM48V8104C	4K

•Extended Data Out Mode operation

•CAS-before-RAS refresh capability

•RAS-only and Hidden refresh capability

•Self-refresh capability (L-ver only)

•Fast parallel test mode capability

•LVTTL(3.3V) compatible inputs and outputs

•Early Write or output enable controlled write

•JEDEC Standard pinout

•Available in Plastic SOJ and TSOP(II) packages

•+3.3V±0.3V power supply

FUNCTIONAL BLOCK DIAGRAM

RAS

Control

Vcc

CAS

Clocks

VBB Generator

Vss

W

*	Access mode & RAS only refresh mode
	: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)						Refresh Timer	Row Decoder
	CAS-before-RAS & Hidden refresh mode								& I/O	Data in
	: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)						Refresh Control	Memory Array		Buffer
									Amps
	Performance Range:						Refresh Counter	8,388,608 x 8
¡Ü								Cells	Sense
	Speed	tRAC	tCAC	tRC	tHPC	A0~A12	Row Address Buffer			Data out
	-45	45ns	12ns	74ns	17ns	(A0~A11)*1				Buffer
						A0~A9	Col. Address Buffer	Column Decoder
	-5	50ns	13ns	84ns	20ns	(A0~A10)*1
	-6	60ns	15ns	104ns	25ns		Note) *1 : 4K Refresh

DQ0

to

DQ7

OE

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

KM48V8004C,KM48V8104C	CMOS DRAM

PIN CONFIGURATION (Top Views)

		•KM48V80(1)04CK
	VCC				1	32			VSS
	DQ0				2	31			DQ7
	DQ1				3	30			DQ6
	DQ2				4	29			DQ5
	DQ3				5	28			DQ4
	N.C				6	27			VSS
	VCC				7	26
									CAS
					8	25
		W							OE
					9	24			A12(N.C)*
	RAS
	A0				10	23			A11
	A1				11	22			A10
	A2				12	21			A9
	A3				13	20			A8
	A4				14	19			A7
	A5				15	18			A6
	VCC				16	17			VSS

(K : 400mil SOJ)

* (N.C) : N.C for 4K Refresh product

					•KM48V80(1)04CS
	VCC						1	32		VSS
DQ0							2	31		DQ7
DQ1							3	30		DQ6
DQ2							4	29		DQ5
DQ3							5	28		DQ4
	N.C						6	27		VSS
	VCC						7	26		CAS
		W					8	25		OE
	RAS						9	24		A12(N.C)*
	A0						10	23		A11
	A1						11	22		A10
	A2						12	21		A9
	A3						13	20		A8
	A4						14	19		A7
	A5						15	18		A6
	VCC						16	17		VSS

(S : 400mil TSOP(II))

			Pin Name				Pin Function
			A0 - A12				Address Inputs(8K Product)
			A0 - A11				Address Inputs(4K Product)
			DQ0 - 7				Data In/Out
			VSS				Ground
							Row Address Strobe
			RAS
							Column Address Strobe
			CAS
							Read/Write Input
			W
							Data Output Enable
			OE
			VCC				Power(+3.3V)
			N.C				No Connection

KM48V8004C,KM48V8104C					CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter	Symbol	Rating				Units
Voltage on any pin relative to VSS	VIN,VOUT	-0.5	to	+4.6		V
Voltage on VCC supply relative to VSS	VCC	-0.5	to	+4.6		V
Storage Temperature	Tstg	-55 to +150				°C
Power Dissipation	PD		1			W
Short Circuit Output Current	IOS		50			mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70°C)

	Parameter	Symbol	Min	Typ	Max	Units
Supply Voltage		VCC	3.0	3.3	3.6	V
Ground		VSS	0	0	0	V
Input High Voltage		VIH	2.0	-	VCC+0.3*1	V
Input Low Voltage		VIL	-0.3*2	-	0.8	V
*1	: VCC+1.3V at pulse width≤15ns which is measured at VCC
*2	: -1.3 at pulse width≤15ns which is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

	Parameter		Symbol	Min	Max	Units
	Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,		II(L)	-5	5	uA
	all other pins not under test=0 Volt)
	Output Leakage Current		IO(L)	-5	5	uA
	(Data out is disabled, 0V≤VOUT≤VCC)
	Output High Voltage Level(IOH=-2mA)		VOH	2.4	-	V
	Output Low Voltage Level(IOL=2mA)		VOL	-	0.4	V

KM48V8004C,KM48V8104C							CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol	Power	Speed			Max			Units
				KM48V8004C		KM48V8104C
		-45		90		120		mA
ICC1	Don′t care	-5		80		110		mA
		-6		70		100		mA
ICC2	Normal	Don′t care		1		1		mA
	L			1		1		mA
		-45		90		120		mA
ICC3	Don′t care	-5		80		110		mA
		-6		70		100		mA
		-45		100		100		mA
ICC4	Don′t care	-5		90		90		mA
		-6		80		80		mA
ICC5	Normal	Don′t care		500		500		uA
	L			200		200		uA
		-45		120		120		mA
ICC6	Don′t care	-5		110		110		mA
		-6		100		100		mA
ICC7	L	Don′t care		350		350		uA
ICCS	L	Don′t care		350		350		uA

ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)

ICC2 : Standby Current (RAS=CAS=W=VIH)

ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.)

ICC4* : Extended Data Out Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.)

ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V

W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us

ICCS : Self Refresh Current

RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.

KM48V8004C,KM48V8104C

CMOS DRAM

CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A12]

CIN1

-

5

pF

Input capacitance

CIN2

-

7

pF

[RAS,

CAS,

W,

OE]

Output capacitance [DQ0 - DQ7]

CDQ

-

7

pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)

Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

						Parameter													Symbol	-45				-5			-6		Units	Note
																				Min		Max	Min		Max	Min		Max
		Random read or write cycle time																	tRC	74			84			104			ns
		Read-modify-write cycle time																	tRWC	101			113			138			ns
		Access time from																	tRAC			45			50			60	ns	3,4,10
							RAS
		Access time from																	tCAC			12			13			15	ns	3,4,5
							CAS
		Access time from column address																	tAA			23			25			30	ns	3,10
				to output in Low-Z															tCLZ	3			3			3			ns	3
		CAS
		Output buffer turn-off delay from																	tCEZ	3		13	3		13	3		13	ns	6,13
													CAS
			to output in Low-Z																tOLZ	3			3			3			ns	3
		OE
		Transition time (rise and fall)																	tT	1		50	1		50	1		50	ns	2
				precharge time															tRP	25			30			40			ns
		RAS
				pulse width															tRAS	45		10K	50		10K	60		10K	ns
		RAS
				hold time															tRSH	8			8			10			ns
		RAS
				hold time															tCSH	35			38			40			ns
		CAS
				pulse width															tCAS	7		5K	8		10K	10		10K	ns	14
		CAS
				to		delay time													tRCD	11		33	11		37	14		45	ns	4
		RAS			CAS
				to column address delay time															tRAD	9		22	9		25	12		30	ns	10
		RAS
				to		precharge time													tCRP	5			5			5			ns
		CAS			RAS
		Row address set-up time																	tASR	0			0			0			ns
		Row address hold time																	tRAH	7			7			10			ns
		Column address set-up time																	tASC	0			0			0			ns
		Column address hold time																	tCAH	7			7			10			ns
		Column address to										lead time							tRAL	23			25			30			ns
									RAS
		Read command set-up time																	tRCS	0			0			0			ns
		Read command hold time referenced to																	tRCH	0			0			0			ns	8
																CAS
		Read command hold time referenced to																	tRRH	0			0			0			ns	8
															RAS
		Write command hold time																	tWCH	7			7			10			ns
		Write command pulse width																	tWP	6			7			10			ns
		Write command to									lead time								tRWL	8			8			10			ns
								RAS
		Write command to									lead time								tCWL	7			7			10			ns
								CAS
		Data set-up time																	tDS	0			0			0			ns	9

KM48V8004C,KM48V8104C																																																CMOS DRAM
	AC CHARACTERISTICS (Continued)
																		Parameter																					Symbol	-45				-5			-6		Units	Note
																																								Min		Max	Min		Max	Min		Max
		Data hold time																																					tDH	7			7			10			ns	9
		Refresh period (Normal)																																					tREF			64			64			64	ms
		Refresh period (L-ver)																																					tREF			128			128			128	ms
		Write command set-up time																																					tWCS	0			0			0			ns	7
									to			delay time																											tCWD	24			27			32			ns	7
		CAS									W
									to			delay time																											tRWD	57			64			77			ns	7
		RAS									W
		Column address to																							delay time														tAWD	35			39			47			ns	7
																				W
									set-up time																		-before-								refresh)				tCSR	5			5			5			ns
		CAS															(CAS														RAS
									hold time															-before-									refresh)						tCHR	10			10			10			ns
		CAS													(CAS															RAS
									to					precharge time																									tRPC	5			5			5			ns
		RAS									CAS
		Access time from																									precharge												tCPA			24			28			35	ns	3
																		CAS
		Hyper Page cycle time																																					tHPC	17			20			25			ns	14
		Hyper Page read-modify-write cycle time																																					tHPRWC	47			47			56			ns	14
									precharge time (Hyper page cycle)																														tCP	6.5			7			10			ns
		CAS
									pulse width (Hyper page cycle)																														tRASP	45		200K	50		200K	60		200K	ns
		RAS
									hold time from																				precharge										tRHCP	24			30			35			ns
		RAS																			CAS
						access time																																	tOEA			12			13			15	ns	3
		OE
						to data delay																																	tOED	8			10			13			ns
		OE
									precharge to															delay time															tCPWD	36			41			52			ns
		CAS																	W
		Output buffer turn off delay time from																																					tOEZ	3		11	3		13	3		13	ns	6
																																					OE
					command hold time																																		tOEH	5			5			5			ns
		OE
		Write command set-up time (Test mode in)																																					tWTS	10			10			10			ns	11
		Write command hold time (Test mode in)																																					tWTH	10			10			10			ns	11
				to								precharge time (C-B-R refresh)																											tWRP	10			10			10			ns
		W							RAS
				to								hold time (C-B-R refresh)																											tWRH	10			10			10			ns
		W							RAS
		Output data hold time																																					tDOH	4			5			5			ns
		Output buffer turn off delay from																																					tREZ	3		13	3		13	3		13	ns	6,13
																																RAS
		Output buffer turn off delay from																																					tWEZ	3		13	3		13	3		13	ns	6
																																W
			to data delay																																				tWED	8			15			15			ns
		W
					to								hold time																										tOCH	5			5			5			ns
		OE								CAS
							hold time to																																tCHO	5			5			5			ns
		CAS														OE
						precharge time																																	tOEP	5			5			5			ns
		OE
				pulse width (Hyper Page Cycle)																																			tWPE	5			5			5			ns
		W
							pulse width (C-B-R self refresh)																																tRASS	100			100			100			us	15,16,17
		RAS
								precharge time (C-B-R self refresh)																															tRPS	74			90			110			ns	15,16,17
		RAS
								hold time (C-B-R self refresh)																															tCHS	-50			-50			-50			ns	15,16,17
		CAS

	KM48V8004C,KM48V8104C																							CMOS DRAM
TEST MODE CYCLE																										( Note 11 )
							Parameter								Symbol		-45			-5			-6		Units	Note
																Min		Max	Min		Max	Min		Max
		Random read or write cycle time													tRC	79			89			109			ns
		Read-modify-write cycle time													tRWC	110			121			145			ns
		Access time from													tRAC			50			55			65	ns	3,4,10,12
								RAS
		Access time from													tCAC			17			18			20	ns	3,4,5,12
								CAS
		Access time from column address													tAA			28			30			35	ns	3,10,12
					pulse width										tRAS	50		10K	55		10K	65		10K	ns
		RAS
					pulse width										tCAS	12		10K	13		10K	15		10K	ns
		CAS
					hold time										tRSH	18			18			20			ns
		RAS
					hold time										tCSH	39			43			50			ns
		CAS
		Column Address to												lead time	tRAL	28			30			35			ns
										RAS
					to		delay time								tCWD	29			35			39			ns	7
			CAS			W
					to		delay time								tRWD	62			72			84			ns	7
		RAS				W
		Column Address to									delay time				tAWD	40			47			54			ns	7
										W
		Hyper Page cycle time													tHPC	22			25			30			ns	14
		Hyper Page read-modify-write cycle time													tHPRWC	52			53			61			ns	14
					pulse width (Hyper page cycle)										tRASP	50		200K	55		200K	65		200K	ns
		RAS
		Access time from										precharge			tCPA			29			33			40	ns	3
									CAS
				access time											tOEA			17			18			20	ns	3
			OE
				to data delay											tOED	13			18			20			ns
		OE
				command hold time											tOEH	13			18			20			ns
		OE