Samsung KS57C5312, KS57C5308, KS57C5304, KS57P5312, KS57C5208 Datasheet
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KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
OVERVIEW
The KS57C5204/C5208/C5304/C5308/C5312 single-chip CMOS microcontroller has been designed for highperformance using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core is notable for its low energy consumption and low operating voltage.
You can select from three ROM sizes: 4K, 8K, or 12K bytes.
Except for the difference in ROM size, the features and functions of the KS57C5204 and the KS57C5208 are identical and the KS57C5304, KS57C5308, and the KS57C5312 are identical.
With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, the KS57C5204/C5208 /C5304/C5308/C5312 offers an excellent design solution for a wide variety of telecommunication applications.
Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the KS57C5204/C5208, and up to 23 pins of the available 30-pin SDIP or 32-pin SOP package for the KS57C5304/C5308/C5312 can be assign to I/O. Six vectored interrupts for KS57C5204/C5208 and four vectored interrupts for KS57C5304/C5308/C5312 provide fast response to internal and external events. In addition, the KS57C5204/C5208/C5304/C5308/C5312's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
OTP
The KS57C5204/C5208 microcontroller is also available in OTP (One Time Programmable) version, KS57P5208. The KS57C5304/C5308/C5312 microcontroller is also available in OTP (One Time Programmable) version, KS57P5308/P5312. The KS57P5208/P5308/P5312 microcontroller has an on-chip 8K-byte (P5208/P5308) or 12K-byte (P5312) one-time-programable EPROM instead of masked ROM. The KS57P5208 is comparable to KS57C5204/C5208, both in function and in pin configuration. Also, the KS57P5308/P5312 is comparable to the KS57C5304/C5308/C5312, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW |
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 |
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FEATURES
Memory
∙768 × 4-bit RAM
4,096 × 8-bit ROM (KS57C5204/C5304)
8,192 × 8-bit ROM (KS57C5208/C5308)
12,288 × 8-bit ROM (KS57C5312)
I/O Pins
∙Input only: 4 pins (KS57C5204/C5208)
1pins (KS57C5304/C5308/C5312)
∙I/O: 35 pins (KS57C5204/C5208)
23 pins (KS57C5304/C5308/C5312)
∙N-channel open-drain I/O: 8 pins
Memory-Mapped I/O Structure
∙Data memory bank 15
DTMF Generator
∙16 dual-tone frequencies for tone dialing
8-Bit Basic Timer
∙Programmable interval timer
∙Watchdog timer
Two 8-Bit Timer/Counters
∙Programmable 8-bit timer
∙External event counter function
∙Arbitrary clock frequency output
Watch Timer
∙Real-time and time interval generation
∙Four frequency outputs to the BUZ pin
Bit Sequential Carrier
∙Supports 16-bit serial data transfer in arbitrary
format
Interrupts
∙3 external interrupt vectors (KS57C5204/C5208)
1 external interrupt vectors (KS57C5304/C5308/C5312)
∙3 internal interrupt vectors
∙2 quasi-interrupts
Power-Down Modes
∙Idle: Only CPU clock stops
∙Stop: System clock stops
Oscillation Sources
∙Crystal, or ceramic for main system clock
∙Main system clock frequency: 0.4–6.0 MHz (typical)
∙CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
∙0.95, 1.91, and 15.3 μs at 4.19 MHz
∙1.12, 2.23, 17.88 μs at 3.58 MHz
∙0.67, 1.33, 10.7 μs at 6.0 MHz
Operating Temperature
∙– 40 °C to 85 °C
Operating Voltage Range
∙1.8 V to 5.5 V
Package Types
∙42 SDIP, 44 QFP (KS57C5204/C5208)
∙30 SDIP, 32 SOP (KS57C5304/C5308/C5312)
1-2
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
BLOCK DIAGRAM
INT0, INT1, INT2, INT4 |
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8-Bit |
RESET |
XIN |
XOUT |
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Watchdog |
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Timer/ |
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Timer |
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Counter 0 |
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Interrupt |
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Stack |
Basic |
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8-Bit |
Control |
Clock |
Pointer |
Timer |
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Block |
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Timer/ |
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Watch |
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Counter 1 |
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Program |
Timer |
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P1.0/INT0 |
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P6.0-P6.3/ |
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Counter |
Input |
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I/O Port 6 |
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P1.1/INT1 |
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KS0-KS3 |
Interrupts |
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Port 1 |
P1.2/INT2 |
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P7.0-P7.3/ |
I/O Port 7 |
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Program |
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P1.3/INT4 |
Instruction Decoder |
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KS4-KS7 |
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P2.0/TCLO0 |
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Status Word |
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P8.0 - P8.3 |
I/O Port 8 |
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P2.1/TCLO1 |
Arithmetic |
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I/O Port 2 |
P2.2/CLO |
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P2.3/BUZ |
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P9.0 - P9.2 |
I/O Port 9 |
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Logic Unit |
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Flags |
I/O Port 3 |
P3.0/TCL0 |
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P3.1/TCL1 |
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P3.2 |
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P3.3 |
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I/O Port 4 |
P4.0/BTCO |
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P4.1-4.3 |
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768x4-Bit |
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Program Memory |
I/O Port 5 |
P5.0-P5.3 |
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KS57C5204/C5304: 4KBytes |
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Data |
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KS57C5208/C5308: 8KBytes |
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Memory |
DTMF |
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KS57C5312: 12KBytes |
DTMF |
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Generator |
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NOTE: |
KS57C5304/C5308/C5312 does not use P1.1/INT1, P1.2/INT2, P1.3/INT4, P3.2, P3.3, INT1, INT2, |
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INT4, P8.0-P8.3, and P9.0-P9.2. |
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Figure 1-1. KS57C5204/C5208/C5304/C5308/C5312 Simplified Block Diagram
1-3
PRODUCT OVERVIEW |
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 |
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PIN ASSIGNMENTS
P1.0/INT0 
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P1.1/INT1 
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P1.2/INT2 
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P1.3/INT4 
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P2.0/TCLO0 
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P2.1/TCLO1 
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P2.2/CLO 
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P2.3/BUZ 
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P3.0/TCL0 
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P3.1/TCL1 
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VDD 
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VSS 
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XOUT 
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XIN 
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TEST 
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P4.0/BTCO 
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P4.1 
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RESET 
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P3.2 
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P3.3 
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P4.2 21
KS57C5204/C5208 600)-SDIP-(42
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P9.2
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P9.1
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P9.0
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DTMF
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P7.3/KS7
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P7.2/KS6
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P7.1/KS5
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P7.0/KS4
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P6.3/KS3
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P6.2/KS2
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P6.1/KS1
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P6.0/KS0
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P5.3
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P5.2
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P5.1
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P5.0
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P8.3
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P8.2
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P8.1
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P8.0
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P4.3
Figure 1-2. KS57C5204/C5208 Pin Assignment Diagram (42-SDIP)
1-4
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
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P7.3/KS7 |
P7.2/KS6 |
P7.1/KS5 |
P7.0/KS4 |
P6.3/KS3 |
P6.2/KS2 |
P6.1/KS1 |
P6.0/KS0 |
P5.3 |
P5.2 |
P5.1 |
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33 |
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DTMF |
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34 |
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22 |
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P5.0 |
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P9.0 |
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21 |
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P8.3 |
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P9.1 |
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20 |
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P8.2 |
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P9.2 |
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KS57C5204 |
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P8.1 |
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NC |
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P8.0 |
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/C5208 |
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P1.0/INT0 |
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17 |
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P4.3 |
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P1.1/INT1 |
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40 |
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(44-QFP-1010B) |
16 |
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NC |
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P1.2/INT2 |
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15 |
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P4.2 |
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P1.3/INT4 |
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14 |
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P3.3 |
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P2.0/TCLO0 |
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P3.2 |
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P2.1/TCLO1 |
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1 2 3 4 5 6 7 8 9 10 11 |
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RESET |
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P2.2/CLO |
P2.3/BUZ |
P3.0/TCL0 |
P3.1/TCL1 |
VDD |
VSS |
XOUT |
XIN |
TEST |
P4.0/BTCO |
P4.1 |
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Figure 1-3. KS57C5204/C5208 Pin Assignment Diagram (44-QFP)
1-5
PRODUCT OVERVIEW |
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 |
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VSS 
1
XOUT 
2
XIN 
3 TEST 
4 P4.0/BTCO 
5 P4.1 
6
RESET 
7 P4.2 
8 P4.3 
9 P5.0 
10 P5.1 
11 P5.2 
12 P5.3 
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P6.0/KS0 
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P6.1/KS1 
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KS57C5304/C5308/C5312 400)-SDIP-(30
30 
VDD
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P3.1/TCL1
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P3.0/TCL0
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P2.3/BUZ
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P2.2/CLO
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P2.1/TCLO1
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P2.0/TCLO0
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P1.0/INT0
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DTMF
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P7.3/KS7
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P7.2/KS6
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P7.1/KS5
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P7.0/KS4
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P6.3/KS3
16 
P6.2/KS2
Figure 1-4. KS57C5304/C5308/C5312 Pin Assignment Diagram (30-SDIP)
VSS |
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XOUT |
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XIN |
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TEST |
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P4.0/BTCO |
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P4.1 |
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RESET |
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P4.2 |
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NC |
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P4.3 |
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P5.0 |
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P5.1 |
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P5.2 |
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P5.3 |
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P6.0/KS0 |
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P6.1/KS1 |
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KS57C5304/C5308/C5312 450A)-SOP-(32
32 
VDD
31 
P3.1/TCL1
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P3.0/TCL0
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P2.3/BUZ
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P2.2/CLO
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P2.1/TCLO1
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P2.0/TCLO0
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P1.0/INT0
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NC
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DTMF
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P7.3/KS7
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P7.2/KS6
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P7.1/KS5
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P7.0/KS4
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P6.3/KS3
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P6.2/KS2
Figure 1-5. KS57C5304/C5308/C5312 Pin Assignment Diagram (32-SOP)
1-6
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. KS57C5204/C5208 Pin Descriptions
Pin |
Pin |
Reset |
Description |
Pin |
Share |
Circuit |
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Name |
Type |
Value |
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Number |
Pin |
Type |
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P1.0 |
I |
I |
4-bit input port. |
1 (39) |
INT0 |
A-4 |
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P1.1 |
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1-bit and 4-bit read and test is possible. |
2 (40) |
INT1 |
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P1.2 |
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Each pull-up resistors are assignable by software. |
3 (41) |
INT2 |
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P1.3 |
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4 (42) |
INT4 |
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P2.0 |
I/O |
I |
4-bit I/O port. |
5 (43) |
TCLO0 |
D-2 |
|
P2.1 |
|
|
1-bit and 4-bit read/write and test is possible. |
6 (44) |
TCLO1 |
|
|
P2.2 |
|
|
Individual pins are software configurable as input or |
7 |
(1) |
CLO |
|
P2.3 |
|
|
output. |
8 |
(2) |
BUZ |
|
|
|
|
|
|
|
|
|
P3.0 |
|
|
4-bit pull-up resistors are software assignable to input |
9 |
(3) |
TCL0 |
D-4 |
P3.1 |
|
|
pins and are automatically disabled for output pins. |
10 (4) |
TCL1 |
|
|
P3.2 |
|
|
Ports 2 and 3 can be paired to enable 8-bit data |
19 |
(13) |
|
|
P3.3 |
|
|
transfer. |
20 |
(14) |
|
|
|
|
|
|
|
|
|
|
P4.0 |
I/O |
I |
4-bit I/O ports. |
16 |
(10) |
BTCO |
E-2 |
P4.1 |
|
|
1-bit and 4-bit read/write and test is possible. |
17 |
(11) |
|
|
P4.2 |
|
|
Individual pins are software configurable as input or |
21 |
(15) |
|
|
P4.3 |
|
|
output. |
22 |
(17) |
|
|
|
|
|
4-bit pull-up resistors are software assignable to input |
|
|
|
|
P5.0-P5.3 |
|
|
pins and are automatically disabled for output pins. |
27-30 |
|
|
|
|
|
|
N-channel open-drain or push-pull output can be |
(22-25) |
|
|
|
|
|
|
selected by software (1-bit unit) |
|
|
|
|
|
|
|
Ports 4 and 5 can be paired to support 8-bit data |
|
|
|
|
|
|
|
transfer. |
|
|
|
|
|
|
|
|
|
|
|
|
P6.0-P6.3 |
I/O |
I |
4-bit I/O ports. |
31-34 |
KS0-KS3 |
D-4 |
|
|
|
|
1-bit or 4-bit read/write and test is possible. |
(26-29) |
|
|
|
P7.0-P7.3 |
|
|
Individual pins are software configurable as input or |
35-38 |
KS4-KS7 |
|
|
|
|
|
output. |
(30-33) |
|
|
|
|
|
|
4-bit pull-up resistors are software assignable to input |
|
|
|
|
|
|
|
pins and are automatically disabled for output pins. |
|
|
|
|
|
|
|
Ports 6 and 7 can be paired to enable 8-bit data |
|
|
|
|
|
|
|
transfer. |
|
|
|
|
|
|
|
|
|
|
|
|
P8.0-P8.3 |
I/O |
I |
4-bit I/O port. |
23-26 |
– |
D-2 |
|
|
|
|
1-bit or 4-bit read/write and test is possible. |
(18-21) |
|
|
|
P9.0-P9.2 |
|
|
Individual pins are software configurable as input or |
40-42 |
|
|
|
|
|
|
output. |
(35-37) |
|
|
|
|
|
|
4-bit pull-up resistors are software assignable to input |
|
|
|
|
|
|
|
pins and are automatically disabled for output pins. |
|
|
|
|
|
|
|
Ports 8 and 9 can be paired to enable 8-bit data |
|
|
|
|
|
|
|
transfer. |
|
|
|
|
|
|
|
|
|
|
|
|
1-7
PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 1-1. KS57C5204/C5208 Pin Descriptions (Continued)
Pin Name |
Pin |
Reset |
Description |
Pin |
Share |
Circu |
|
Type |
Value |
|
Number |
Pin |
it |
|
|
|
|
|
|
Type |
|
|
|
|
|
|
|
DTMF |
O |
– |
DTMF output. |
39 (34) |
– |
G-6 |
|
|
|
|
|
|
|
BTCO |
I/O |
I |
Basic timer clock output |
16 (10) |
P4.0 |
E-2 |
|
|
|
|
|
|
|
INT0 |
I |
I |
External interrupts. The triggering edge for INT0 and |
1 (39) |
P1.0 |
A-4 |
INT1 |
|
|
INT1 is selectable. |
2 (40) |
P1.1 |
|
|
|
|
|
|
|
|
INT2 |
I |
I |
Quasi-interrupt with detection of rising edges |
3 (41) |
P1.2 |
A-4 |
|
|
|
|
|
|
|
INT4 |
I |
I |
External interrupt with detection of rising and falling |
4 (42) |
P1.3 |
A-4 |
|
|
|
edges. |
|
|
|
|
|
|
|
|
|
|
TCLO0 |
I/O |
I |
Timer/counter 0 clock output |
5 (43) |
P2.0 |
D-2 |
|
|
|
|
|
|
|
TCLO1 |
I/O |
I |
Timer/counter 1 clock output |
6 (44) |
P2.1 |
D-2 |
|
|
|
|
|
|
|
CLO |
I/O |
I |
Clock output |
7 (1) |
P2.2 |
D-2 |
|
|
|
|
|
|
|
BUZ |
I/O |
I |
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the |
8 (2) |
P2.3 |
D-2 |
|
|
|
watch timer clock frequency of 4.19 MHz for buzzer |
|
|
|
|
|
|
sound |
|
|
|
|
|
|
|
|
|
|
TCL0 |
I/O |
I |
External clock input for timer/counter 0 |
9 (3) |
P3.0 |
D-4 |
|
|
|
|
|
|
|
TCL1 |
I/O |
I |
External clock input for timer/counter 1 |
10 (4) |
P3.1 |
D-4 |
|
|
|
|
|
|
|
KS0-KS3 |
I/O |
I |
Quasi-interrupt inputs with falling edge detection |
31-34 |
P6.0-P6.3 |
D-4 |
|
|
|
|
(26-29) |
P7.0-P7.3 |
|
KS4-KS7 |
|
|
|
35-38 |
|
|
|
|
|
|
(30-33) |
|
|
|
|
|
|
|
|
|
VDD |
– |
– |
Power supply |
11 (5) |
– |
– |
VSS |
– |
– |
Ground |
12 (6) |
– |
– |
RESET |
– |
– |
RESET signal |
18 (12) |
– |
B |
|
|
|
|
|
|
|
XIN |
– |
– |
Crystal, or ceramic oscillator signal for main system |
14 (8) |
– |
– |
X |
|
|
clock. (For external clock input, use XIN and input XIN's |
13 (7) |
|
|
OUT |
|
|
reverse phase to XOUT) |
|
|
|
|
|
|
|
|
|
|
TEST |
– |
– |
Chip test input pin, Hold GND when the device is |
15 (9) |
– |
– |
|
|
|
operating. |
|
|
|
|
|
|
|
|
|
|
NC |
– |
– |
No connection |
(16, 38) |
– |
– |
|
|
|
|
|
|
|
NOTE: Parentheses indicate pin number for 44 QFP package.
1-8
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
Table 1-2. KS57C5304/C5308/C5312 Pin Descriptions
Pin |
Pin |
Description |
Pin |
Share |
Circuit |
|
Name |
Type |
|
Number |
Pin |
Type |
|
|
|
|
|
|
|
|
P1.0 |
I |
1-bit input port. |
23 |
(25) |
INT0 |
A-4 |
|
|
1-bit and 4-bit read and test is possible. |
|
|
|
|
|
|
Each bit pull-up resistors are assignable. |
|
|
|
|
|
|
|
|
|
|
|
P2.0 |
I/O |
4-bit I/O port. |
24 |
(26) |
TCLO0 |
D-2 |
P2.1 |
|
1-bit and 4-bit read/write and test is possible. |
25 |
(27) |
TCLO1 |
|
P2.2 |
|
Each individual pin can be assignable as input or |
26 |
(28) |
CLO |
|
P2.3 |
|
output. 4-bit pull-up resisters are software assignable to |
27 |
(29) |
BUZ |
|
|
|
input pins and are automatically disabled for output |
|
|
|
|
|
|
pins. |
|
|
|
|
P3.0 |
|
Ports 2 and 3 can be paired to enable 8-bit data |
28 |
(30) |
TCL0 |
D-4 |
P3.1 |
|
transfer. |
29 |
(31) |
TCL1 |
|
|
|
|
|
|
|
|
P4.0 |
I/O |
4-bit I/O ports. |
5 |
(5) |
BTCO |
E-2 |
P4.1 |
|
1-bit and 4-bit read/write and test is possible. |
6 |
(6) |
|
|
P4.2 |
|
Each individual pin can be assignable as input or |
8 |
(8) |
|
|
P4.3 |
|
output. 4-bit pull-up resisters are software assignable to |
9 (10) |
|
|
|
P5.0-P5.3 |
|
input pins and are automatically disabled for output |
10-13 |
|
|
|
|
|
pins. |
(11-14) |
|
|
|
|
|
The N-channel open-drain or push-pull output can be |
|
|
|
|
|
|
selected by software (1-bit unit). |
|
|
|
|
|
|
Ports 4 and 5 can be paired to enable 8-bit data |
|
|
|
|
|
|
transfer. |
|
|
|
|
|
|
|
|
|
|
|
P6.0-P6.3 |
I/O |
4-bit I/O ports. |
14-17 |
KS0-KS3 |
D-4 |
|
|
|
1-bit and 4-bit read/write and test is possible. |
(15-18) |
|
|
|
P7.0-P7.3 |
|
Each individual pin can be assignable as input or |
18-21 |
KS4-KS7 |
|
|
|
output. 4-bit pull-up resisters are software assignable to |
(19-22) |
|
|
||
|
|
|
|
|||
|
|
input pins and are automatically disabled for output |
|
|
|
|
|
|
pins. |
|
|
|
|
|
|
Ports 6 and 7 can be paired to enable 8-bit data |
|
|
|
|
|
|
transfer. |
|
|
|
|
|
|
|
|
|
|
|
1-9
PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 1-2. KS57C5304/C5308/C5312 Pin Descriptions (Continued)
Pin Name |
I/O |
Description |
Pin |
Share |
Circuit |
|
|
Type |
|
Number |
Pin |
Type |
|
|
|
|
|
|
|
|
DTMF |
O |
DTMF output. |
22 |
(23) |
– |
G-6 |
|
|
|
|
|
|
|
INT0 |
I |
External interrupt input. |
23 |
(25) |
P1.0 |
A-3 |
|
|
The triggering edge for INT0 is selectable. |
|
|
|
|
|
|
|
|
|
|
|
TCLO0 |
I/O |
Timer/counter 0 clock output |
24 |
(26) |
P2.0 |
D-2 |
|
|
|
|
|
|
|
TCLO1 |
I/O |
Timer/counter 1 clock output |
25 |
(27) |
P2.1 |
D-2 |
|
|
|
|
|
|
|
CLO |
I/O |
Clock output |
26 |
(28) |
P2.2 |
D-2 |
|
|
|
|
|
|
|
BUZ |
I/O |
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the |
27 |
(29) |
P2.3 |
D-2 |
|
|
watch timer clock frequency of 4.19 MHz for buzzer |
|
|
|
|
|
|
sound |
|
|
|
|
|
|
|
|
|
|
|
TCL0 |
I/O |
External clock input for timer/counter 0 |
28 |
(30) |
P3.0 |
D-4 |
|
|
|
|
|
|
|
TCL1 |
I/O |
External clock input for timer/counter 1 |
29 |
(31) |
P3.1 |
D-4 |
|
|
|
|
|
|
|
BTCO |
I/O |
Basic timer clock output |
5 |
(5) |
P4.0 |
E-2 |
|
|
|
|
|
|
|
VDD |
– |
Power supply |
30 |
(32) |
– |
– |
VSS |
– |
Ground |
1 |
(1) |
– |
– |
XIN |
– |
Crystal, or ceramic oscillator signal for main system |
3 |
(3) |
– |
– |
X |
|
clock. (For external clock input, use XIN and input XIN's |
2 |
(2) |
|
|
OUT |
|
reverse phase to XOUT) |
|
|
|
|
|
|
|
|
|
|
|
NC |
– |
No connection |
(9, 24) |
– |
– |
|
|
|
|
|
|
|
|
TEST |
– |
Chip test input pin, Hold GND when the device is |
4 |
(4) |
– |
– |
|
|
operating. |
|
|
|
|
|
|
|
|
|
|
|
RESET |
– |
RESET signal |
7 |
(7) |
– |
B |
|
|
|
|
|
|
|
KS0-KS3 |
I/O |
Quasi-interrupt inputs with falling edge detection |
14-17 |
P6.0-P6.3 |
D-4 |
|
|
|
|
(15-18) |
P7.0-P7.3 |
|
|
KS4-KS7 |
|
|
18-21 |
|
|
|
|
|
|
(19-22) |
|
|
|
|
|
|
|
|
|
|
NOTE: Parentheses indicate the pin number for 32-SOP package. |
|
|
|
|
||
1-10
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
P-Channel
In 
N-Channel
Figure 1-6. Pin Circuit Type A
VDD
|
Pull-Up |
|
|
Resistor |
|
P-Channel |
Resistor |
|
Enable |
||
|
||
In |
|
Schmitt Trigger
Figure 1-7. Pin Circuit Type A-4
VDD
Pull-Up
Resistor
In
Schmitt Trigger
Figure 1-8. Pin Circuit Type B
|
VDD |
Data |
P-Channel |
|
|
|
Out |
Output |
N-Channel |
DIsable |
|
Figure 1-9. Pin Circuit Type C
1-11
PRODUCT OVERVIEW |
|
|
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 |
||
|
|
VDD |
|
|
VDD |
|
|
|
|
|
|
|
|
Pull-up |
PNE |
Pull-up |
|
|
|
Resistor |
|
VDD |
Resistor |
Pull-up |
|
P-Channel |
|
|
|
Enable |
|
|
|
Pull-up |
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
Resistor |
Data |
Circuit |
|
Data |
P-Channel |
Enable |
|
I/O |
|
I/O |
||
|
|
|
|||
Output |
Type C |
|
|
||
|
|
|
|
||
|
|
|
|
|
|
DIsable |
|
|
Output |
|
|
|
|
|
N-Channel |
|
|
|
|
|
Disable |
|
|
|
|
|
|
|
|
Figure 1-10. Pin Circuit Type D-2 |
|
Figure 1-12. Pin Circuit Type E-2 |
|||
|
|
VDD |
|
|
|
Pull-up |
|
|
|
Resistor |
|
Pull-up |
|
P-Channel |
|
Enable |
|
||
|
|
||
Data |
Circuit |
DTMF Out |
|
|
I/O |
||
Output |
Type C |
||
|
|||
|
|
||
Disable |
|
Output |
|
|
|
Disable |
|
|
Schmitt Trigger |
|
Figure 1-11. Pin Circuit Type D-4 |
Figure 1-13. Pin Circuit Type G-6 |
|
1-12
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