Samsung KM681002BTI-8, KM681002BTI-12, KM681002BTI-10, KM681002BT-8, KM681002BT-12 Datasheet

KM681002B, KM681002BI	CMOS SRAM

Document Title

128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature Range.

Revision History

RevNo.	History
Rev. 0.0	Initial release with Design Target.
Rev.1.0	Release to Preliminary Data Sheet.
	1. Replace Design Target to Preliminary.
Rev.2.0	Release to Final Data Sheet.
	2.1. Delete Preliminary
	2.2. Delete 32-SOJ-300 package
	2.3. Delete L-version.
	2.4. Delete Data Retention Characteristics and Waveform.
	2.5. Add Capacitive load of the test environment in A.C test load
	2.6. Change D.C characteristics
	Items	Previous spec.	Changed spec.
		(8/10/12ns part)	(8/10/12ns part)
	Icc	160/150/140mA	160/155/150mA
	Isb	30mA	50mA

Draft Data

Apr. 1st, 1997

Jun. 1st, 1997

Feb. 25th, 1998

Remark

Design Target

Preliminary

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquart ers.

	- 1 -	Rev 2.0
		February 1998

KM681002B, KM681002BI					CMOS SRAM
128K x 8 Bit High-Speed CMOS Static RAM
FEATURES		GENERAL DESCRIPTION
•	Fast Access Time 8,10,12ns(Max.)		The KM681002B is a 1,048,576-bit high-speed Static Random
•	Low Power Dissipation		Access Memory organized as 131,072 words by 8 bits. The
	Standby (TTL) : 50 mA(Max.)		KM681002B uses 8 common input and output lines and has an
	(CMOS) : 10 mA(Max.)		output enable pin which operates faster than address access
	Operating KM681002B - 8 : 160 mA(Max.)		time at read cycle. The device is fabricated using Samsung ′s
	KM681002B - 10 : 155 mA(Max.)		advanced CMOS process and designed for high-speed circuit
	KM681002B - 12 : 150 mA(Max.)		technology. It is particularly well suited for use in high-density
• Single 5.0V ±10% Power Supply			high-speed system applications. The KM681002B is packaged
•	TTL Compatible Inputs and Outputs		in a 400mil 32-pin plastic SOJ or TSOP2 forward.
•	I/O Compatible with 3.3V Device
•	Fully Static Operation
	- No Clock or Refresh required	ORDERING INFORMATION
•	Three State Outputs
•	Center Power/Ground Pin Configuration
			KM681002B -8/10/12		Commercial Temp.
•	Standard Pin Configuration
			KM681002BI -8/10/12		Industrial Temp.
	KM681002BJ : 32-SOJ-400
	KM681002BT: 32-TSOP2-400F

PIN CONFIGURATION (Top View)

			A0	1		32	A16
FUNCTIONAL BLOCK DIAGRAM			A1	2		31	A15
			A2	3		30	A14
			A3	4		29	A13
	Clk Gen.	Pre-Charge Circuit	CS	5		28	OE
			I/O1	6		27	I/O8
A0			I/O2	7		26	I/O7
			Vcc	8		25	Vss
A1					SOJ/
			Vss	9		24	Vcc
A2	Select				TSOP2
		Memory Array
A3			I/O3	10		23	I/O6
A4	Row	256 Rows	I/O4	11		22	I/O5
		512x8 Columns
A5
			WE	12		21	A12
A6
			A4	13		20	A11
A7
			A5	14		19	A10
	Data	I/O Circuit	A6	15		18	A9
I/O1~I/O8
	Cont.	Column Select	A7	16		17	A8
	CLK
	Gen.		PIN FUNCTION
	A8	A9 A10 A11 A12 A13 A14 A15 A16	Pin Name		Pin Function
			A0 - A16		Address Inputs
CS			WE		Write Enable
WE			CS		Chip Select
OE			OE		Output Enable
			I/O1 ~ I/O8		Data Inputs/Outputs
			VCC		Power(+5.0V)
			VSS		Ground
			N.C		No Connection

- 2 -

Rev 2.0

February 1998

KM681002B, KM681002BI				CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter		Symbol	Rating		Unit
Voltage on Any Pin Relative to V SS		VIN, VOUT	-0.5 to 7.0		V
Voltage on VCC Supply Relative to V SS		VCC	-0.5 to 7.0		V
Power Dissipation		PD	1.0		W
Storage Temperature		TSTG	-65 to 150		°C
Operating Temperature	Commercial	TA	0 to 70		°C
	Industrial	TA	-40 to 85		°C

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this spec ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (TA=0 to 70°C)

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage	VCC	4.5	5.0	5.5	V
Ground	VSS	0	0	0	V
Input High Voltage	VIH	2.2	-	VCC + 0.5**	V
Input Low Voltage	VIL	-0.5*	-	0.8	V

NOTE: The above parameters are also guaranteed at industrial temperature range.

*VIL(Min) = -2.0V a.c(Pulse Width≤6ns) for I≤20mA

**VIH(Max) = VCC + 2.0V a.c (Pulse Width≤6ns) for I≤20mA

DC AND OPERATING CHARACTERISTICS (TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Max

Unit

Input Leakage Current

ILI

VIN = VSS to VCC

-2

2

mA

Output Leakage Current

ILO

-2

2

mA

CS=VIH or OE=VIH or WE=VIL

VOUT=VSS to VCC

Operating Current

ICC

Min. Cycle, 100% Duty

8ns

-

160

mA

CS=VIL, VIN=VIH or VIL,

10ns

-

155

IOUT=0mA

12ns

-

150

Standby Current

ISB

Min. Cycle,

-

50

mA

CS=VIH

ISB1

f=0MHz,

³VCC-0.2V,

-

10

mA

CS

VIN³VCC-0.2V or VIN£0.2V

Output Low Voltage Level

VOL

IOL=8mA

-

0.4

V

Output High Voltage Level

VOH

IOH=-4mA

2.4

-

V

VOH1*

IOH1=-0.1mA

-

3.95

V

NOTE: The above parameters are also guaranteed at industrial temperature range. * VCC=5.0V, Temp.=25°C

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item	Symbol	Test Conditions	MIN	Max	Unit
Input/Output Capacitance	CI/O	VI/O=0V	-	8	pF
Input Capacitance	CIN	VIN=0V	-	6	pF

* NOTE : Capacitance is sampled and not 100% tested.

- 3 -

Rev 2.0

February 1998