Samsung KM48L16031BT-G0, KM48L16031BT-FZ, KM48L16031BT-FY, KM48L16031BT-F0, KM44L32031BT-FZ Datasheet

128Mb DDR SDRAM		Target

DDR SDRAM Specification

Version 0.61

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REV. 0.61 August 9. '99

128Mb DDR SDRAM		Target

Revision History

Version 0 (May, 1998)

-First version for internal review

Version 0.1(June, 1998)

-Added x4 organization

Version 0.2(Sep,1998)

1. Added "Issue prcharge command for all banks of the device" as the fourth step of power-up squence. 2. In power down mode timing diagram, NOP condition is added to precharge power down exit.

Version 0.3(Dec,1998)

-Added QFC Function.

-Added DC current value

-Reduce I/O capacitance values

Version 0.4(Feb,1999)

-Added DDR SDRAM history for reference(refer to the following page) -Added low power version DC spec

Version 0.5(Apr,1999)

-Revised following first showing for JEDEC standard -Added DC target current based on new DC test condition

Version 0.6(July 1,1999)

1.Modified binning policy

From To

-Z (133Mhz) -Z (133Mhz/266Mbps@CL=2) -8 (125Mhz) -Y (133Mhz/266Mbps@CL=2.5) -0 (100Mhz) -0 (100Mhz/200Mbps@CL=2)

2.Modified the following AC spec values

	From.				To.
	-Z		-0	-Z	-Y	-0
tAC	+/- 0.75ns		+/- 1ns	+/- 0.75ns	+/- 0.75ns	+/- 0.8ns
tDQSCK	+/- 0.75ns		+/- 1ns	+/- 0.75ns	+/- 0.75ns	+/- 0.8ns
tDQSQ	+/- 0.5ns		+/- 0.75ns	+/- 0.5ns	+/- 0.5ns	+/- 0.6ns
tDS/tDH	0.5 ns		0.75 ns	0.5 ns	0.5 ns	0.6 ns
tCDLR*1	2.5tCK-tDQSS		2.5tCK-tDQSS	1tCK	1tCK	1tCK
tPRE*1	1tCK +/- 0.75ns		1tCK +/- 1ns	0.9/1.1 tCK	0.9/1.1 tCK	0.9/1.1 tCK
tRPST*1	tCK/2 +/- 0.75ns		tCK/2 +/- 1ns	0.4/0.6 tCK	0.4/0.6 tCK	0.4/0.6 tCK
tHZQ*1	tCK/2 +/- 0.75ns		tCK/2 +/- 1ns	+/- 0.75ns	+/- 0.75ns	+/-0.8ns

*1 : Changed description method for the same functionality. This means no difference from the previous version.

3.Changed the following AC parameter symbol
			From.	To.
Output data access time from CK/CK			tDQCK	tAC

Version 0.61(August 9,1999)

- Changed the some values of "write with auto precharge" table for different bank in page 30.

Asserted			For Different Bank
command
	3				4
	Old		New	Old		New
Read	Legal		Illegal	Legal		Illegal
Read + AP*1	Legal		Illegal	Legal		Illegal

- 2 of 63 - REV. 0.61 August 9. '99

128Mb DDR SDRAM		Target

Revision History

-This revision history is for 64Mb and only for reference in other density.

Version 0.5 (JUN, 1997)

-First version for external release

-Center aligned DQ on reads and writes, 3.3V Vdd/Vddq, LVTTL for command and SSTL for DQ, DQS, CK and DM.

Version 0.6 (SEP. 1997)

-Changed to Edge alignedDQ on reads

-Add detailed discription for each functionality

Version 0.7 (JAN. 1998)

- Power supply: 3.3V +10%,-5% power supply for device operation (Vdd) 2.5V Power supply for I/O interface (Vddq)

-Interface: Add SSTL_2 for CK/DM (class I), DQ/DQS(class II) for KM416H431T.

*Put two part numbers, KM416H430T and KM416H431T.

-Clock input: Change to differential clock from single ended clock.

*Use CK, CK instead of CLK.

-Package: Change to 66pin TSOP-II, instead of 54pin TSOP-II

-tDQSS: Change to 0.75 ~ 1.25 tCK form 3ns ~ 1 tCK.

Add tSDQS(DQS-in setup time)

- In page 13, "DM can be ~" is modified to "DM must be ~".

- Tighten AC specs Change CK/CK hign/low level width from 0.4(min)/0.6(max)tCK to 0.45(min)/0.55(max)tCK. -> Better input clock duty ratio from differential clock.

Version 0.8 (FEB. 1998)

- Correct pin rotation on pin 48 and 49 from 48-Vref, 49-Vss to 48-Vss, 49-Vref.

Version 0.9 (MAR. 1998)

-Change power-up sequence

. Add EMRS for DLL enable/disable

. Change DLL reset pin from A9 to A8 on MRS.

-Change speed range

. Add 133Mhz (266Mbps/pin), remove -12 (83Mhz)

-Change output load circuit

-Change input capacitance

-Add a comment on read interrupting write timing: Read command interrupting write can not be issued at the next clock edge of write command.

-Modify the simplified state diagram on page 24.

Version 0.91 (May, 1998)

-Changed part number from KM416H430T/KM416H431T to KM416H4030T/KM416H4031T

-Added the 66pin package dimension on page 30.

-Changed Output Load Circuit 2 in page 29

-Removed CL=1.5

-Corrected typos

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REV. 0.61 August 9. '99

128Mb DDR SDRAM		Target
	Contents
	Revision History	2
	DDR SDRAM Ordering Information	8
	1. Key Features	9
	1.1 Features	9
	1.2 Operating Frequencies	9
	1.3 Device Information by organization	9
	2. Package Pinout & Dimension	10
	2.1 Package Pintout	10
	2.2 Input/Output Function Description	11
	2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension	12
	3. Functional Description	13
	3.1 Simplified State Diagram	13
	3.2 Basic Functionality	14
	3.2.1 Power-Up Sequence	14
	3.2.2 Mode Register Definition	15
	3.2.2.1 Mode Register Set(MRS)	15
	3.2.2.2 Extended Mode Register Set(EMRS)	17
	3.2.3 Precharge	18
	3.2.4 No Operation(NOP) & Device Deselect	18
	3.2.5 Row Active	19
	3.2.6 Read Bank	19
	3.2.7 Write Bank	19
	3.3 Essential Functionality for DDR SDRAM	20
	3.3.1 Burst Read Operation	20
	3.3.2 Burst Write Operation	21
	3.3.3 Read Interrupted by a Read	22
	3.3.4 Read Interrupted by a Write & Burst Stop	22
	3.3.5 Read Interrupted by a Precharge	23
	3.3.6 Write Interrupted by a Write	24

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			3.3.7 Write Interrupted by a Read & DM			25
			3.3.8 Write Interrupted by a Precharge & DM			26
			3.3.9 Burst Stop			27
		3.3.10 DM masking				28
		3.3.11 Read With Auto Precharge				29
		3.3.12 Write With Auto Precharge				30
		3.3.13 Auto Refresh & Self Refresh				31
		3.3.14 Power Down				32
	4. Command Truth Table					33
	5. Functional Truth Table					34
	6. Absolute Maximum Rating					39
	7. DC Operating Conditions & Specifications					39
	7.1 DC Operating Conditions					39
	7.2 DC Specifications					40
	8. AC Operating Conditions & Timming Specification					41
	8.1 AC Operating Conditions					41
	8.2 AC Timming Parameters & Specification					42
	9. AC Operating Test Conditions					44
	10. Input/Output Capacitance					44
	11. IBIS: I/V Characteristics for Input and Output Buffers					45
	11.1 Normal strength driver					45
	11.2 Half strength driver( will be included in the future)					47
	12. QFC function					48
						48
			QFC definition
						48
			QFC timming on Read Operation
						49
			QFC timming on Write operation with tDQSSmax
						49
			QFC timming on Write operation with tDQSSmin

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128Mb DDR SDRAM		Target
	List of tables
	Table 1 : Operating frequency and DLL jitter	9
	Table 2. : Column address configurtion	10
	Table 3 : Input/Output function description	11
	Table 4 : Burst address ordering for burst length	16
	Table 5 : Bank selection for precharge by bank address bits	18
	Table 6 : Operating description when new command asserted while	29
	read with auto precharge is issued
	Table 7 : Operating description when new command asserted while	30
	write with auto precharge is issued
	Table 8 : Command truth table	33
	Table 9-1 : Functional truth table	34
	Table 9-2 : Functional truth table (contiued)	35
	Table 9-3 : Functional truth table (contiued)	36
	Table 9-4 : Functional truth table (contiued)	37
	Table 9-5 : Functional truth table (cotinued)	38
	Table 10 : Absolute maximum raings	39
	Table 11 : DC operating condtion	39
	Table 12 : DC specification	40
	Table 13 : AC operating condition	41
	Table 14 : AC timing parameters and specifications	42
	Table 15 : AC operating test conditions	44
	Table 16 : Input/Output capacitance	44
	Table 17 : Pull down and pull up current values	46

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128Mb DDR SDRAM				Target
	List of figures
	Figure 1 : 128Mb Package Pinout			10
	Figure 2 : Package dimension			12
	Figure 3 :State digram			13
	Figure 4 : Power up and initialization sequence			14
	Figure 5 : Mode register set			15
	Figure 6 : Mode register set sequence			16
	Figure 7 : Extend mode register set			17
	Figure 8 : Bank activation command cycle timing			19
	Figure 9 : Burst read operation timing			20
	Figure 10 : Burst write operation timing			21
	Figure 11 : Read interrupted by a read timing			22
	Figure 12 : Read interrupted by a write and burst stop timing			22
	Figure 13 : Read interrupted by a precharge timing			23
	Figure 14 : Write interrupted by a write timing			24
	Figure 15 : Write interrupted by a read and DM timing			25
	Figure 16 : Write interrupted by a precharge and DM timing			26
	Figure 17 : Burst stop timing			27
	Figure 18 : DM masking timing			28
	Figure 19 : Read with auto precharge timing			29
	Figure 20 : Write with auto precharge timing			30
	Figure 21 : Auto refresh timing			31
	Figure 22 : Self refresh timing			31
	Figure 23 : Power down entry and exit timing			32
	Figure 24 : Output Load Circuit (SSTL_2)			44
	Figure 25 : I / V characteristics for input/output buffers:			45
		pull-up(above) and pull-down(below)
	Figure 26 : QFC timing on read operation			48
	Figure 27 : QFC timing on write operation with tDQSSmax			49
	Figure 28 : QFC timing on write operation with tDQSSmin			49

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128Mb DDR SDRAM

Target

DDR SDRAM ORDERING INFORMATION

KM 4 XX L XX X X X X X - X X

1. SAMSUNG Memory

12. Speed

2. Device

11. Power

3. Organization

10. Package Type

4. Product & Voltage(VDD)

9. Revision

5. Depth

8. Interface & Voltage(VDDQ)

6. Refresh

7. Number of Bank

1. SAMSUNG Memory

7. Number of Bank

2. Device

• 3

4 Banks

• 4

DRAM

• 4

8 Banks

3. Organization

•

4

x4

8. Interface & Voltage(VDDQ)

•

8

x8

• 0

Mixed Interface(LVTTL & SSTL_3 & 3.3V VDDQ)

• 16

x16

• 1

SSTL_2(2.5V VDDQ)

• 32

x32

4. Product & Voltage(VDD)

9. Revision

• H

DDR SDRAM(3.3V VDD)

• Blank

1st Gen.

• L

DDR SDRAM(2.5V VDD)

• A

2nd Gen.

5. Depth

• B

3rd Gen.

•

4

4M

• C

4th Gen.

•

8

8M

•

16

16M

10. Package Type

•

32

32M

• T

66pin TSOP-II

•

64

64M

• B

BGA

•

12

128M

• C

u - BGA(CSP)

•

25

256M

11. Power

•

51

512M

• G

Auto & Self Refresh

•

1G

1G

• F

Auto & Self Refresh with Low Power

•

2G

2G

•

4G

4G

12. Speed

6. Refresh

•

Z

7.5ns, 133MHz@CL2 (266Mbps/pin)

• 0

64m/4K(15.6us)

•

Y

7.5ns, 133MHz@CL2.5(266Mbps/pin)

• 1

32m/2K(15.6us)

•

0

10ns, 100MHz @CL2(200Mbps/pin)

• 2

128m/8K(15.6us)

• 3

64m/8K(7.8us)

• 4

128m/16K(7.8us)

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1. Key Features

1.1 Features

•Double-data-rate architecture; two data transfers per clock cycle

•Bidirectional data strobe(DQS)

•Four banks operation

•Differential clock inputs(CK and CK)

•DLL aligns DQ and DQS transition with CK transition

•MRS cycle with address key programs -. Read latency 2, 2.5 (clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

•All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

•Data I/O transactions on both edges of data strobe

•Edge aligned data output, center aligned data input

•LDM,UDM/DM for write masking only

•Auto & Self refresh

•15.6us refresh interval

•Maximum burst refresh cycle : 8

•66pin TSOP II package

1.2 Operating Frequencies

	Maximum Operation
	Frequency
	PC266A(-Z)		PC266B(-Y)	PC200(-0)
Speed	133MHz@CL2		133MHz@CL2.5	100MHz@CL2
DLL jitter	±0.75ns		±0.75ns	±0.8ns

*CL : Cas Latency

Table 1. Operating frequency and DLL jitter

1.3 Device information by Organization

	Density	Part No.	Operating Freq.	Interface	Package
		KM44L32031BT-G(F)Z/Y/0			66pin
	128Mb	KM48L16031BT-G(F)Z/Y/0	133/133/100MHz	SSTL_2
					TSOP II
		KM416L8031BT-G(F)Z/Y/0

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1.Package Pinout & Dimension

2.1Package Pinout

8Mb x 16

16Mb x 8

32Mb x 4

VDD

VDD

VDD

1

66

VSS

VSS

VSS

DQ0

2

65

NC

DQ7

DQ15

DQ0

NC

VDDQ

VDDQ

3

64

VSSQ

VSSQ

VSSQ

VDDQ

4

63

NC

NC

DQ14

DQ1

NC

NC

5

62

DQ3

DQ6

DQ13

DQ2

DQ1

DQ0

VSSQ

6

61

VDDQ

VDDQ

VDDQ

VSSQ

VSSQ

DQ3

NC

7

60

NC

NC

DQ12

NC

8

59

NC

DQ5

DQ11

DQ4

DQ2

NC

9

58

VSSQ

VSSQ

VSSQ

VDDQ

VDDQ

VDDQ

DQ5

10

57

NC

NC

DQ10

NC

NC

66 PIN TSOP(II)

DQ6

DQ3

11

56

DQ2

DQ4

DQ9

DQ1

(400mil x 875mil)

VSSQ

VSSQ

12

55

VDDQ

VDDQ

VDDQ

VSSQ

(0.65 mm PIN PITCH)

54

NC

NC

DQ8

DQ7

NC

NC

13

NC

Bank Address

53

NC

NC

NC

NC

NC

14

VDDQ

15

BA0-BA1

52

VSSQ

VSSQ

VSSQ

VDDQ

VDDQ

LDQS

NC

16

51

DQS

DQS

UDQS

NC

Row Address

50

NC

NC

NC

NC

NC

NC

17

A0-A11

49

VREF

VREF

VREF

VDD

VDD

VDD

18

48

VSS

VSS

VSS

QFC/NC

QFC/NC QFC/NC

19

Auto Precharge

LDM

NC

NC

20

47

DM

DM

UDM

A10

WE

WE

WE

21

46

CK

CK

CK

45

CK

CK

CK

CAS

CAS

CAS

22

23

44

CKE

CKE

CKE

RAS

RAS

RAS

43

NC

NC

NC

CS

CS

CS

24

NC

NC

NC

25

MS-024FC

42

NC

NC

NC

41

A11

A11

A11

BA0

BA0

BA0

26

BA1

40

A9

A9

A9

BA1

BA1

27

AP/A10

AP/A10

AP/A10

28

39

A8

A8

A8

38

A7

A7

A7

A0

A0

A0

29

37

A6

A6

A6

A1

A1

A1

30

A2

36

A5

A5

A5

A2

A2

31

A3

A3

35

A4

A4

A4

A3

32

VSS

VSS

VSS

VDD

VDD

VDD

33

34

FIgure 1. 128Mb package Pinout

Organization	Column Address
32Mx4	A0-A9, A11
16Mx8	A0-A9
8Mx16	A0-A8

DM is internally loaded to match DQ and DQS identically.

Table 2. Column address configuration

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2.2 Input/Output Function Description

SYMBOL

TYPE

DESCRIPTION

CK, CK

Input

Clock : CK and CK are differential clock inputs. All address and control input signals are sam-

pled on the positive edge of CK/negative edge of CK. Output (read) data is referenced to both

edges of CK. Internal clock signals are derived from CK/CK.

CKE

Input

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Deactivating the clock provides PRECHARGE

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN

(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,

which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled

during power-down and self refresh modes, providing low standby power. CKE will recognize

an LVCMOS LOW level prior to VREF being stable on power-up.

CS

Input

Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command

decoder. All commands are masked when CS is registered HIGH. CS provides for external

bank selection on systems with multiple banks CS is considered part of the command code.

RAS, CAS, WE

Input

Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.

LDM,(U)DM

Input

Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled on both

edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-

ing. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on

DQ8-DQ15.

BA0, BA1

Input

Bank Addres Inputs : BA0 and BA1 define to which bank ACTIVE, READ, WRITE or PRE-

CHARGE command is being applied.

A [n : 0]

Input

Address Inputs : Provide the row address for ACTIVE commands, the column address and

AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-

ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-

mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If

only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also

provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which

mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).

DQ

I/O

Data Input/Output : Data bus

LDQS,(U)DQS

I/O

Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on

DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.

QFC

Output

FET Control : Optional. Output during every Read and Write access. Can be used to control

isolation switches on modules.

NC

-

No Connect : No internal electrical connection is present.

VDDQ

Supply

DQ Power Supply : +2.5V ± 0.2V.

VSSQ

Supply

DQ Ground.

VDD

Supply

Power Supply : One of +3.3V ± 0.3V or +2.5V ± 0.2V (device specific).

VSS

Supply

Ground.

VREF

Input

SSTL_2 reference voltage.

Table 3. Input/Output Function Description

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128Mb DDR SDRAM		Target

2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension
												Units : Millimeters
			#66		#34			(0.80)											(0.50)
					0.10														(10.76)		0.20
	(1.50)				10.16±				(10× )										(10× )		11.76±
			#1		#33			(0.80)	0.125						+0.075-0.035				(0.50)
			(1.50)
0.665± 0.05 0.210± 0.05				22.22± 0.10		1.00± 0.10	1.20MAX													0.45~0.75
	(				(10× )							)							)
	R0.																		5
	1										×								.2
		5)							(	4									(R0
		)						0.10 MAX								2	5	)
															.				0.25TYP
	5		(0.71)	0.65TYP	0.30± 0.08									0
	.1					MIN							R
	0			0.65± 0.08			[	0.075 MAX ]				(
	(R				(10× )
						0.05
NOTE																			0× ~8×
1. (	) IS REFERENCE
2. [	] IS ASS’Y OUT QUALITY

Figure 2. Package dimension

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3.Functional Description

3.1Simplified State Diagram

						SELF
						REFRESH
					REFS
						REFSX
	MODE	MRS				REFA	AUTO
	REGISTER		IDLE
						REFRESH
	SET
						CKEL
	POWER			CKEH
			ACT
	DOWN					POWER
		CKEL				DOWN
		CKEH
			ROW
			ACTIVE			BURST STOP
		WRITE				READ
			WRITEA	READA
	WRITEA		READ			READ
	WRITEA					READA
				READA
			PRE
	WRITEA					READA
			PRE		PRE
POWER	POWER		PRE
APPLIED		PRE
	ON		CHARGE
							Automatic Sequence
							Command Sequence

WRITEA : Write with autoprecharge

READA : Read with autoprecharge

Figure 3. State diagram

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3.2Basic Functionality

3.2.1Power-Up and Initialization Sequence

The following sequence is required for POWER UP and Initialization.

1.Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.)

-Apply VDD before or at the same time as VDDQ.

-Apply VDDQ before or at the same time as VTT & Vref.

2.Start clock and maintain stable condition for a minimum of 200us.

3.The minimum of 200us after stable power and clock(CK, CK), apply NOP & take CKE high.

4.Issue precharge commands for all banks of the device.

*1	5. Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low"
	to all of the rest address pins, A1~A11 and BA1)
*1	6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required to
	lock the DLL.
*2	(To issue DLL reset command, provide "High" to A8 and "Low" to BA0)
	7. Issue precharge commands for all banks of the device.

8.Issue 2 or more auto-refresh commands.

9.Issue a mode register set command with low to A8 to initialize device operation.

*1 Every "DLL enable" command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6 & 7 is regardless of the order.

Power up & Initialization Sequence
0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
CK
CK
	tRP		2 Clock min.		2 Clock min.		tRP			tRFC				tRFC			2 Clock min.
Command
								1st Auto					2nd Auto				Mode		Any
precharge		EMRS		MRS		precharge
ALL Banks			DLL Reset			ALL Banks		Refresh					Refresh			Register Set		Command
											min.200 Cycle

Figure 4. Power up and initialization sequence

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3.2.2 Mode Register Definition

3.2.2.1 Mode Register Set(MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst lengths, addressing modes and CAS latencies.

			BA1		BA0			A11		A10				A9		A8					A7				A6					A5		A4						A3			A2			A1					A0				Address Bus
																																																					Mode Register
			RFU		0						RFU						DLL				TM					CAS Latency												BT			Burst Length
									A8			DLL Reset										A7					mode											A3			Burst Type
									0					No							0						Normal											0			Sequential
									1					Yes							1						Test											1			Interleave
																																								Burst Length
																		CAS Latency
																																									A2			A1					A0				Latency
																		A6				A5					A4				Latency																						Sequential		Interleave
																		0			0				0					Reserved										0			0						0				Reserve		Reserve
BA0						An ~ A0
																		0			0				1					Reserved										0			0						1			2			2
0				(Existing)MRS Cycle
																		0			1				0					2										0			1						0			4			4
1			Extended Funtions(EMRS)
																		0			1				1					Reserved										0			1						1			8			8
																		1			0				0					Reserved										1			0						0				Reserve		Reserve
* RFU(Reserved for future use)																		1			0				1					Reserved										1			0						1				Reserve		Reserve
should stay "0" during MRS																		1			1				0					2.5										1			1						0				Reserve		Reserve
cycle.
																		1			1				1					Reserved										1			1						1				Reserve		Reserve

Figure 5. Mode Register Set

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REV. 0.61 August 9. '99