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Preliminary |
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KM416S8030 |
CMOS SDRAM |
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2M x 16Bit x 4 Banks Synchronous DRAM |
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FEATURES |
GENERAL DESCRIPTION |
•JEDEC standard 3.3V power supply
•LVTTL compatible with multiplexed address
•Four banks operation
•MRS cycle with address key programs
-. CAS Latency (2 & 3)
-. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave)
•All inputs are sampled at the positive going edge of the system clock.
•Burst Read Single-bit Write operation
•DQM for masking
•Auto & self refresh
•64ms refresh period (4K cycle)
The KM416S8030 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clcok cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part NO. |
MAX Freq. |
Interface |
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KM416S8030T-G/F8 |
125MHz |
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KM416S8030T-G/FH |
100MHz |
LVTTL |
54pin |
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KM416S8030T-G/FL |
100MHz |
TSOP(II) |
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KM416S8030T-G/F10 |
100MHz |
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FUNCTIONAL BLOCK DIAGRAM
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Data Input Register |
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Bank Select |
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Address |
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CounterRefresh |
BufferRow |
DecoderRow |
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2M x 16 |
AMPSense |
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2M x 16 |
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2M x 16 |
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CLK |
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2M x 16 |
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Register |
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LRAS |
LCBR |
Buffer.Col |
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ADD |
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Column Decoder |
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Latency & Burst Length |
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LCKE |
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Programming Register |
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LRAS |
LCBR |
LWE |
LCAS |
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LWCBR |
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Timing Register |
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CLK |
CKE |
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CS |
RAS |
CAS |
WE |
LDQM |
UDQM |
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I/O |
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LWE |
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Control |
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LDQM |
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Output |
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DQi |
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Buffer |
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LDQM
*Samsung Electronics reserves the right to change products or specification without notice.
REV. 2 Mar. '98
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Preliminary |
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KM416S8030 |
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CMOS SDRAM |
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PIN CONFIGURATION (TOP VIEW) |
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VDD |
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1 |
54 |
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VSS |
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DQ0 |
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DQ15 |
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VDDQ |
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VSSQ |
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DQ1 |
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4 |
51 |
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DQ14 |
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DQ2 |
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DQ13 |
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VSSQ |
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VDDQ |
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DQ3 |
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DQ12 |
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DQ4 |
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DQ11 |
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VDDQ |
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VSSQ |
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DQ5 |
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10 |
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DQ10 |
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DQ6 |
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DQ9 |
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VSSQ |
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VDDQ |
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DQ7 |
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DQ8 |
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VDD |
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VSS |
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LDQM |
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N.C/RFU |
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WE |
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UDQM |
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CAS |
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CLK |
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RAS |
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CKE |
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CS |
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N.C |
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BA0 |
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A11 |
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BA1 |
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A9 |
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A10/AP |
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A8 |
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A0 |
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A7 |
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A1 |
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A6 |
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A2 |
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A5 |
54PIN TSOP (II) |
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A3 |
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A4 |
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VDD |
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VSS |
(400mil x 875mil) |
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(0.8 mm PIN PITCH) |
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PIN FUNCTION DESCRIPTION |
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PIN |
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NAME |
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INPUT FUNCTION |
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CLK |
System Clock |
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Active on the positive going edge to sample all inputs. |
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Disables or enables device operation by masking or enabling all inputs except |
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CS |
Chip Select |
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CLK, CKE and DQM |
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Masks system clock to freeze operation from the next clock cycle. |
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CKE |
Clock Enable |
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CKE should be enabled at least one cycle prior to new command. |
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Disable input buffers for power down in standby. |
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A0 ~ A11 |
Address |
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Row / column addresses are multiplexed on the same pins. |
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Row address : RA0 ~ RA11, column address : CA0 ~ CA8 |
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BA0 ~ BA1 |
Bank Select Address |
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Selects bank to be activated during row address latch time. |
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Selects bank for read/write during column address latch time. |
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Latches row addresses on the positive going edge of the CLK with |
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RAS |
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RAS |
Row Address Strobe |
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Enables row access & precharge. |
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Latches column addresses on the positive going edge of the CLK with |
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CAS |
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CAS |
Column Address Strobe |
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Enables column access. |
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Enables write operation and row precharge. |
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WE |
Write Enable |
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Latches data in starting from CAS, WE active. |
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L(U)DQM |
Data Input/Output Mask |
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Makes data output Hi-Z, tSHZ after the clock and masks the output. |
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Blocks data input when L(U)DQM active. |
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DQ0 ~ 15 |
Data Input/Output |
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Data inputs/outputs are multiplexed on the same pins. |
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VDD/VSS |
Power Supply/Ground |
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Power and ground for the input buffers and the core logic. |
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VDDQ/VSSQ |
Data Output Power/Ground |
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Isolated power supply and ground for the output buffers to provide improved noise |
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immunity. |
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N.C/RFU |
No Connection/ |
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This pin is recommended to be left No Connection on the device. |
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Reserved for Future Use |
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REV. 2 Mar. '98 |
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Preliminary |
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KM416S8030 |
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CMOS SDRAM |
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ABSOLUTE MAXIMUM RATINGS |
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Parameter |
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Symbol |
Value |
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Unit |
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Voltage on any pin relative to Vss |
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VIN, VOUT |
-1.0 ~ 4.6 |
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V |
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Voltage on VDD supply relative to Vss |
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VDD, VDDQ |
-1.0 ~ 4.6 |
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V |
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Storage temperature |
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TSTG |
-55 ~ +150 |
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°C |
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Power dissipation |
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PD |
1 |
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W |
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Short circuit current |
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IOS |
50 |
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mA |
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Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS |
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Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) |
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Parameter |
Symbol |
Min |
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Typ |
Max |
Unit |
Note |
Supply voltage |
VDD, VDDQ |
3.0 |
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3.3 |
3.6 |
V |
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Input logic high votlage |
VIH |
2.0 |
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3.0 |
VDDQ+0.3 |
V |
1 |
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Input logic low voltage |
VIL |
-0.3 |
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0 |
0.8 |
V |
2 |
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Output logic high voltage |
VOH |
2.4 |
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- |
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V |
IOH = -2mA |
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Output logic low voltage |
VOL |
- |
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0.4 |
V |
IOL = 2mA |
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Input leakage current(Inputs) |
IIL |
-5 |
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5 |
uA |
3 |
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Input leakage current (I/O pins) |
IIL |
-5 |
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5 |
uA |
3,4 |
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Note : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. |
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2.VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3.Any input 0V ≤ VIN ≤ VDDQ,
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4.Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) |
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Parameter |
Symbol |
Min |
Max |
Unit |
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Clock |
CCLK |
2.5 |
4 |
pF |
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CKE, DQM |
CIN |
2.5 |
5 |
pF |
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RAS, |
CAS, |
WE, |
CS, |
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Address |
CADD |
2.5 |
5 |
pF |
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DQ0 ~ DQ3 |
COUT |
4 |
6.5 |
pF |
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REV. 2 Mar. '98