Samsung KM41V4000DLT-6, KM41V4000DLJ-7, KM41V4000DLJ-6, KM41V4000DJ-7, KM41V4000DJ-6 Datasheet

KM41C4000D, KM41V4000D

CMOS DRAM

4M x 1Bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

This is a family of 4,194,304 x 1bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5V or +3.3V), access time (-5, -6 or -7), power consumption(Normal or Low power), and package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, self-refresh operation is available in Low power version.

This 4Mx1 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as main memory for main frames and mini computers, personal computer and high performance microprocessor systems.

FEATURES

•Part Identification

-KM41C4000D/D-L(5V, 1K Ref.)

-KM41V4000D/D-L(3.3V, 1K Ref.)

•Active Power Dissipation

		Unit : mW
Speed	3.3V	5V
-5	-	470
-6	220	415
-7	200	360

•Fast Page Mode operation

•CAS-before-RAS refresh capability

•RAS-only and Hidden refresh capability

•Self-refresh capability (3.3V, L-ver only)

•Fast parallel test mode capability

•TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

•Common I/O using early write

•JEDEC Standard pinout

•Available in 26(20)-pin SOJ 300mil and TSOP(II) 300mil packages

•+5V±10% power supply(5V product)

•+3.3V±0.3V power supply(3.3V product)

•	Refresh Cycles
	Part			Refresh						Refresh Period
	NO.			cycle				Normal			L-ver
	KM41C4000D			1K					16ms		128ms
	KM41V4000D
•	Performance Range
	Speed		tRAC	tCAC			tRC			tPC	Remark
	-5		50ns	15ns			90ns			35ns	5V only
	-6		60ns	15ns		110ns				40ns	5V/3.3V
	-7		70ns	20ns		130ns				45ns	5V/3.3V

FUNCTIONAL BLOCK DIAGRAM

RAS

Control

Vcc

CAS

Vss

W

Clocks

VBB Generator

Refresh Timer	Row Decoder
Refresh Control		I/O
		&
	Memory Array
		Amps
Refresh Counter	4,194,304 x1
	Cells
		Sense
Row Address Buffer
A0~A9
Col. Address Buffer	Column Decoder

Data in

Buffer D

Data out Q Buffer

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

KM41C4000D, KM41V4000D

CMOS DRAM

PIN CONFIGURATION (Top Views)

				•KM41C/V4000DJ
	D				1	20		VSS
	W				2	19		Q
RAS					3	18			CAS
N.C					4	17		N.C
A10					5	16		A9
A0					6	15		A8
A1					7	14		A7
A2					8	13		A6
A3					9	12		A5
VCC					10	11		A4

( SOJ )

			•KM41C/V4000DT
	D	1			20			VSS
	W			2	19			Q
RAS				3	18				CAS
N.C				4	17			N.C
A10				5	16			A9
A0		6			15			A8
A1		7			14			A7
A2		8			13			A6
A3		9			12			A5
VCC		10			11			A4

( TSOP-II )

		Pin Name							Pin function
		A0 - A10							Address Inputs
					D				Data In
					Q				Data out
				VSS					Ground
									Row Address Strobe
				RAS
									Column Address Strobe
			CAS
									Read/Write Input
					W
				N.C					No Connection
				VCC					Power(+5V)
									Power(+3.3V)

KM41C4000D, KM41V4000D								CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter		Symbol				Rating			Units
				3.3V				5V
Voltage on any pin relative to VSS		VIN,VOUT	-0.5	to	+4.6		-1	to +7.0	V
Voltage on VCC supply relative to VSS		VCC	-0.5	to	+4.6		-1	to +7.0	V
Storage Temperature		Tstg	-55 to +150				-55 to +150		°C
Power Dissipation		PD		600				600	mW
Short Circuit Output Current		IOS		50				50	mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

	Parameter	Symbol		3.3V				5V		Units
			Min	Typ		Max	Min	Typ	Max
Supply Voltage		VCC	3.0	3.3		3.6	4.5	5.0	5.5	V
Ground		VSS	0	0		0	0	0	0	V
Input High Voltage		VIH	2.0	-		VCC+0.3*1	2.4	-	VCC+1.0*1	V
Input Low Voltage		VIL	-0.3*2	-		0.8	-0.1*2	-	0.8	V
*1	: VCC +1.3V/15ns(3.3V), VCC +2.0V/20ns(5V), Pulse width is measured at VCC
*2	: - 1.3V/15ns(3.3V), - 2.0V/20ns(5V), Pulse width is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

			Parameter	Symbol	Min	Max	Units
		Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,		II(L)	-5	5	uA
		all other input pins not under test=0 Volt)
	3.3V	Output Leakage Current		IO(L)	-5	5	uA
		(Data out is disabled, 0V≤VOUT≤VCC)
		Output High Voltage Level(IOH=-2mA)		VOH	2.4	-	V
		Output Low Voltage Level(IOL=2mA)		VOL	-	0.4	V
		Input Leakage Current (Any input 0≤VIN≤VCC+0.5V,		II(L)	-5	5	uA
		all other input pins not under test=0 Volt)
	5V	Output Leakage Current		IO(L)	-5	5	uA
		(Data out is disabled, 0V≤VOUT≤VCC)
		Output High Voltage Level(IOH=-5mA)		VOH	2.4	-	V
		Output Low Voltage Level(IOL=4.2mA)		VOL	-	0.4	V

: Standby Current (RAS=CAS=W=VCC-0.2V)

KM41C4000D, KM41V4000D						CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Recommend operating conditions unless otherwise noted.)
Symbol	Power	Speed		Max			Units
			KM41V4000D		KM41C4000D
	Don′t Care	-5	-		85		mA
ICC1		-6	60		75		mA
		-7	55		65		mA
ICC2	Don′t Care	Don′t Care	1		2		mA
	Don′t Care	-5	-		85		mA
ICC3		-6	60		75		mA
		-7	55		65		mA
	Don′t Care	-5	-		65		mA
ICC4		-6	45		55		mA
		-7	40		45		mA
ICC5	Normal	Don′t Care	0.5		1		mA
	L		100		200		uA
	Don′t Care	-5	-		85		mA
ICC6		-6	60		75		mA
		-7	55		65		mA
ICC7	L	Don′t Care	200		300		uA
ICCS	L	Don′t Care	150		-		uA

ICC1* : Operating Current (RAS and CAS cycling @tRC=min.)

ICC2 : Standby Current (RAS=CAS=W=VIH)

ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)

ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)

ICC5

ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,

DQ=Don′t Care, TRC=125us(L-ver.), TRAS=TRASmin~300ns

ICCS : Self refresh current

RAS=CAS=VIL, W=OE =A0 ~ A10=D=VCC-0.2V or 0.2V

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.

KM41C4000D, KM41V4000D																																		CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
								Parameter															Symbol						Min					Max			Units
	Input capacitance [D]																							CIN1					-				5				pF
	Input capacitance [A0 ~ A10]																							CIN2					-				5				pF
	Input capacitance																							CIN3					-				7				pF
							[RAS,						CAS,		W]
	Output capacitance [Q]																							COUT					-				7				pF
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
				Parameter																	Symbol			-5*1					-6				7		Units		Notes
																								Min		Max			Min		Max	Min		Max
	Random read or write cycle time																				tRC			90					110			130			ns
	Read-modify-write cycle time																				tRWC			110					130			150			ns
	Access time from																				tRAC					50					60			70	ns		3,4,10
					RAS
	Access time from																				tCAC					15					15			20	ns		3,4,5
					CAS
	Access time from column address																				tAA					25					30			35	ns		3,10
		to output in Low-Z																			tCLZ			0					0			0			ns		3
	CAS
	Output buffer turn-off delay																				tOFF			0		12			0		12	0		17	ns		6
	Transition time (rise and fall)																				tT			3		50			3		50	3		50	ns		2
		precharge time																			tRP			30					40			50			ns
	RAS
		pulse width																			tRAS			50		10K			60		10K	70		10K	ns
	RAS
		hold time																			tRSH			15					15			20			ns
	RAS
		hold time																			tCSH			50					60			70			ns
	CAS
		pulse width																			tCAS			15		10K			15		10K	20		10K	ns
	CAS
		to		delay time																	tRCD			20		35			20		45	20		50	ns		4
	RAS		CAS
		to column address delay time																			tRAD			15		25			15		30	15		35	ns		10
	RAS
		to		precharge time																	tCRP			5					5			5			ns
	CAS		RAS
	Row address set-up time																				tASR			0					0			0			ns
	Row address hold time																				tRAH			10					10			10			ns
	Column address set-up time																				tASC			0					0			0			ns
	Column address hold time																				tCAH			10					10			15			ns
	Column address to											lead time									tRAL			25					30			35			ns
								RAS
	Read command set-up time																				tRCS			0					0			0			ns
	Read command hold time referenced to																				tRCH			0					0			0			ns		8
																		CAS
	Read command hold time referenced to																				tRRH			0					0			0			ns		8
																	RAS
	Write command hold time																				tWCH			10					10			15			ns
	Write command pulse width																				tWP			10					10			15			ns
	Write command to									lead time											tRWL			15					15			15			ns
						RAS
	Write command to									lead time											tCWL			13					15			15			ns
						CAS

Note) *1 : 5V only

KM41C4000D, KM41V4000D

CMOS DRAM

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)

Parameter

Symbol

-5*1

-6

-7

Units

Notes

Min

Max

Min

Max

Min

Max

Data set-up time

tDS

0

0

0

ns

9

Data hold time

tDH

10

10

15

ns

9

Refresh period (Normal)

tREF

16

16

16

ms

Refresh period (L-ver)

tREF

128

128

128

ms

Write command set-up time

tWCS

0

0

0

ns

7

to

delay time

tCWD

15

15

20

ns

7

CAS

W

to

delay time

tRWD

50

60

70

ns

7

RAS

W

Column address to

delay time

tAWD

25

30

35

ns

7

W

precharge to

delay time

tCPWD

30

35

40

ns

7

CAS

W

set-up time

-before-

refresh)

tCSR

10

10

10

ns

CAS

(CAS

RAS

hold time

-before-

refresh)

tCHR

10

10

15

ns

CAS

(CAS

RAS

to

precharge time

tRPC

5

5

5

ns

RAS

CAS

-B-

counter test cycle)

tCPT

20

20

25

ns

CAS

precharge time (C

R

Access time from

precharge

tCPA

30

35

40

ns

3

CAS

Fast Page mode cycle time

tPC

35

40

45

ns

Fast Page read-modify-write cycle time

tPRWC

53

60

70

ns

precharge time (Fast Page cycle)

tCP

10

10

10

ns

CAS

pulse width (Fast Page cycle)

tRASP

50

200K

60

200K

70

200K

ns

RAS

hold time from

precharge

tRHCP

30

35

40

ns

RAS

CAS

Write command set-up time (Test mode in)

tWTS

10

10

10

ns

Write command hold time (Test mode in)

tWTH

10

10

10

ns

to

-B-

refresh)

tWRP

10

10

10

ns

W

RAS

precharge time (C

R

to

-B-

refresh)

tWRH

10

10

10

ns

W

RAS

hold time (C

R

-B-

self refresh)

tRASS

100

100

100

us

14,15,16

RAS

pulse width (C

R

-B-

self refresh)

tRPS

90

110

130

ns

14,15,16

RAS

precharge time (C

R

-B-

self refresh)

tCHS

-50

-50

-50

ns

14,15,16

CAS

Hold time (C

R

Note) *1 : 5V only