Samsung K9F1608W0A-TIB0, K9F1608W0A-TCB0 Datasheet

K9F1608W0A-TCB0, K9F1608W0A-TIB0				FLASH MEMORY
Document Title
2M x 8 Bit NAND Flash Memory
Revision History
Revision No. History				Draft Date	Remark
0.0	Initial issue.			April 10th 1998	Preliminary
1.0	Data Sheet 1998.			July 14th 1998	Final
1.1	Data Sheet 1999.			April 10th 1999	Final
	1) Added CE don’t care mode during the data-loading and reading
1.2	1) Revised real-time map-out algorithm(refer to technical notes)			July 23th 1999	Final
1.3	Changed device name			Sep.15th 1999	Final
	- KM29W16000AT -> K9F1608W0A-TCB0
	- KM29W16000AIT -> K9F1608W0A-TIB0

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

1

K9F1608W0A-TCB0, K9F1608W0A-TIB0	FLASH MEMORY

2M x 8 Bit NAND Flash Memory

FEATURES

∙Voltage Supply : 2.7V ~ 5.5V

∙Organization

-Memory Cell Array : (2M + 64K)bit x 8bit

- Data Register

: (256 + 8)bit x8bit

∙Automatic Program and Erase

-Page Program : (256 + 8)Byte

- Block Erase : (4K + 128)Byte

-Status Register

∙264-Byte Page Read Operation

- Random Access

: 10μs(Max.)

-Serial Page Access : 80ns(Min.)

∙Fast Write Cycle Time

- Program time

: 250μs(typ.)

-Block Erase time : 2ms (typ.)

∙Command/Address/Data Multiplexed I/O port

∙Hardware Data Protection

-Program/Erase Lockout During Power Transitions

∙Reliable CMOS Floating-Gate Technology

-Endurance : 1M Program/Erase Cycles

-Data Retention : 10 years

∙Command Register Operation

∙44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)

-Forward Type

GENERAL DESCRIPTION

The K9F1608W0A is a 2M(2,097,152)x8bit NAND Flash Memory with a spare 64K(65,536)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the 264-byte page in typically 250μs and an erase operation can be performed in typically 2ms on a 4K-byte block.

Data in the page can be read out at 80ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase system functions, including pulse repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the K9F1608W0A extended reliability of 1,000,000 program/erase cycles by providing either ECC(Error Correction Code) or real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications and also the spare 8bytes of a page combined with the other 256 bytes can be utilized by system-level ECC.

The K9F1608W0A is an optimum solution for large nonvolatile storage application such as solid state storage, digital voice recorder, digital still camera and other portable applications requiring nonvolatility.

PIN CONFIGURATION

PIN DESCRIPTION

VSS		1	44		VCC
CLE		2	43		CE
ALE		3	42		RE
WE		4	41		R/B
WP		5	40		GND
N.C		6	39		N.C
N.C		7	38		N.C
N.C		8	37		N.C
N.C		9	36		N.C
N.C		10	35		N.C
		11	34
		12	33
N.C		13	32		N.C
N.C		14	31		N.C
N.C		15	30		N.C
N.C		16	29		N.C
N.C		17	28		N.C
I/O0		18	27		I/O7
I/O1		19	26		I/O6
I/O2		20	25		I/O5
I/O3		21	24		I/O4
VSS		22	23		VCCQ

44(40) TSOP (II) STANDARD TYPE

Pin Name					Pin Function
I/O0 ~ I/O7					Data Inputs/Outputs
CLE					Command Latch Enable
ALE					Address Latch Enable
	CE				Chip Enable
	RE				Read Enable
	WE				Write Enable
	WP				Write Protect
GND					Ground Input
	R/B				Ready/Busy output
VCC					Power(2.7V~5.5V)
VCCQ					Output Butter Power(2.7V~5.5V)
	VSS				Ground
N.C					No Connection

NOTE : Connect all VCC,VccQ and VSS pins of each device to power supply outputs.

Do not leave VCC or VSS disconnected.

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K9F1608W0A-TCB0, K9F1608W0A-TIB0	FLASH MEMORY

Figure 1. FUNCTIONAL BLOCK DIAGRAM

	A8 - A20	X-Buffers
		Latches	16M + 512K Bit
		& Decoders	NAND Flash
		Y-Buffers	ARRAY
	A0 - A7
		Latches	(256 + 8)Byte x 8192
		& Decoders
			Page Register & S/A
	Command		Y-Gating
			I/O Buffers & Latches
		Command
		Register	VccQ
			Vss
	CE	Control Logic
	RE	& High Voltage	I/0 0
	WE	Generator	Global Buffers
			I/0 7
		CLE ALE WP

Figure 2. ARRAY ORGANIZATION

16M : 8K Row

(=512 Block)

1 Block(=16 Row)

(4K + 128)Byte

1 Page = 264 Byte

1 Block = 264 B x 16 Pages = (4K + 128) Bytes

1 Device = 264B x 16Pages x 512 Blocks = 16.5 Mbits

	8 bit
256B Column	8B Column
Page Register	I/O 0 ~ I/O 7
256Byte	8Byte

		I/O 0	I/O 1	I/O 2	I/O 3	I/O 4	I/O 5	I/O 6	I/O 7
1st Cycle		A0	A1	A2	A3	A4	A5	A6	A7	Column Address
2nd Cycle		A8	A9	A10	A11	A12	A13	A14	A15	Row Address
										(Page Address)
3rd Cycle		A16	A17	A18	A19	A20	*X	*X	*X
NOTE : A12	to A20 : Block Address						* : X can be VIL or VIH.

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K9F1608W0A-TCB0, K9F1608W0A-TIB0	FLASH MEMORY

PRODUCT INTRODUCTION

The K9F1608W0A is a 16.5Mbit(17,301,504 bit) memory organized as 8192 rows by 264 columns. Spare eight columns are located from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages formed by one NAND structures, totaling 2,112 NAND structures of 16 cells. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array consists of 512 separately or grouped erasable 4K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1608W0A.

The K9F1608W0A has addresses multiplexed into 8 I/O′s. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O`s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block address loading. The 2M byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.

Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F1608W0A.

Table 1. COMMAND SETS

Function	1st. Cycle	2nd. Cycle	Acceptable Command during Busy
Sequential Data Input	80h	-
Read 1	00h	-
Read 2	50h	-
Read ID	90h	-
Reset	FFh	-	O
Page Program	10h	-
Block Erase	60h	D0h
Read Status	70h	-	O

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K9F1608W0A-TCB0, K9F1608W0A-TIB0	FLASH MEMORY

PIN DESCRIPTION

Command Latch Enable(CLE)

The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the path activation for address and input data to the internal address/data register. Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode. However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby mode.

Write Enable(WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.

I/O Port : I/O 0 ~ I/O 7

The I/O pins are used to input command, address and data, and to outputs data during read operations. The I/O pins float to high-z when the chip is deselected or the outputs are disabled.

Write Protect (WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and return to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or outputs are disabled.

Power Line(VCC & VCCQ)

The VCCQ is the power supply for I/O interface logic. It is electrically isolated from main power line(VCC=2.7~5.5V) for supporting 5V tolerant I/O with 5V power supply at VCCQ.

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K9F1608W0A-TCB0, K9F1608W0A-TIB0	FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

	Parameter		Symbol	Rating	Unit
	Voltage on any pin relative to VSS		VIN	-0.6 to +7.0	V
	Temperature Under Bias	K9F1608W0A-TCB0	TBIAS	-10 to +125	°C
		K9F1608W0A-TIB0		-40 to +125
	Storage Temperature		TSTG	-65 to +150	°C
	Short Circuit Output Current		IOS	5	mA

NOTE :

1.Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCCQ+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F1608W0A-TCB0:TA=0 to 70°C, K9F1608W0A-TIB0:TA=-40 to 85°C)

Parameter	Symbol	Min	Typ.	Max	Unit
Supply Voltage	VCC	2.7	-	5.5	V
Supply Voltage	VCCQ1)	2.7	-	5.5	V
Supply Voltage	VSS	0	0	0	V

NOTE : 1. Vcc and VccQ pins are separater each other.

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter				Symbol				Test Conditions								Vcc=2.7V ~ 3.6V			Vcc=3.6V ~ 5.5V			Unit
																Min	Typ	Max	Min	Typ	Max
	Sequential Read			ICC1			tcycle=80ns, CE=VIL,									-	10	20	-	15	30
							IOUT=0mA
Operating
	Program			ICC2			-									-	10	20	-	15	30	mA
Current
	Erase			ICC3			-									-	10	20	-	25	40
Stand-by Current(TTL)				ISB1			CE=VIH, WP=0V/VCC									-	-	1	-	-	1
Stand-by Current(CMOS)				ISB2			CE=VCC-0.2, WP=0V/VCC									-	5	50	-	5	50
Input Leakage Current				ILI			VIN=0 to 5.5V									-	-	±10	-	-	±10	μA
Output Leakage Current				ILO			VOUT=0 to 5.5V									-	-	±10	-	-	±10
Input High Voltage				VIH			I/O Pins									2.0	-	VCCQ+0.3	3.0	-	VCCQ+0.5
							Except I/O Pins									2.0	-	VCC+0.3	3.0	-	VCC+0.5
Input Low Voltage, All inputs				VIL			-									-0.3	-	0.6	-0.3	-	0.8	V
Output High Voltage Level				VOH			IOH=-400μA									2.4	-	-	2.4	-	-
Output Low Voltage Level				VOL			IOL=2.1mA									-	-	0.4	-	-	0.4
Output Low Current(R/B)				IOL(R/B)			VOL=0.4V									8	10	-	8	10	-	mA

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K9F1608W0A-TCB0, K9F1608W0A-TIB0	FLASH MEMORY

VALID BLOCK

Parameter	Symbol	Min	Typ.	Max	Unit
Valid Block Number	NVB	502	508	512	Blocks

NOTE :

1.The K9F1608W0A may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are guaranteed though its initial number could be reduced. (Refer to the attached technical notes)

2.The 1st block, which is placed on 00h block address, is guaranteed to be a valid block

AC TEST CONDITION

(K9F1608W0A-TCB0:TA=0 to 70°C, K9F1608W0A-TIB0:TA=-40 to 85°C, VCC=2.7V ~ 5.5V unless otherwise noted)

Parameter			Value
		Vcc=2.7V ~ 3.6V		Vcc=3.6V ~ 5.5V
Input Pulse Levels		0.4V to 2.4V		0.4V to 3.4V
Input Rise and Fall Times			5ns
Input and Output Timing Levels			0.8V and 2.0V
Output Load		1 TTL GATE and		1 TTL GATE and CL = 100pF
		CL=50pF(3.0V+/-10%),100pF(3.0V~3.6V)

CAPACITANCE(TA=25°C, Vcc=5.0V f=1.0MHz)

Item	Symbol	Test Condition	Min	Max	Unit
Input/Output Capacitance	CI/O	VIL=0V	-	10	pF
Input Capacitance	CIN	VIN=0V	-	10	pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE	ALE	CE	WE	RE	WP	Mode
H	L	L		H	X	Command Input
L	H	L		H	X	Read Mode
						Address Input(3clock)
H	L	L		H	H	Command Input
L	H	L		H	H	Write Mode
						Address Input(3clock)
L	L	L		H	H	Data Input
L	L	L	H		X	Sequential Read & Data Output
L	L	L	H	H	X	During Read(Busy)
X	X	X	X	X	H	During Program(Busy)
X	X	X	X	X	H	During Erase(Busy)
X	X(1)	X	X	X	L	Write Protect
X	X	H	X	X	0V/VCC(2)	Stand-by

NOTE : 1. X can be VIL or VIH

2. WP should be biased to CMOS high or CMOS low for standby.

Program/Erase Characteristics

	Parameter	Symbol	Min	Typ	Max	Unit
	Program Time	tPROG	-	0.25	1.5	ms
	Number of Partial Program Cycles in the Same Page	Nop	-	-	10	cycles
	Block Erase Time	tBERS	-	2	10	ms

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K9F1608W0A-TCB0, K9F1608W0A-TIB0	FLASH MEMORY

AC Timing Characteristics for Command / Address / Data Input

			Parameter	Symbol	Min	Max	Unit
	CLE Set-up Time			tCLS	20	-	ns
	CLE Hold Time			tCLH	40	-	ns
	CE Setup Time			tCS	20	-	ns
	CE Hold Time			tCH	40	-	ns
	WE Pulse Width			tWP	40	-	ns
	ALE Setup Time			tALS	20	-	ns
	ALE Hold Time			tALH	40	-	ns
	Data Setup Time			tDS	30	-	ns
	Data Hold Time			tDH	20	-	ns
	Write Cycle Time			tWC	80	-	ns
	WE High Hold Time			tWH	20	-	ns

AC Characteristics for Operation

Parameter

Symbol

Min

Max

Unit

Data Transfer from Cell to Register

tR

-

10

μs

ALE to RE Delay

tAR

150

-

ns

ALE to RE Delay(read ID)

tAR1

200

-

ns

CE to RE Delay( ID read)

tCR

200

-

ns

Ready to RE Low

tRR

20

-

ns

WE High to Busy

tWB

-

200

ns

Read Cycle Time

tRC

80

-

ns

RE Access Time

tREA

-

45

ns

RE High to Output Hi-Z

tRHZ

5

20

ns

CE High to Output Hi-Z

tCHZ

-

30

ns

RE High Hold Time

tREH

20

-

ns

Output Hi-Z to RE Low

tIR

0

-

ns

Last RE High to Busy(at sequential read)

tRB

-

200

ns

tCRY

-

ns

CE High to Ready(in case of interception by CE at read)(1)

100+tr(R/B)(2)

tCEH

250

-

ns

CE High Hold Time(at the last serial read)(3)

RE Low to Status Output

tRSTO

-

45

ns

CE Low to Status Output

tCSTO

-

55

ns

RE High to WE Low

tRHW

0

-

ns

WE High to RE Low

tWHR

50

-

ns

Device Resetting Time(Read/Program/Erase)

tRST

-

5/10/500

μs

NOTE : 1. If CE goes high within 30ns after the rising edge of the last RE, R/B will not return to VOL.

2.The time to Ready depends on the value of the pull-up resistor tied R/B pin.

3.To break the sequential read cycle, CE must be held high for longer time than tCEH.

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