Samsung KM416C4100BS-5, KM416C4100BS-45, KM416C4000BS-6, KM416C4000BS-5, KM416C4000BS-45 Datasheet

KM416C4000B,KM416C4100B	CMOS DRAM

4M x 16bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

FEATURES

• Fast Page Mode operation

• Part Identification

•

2CAS

Byte/Word Read/Write operation

• CAS-before-RAS refresh capability

- KM416C4000B(5.0V, 8K Ref.)

•

RAS

-only and Hidden refresh capability

- KM416C4100B(5.0V, 4K Ref.)

• Fast parallel test mode capability

• TTL(5.0V) compatible inputs and outputs

• Active Power Dissipation

Unit : mW

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic TSOP(II) package

Speed

8K

4K

-45

550

715

• +5.0V±10% power supply

-5

495

660

-6

440

605

• Refresh Cycles

Part

Refresh

Refresh time

FUNCTIONAL BLOCK DIAGRAM

NO.

cycle

Normal

KM416C4000B*

8K

64ms

RAS

Vcc

KM416C4100B

4K

UCAS

Control

Vss

LCAS

Clocks

VBB Generator

W

* Access mode & RAS only refresh mode									Lower
: 8K cycle/64ms
							Row Decoder		Data in
CAS-before-RAS & Hidden refresh mode						Refresh Timer			Buffer
: 4K cycle/64ms						Refresh Control		I/O	Lower
									Data out
								&
							Memory Array		Buffer
								Amps
• Performance Range						Refresh Counter	4,194,304 x 16		Upper
							Cells
Speed	tRAC	tCAC	tRC	tPC				Sense	Data in
					A0~A12	Row Address Buffer			Buffer
-45	45ns	12ns	80ns	31ns	(A0~A11)*1				Upper
-5	50ns	13ns	90ns	35ns	A0~A8	Col. Address Buffer	Column Decoder		Data out
									Buffer
					(A0~A9)*1
-6	60ns	15ns	110ns	40ns		Note) *1 : 4K Refresh

DQ0

to

DQ7

OE

DQ8 to

DQ15

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

KM416C4000B,KM416C4100B	CMOS DRAM

PIN CONFIGURATION (Top Views)

• KM416C40(1)00BS
VCC				1		50				VSS
DQ0				2		49				DQ15
DQ1				3		48				DQ14
DQ2				4		47				DQ13
DQ3				5		46				DQ12
VCC				6		45				VSS
DQ4				7		44				DQ11
DQ5				8		43				DQ10
DQ6					9	42				DQ9
DQ7				10		41				DQ8
N.C				11		40				N.C
VCC				12		39				VSS
W				13		38				LCAS
RAS				14		37				UCAS
N.C				15		36				OE
N.C				16		35				N.C
N.C				17		34				N.C
N.C				18		33				A12(N.C)*
A0				19		32				A11
A1					20	31				A10
A2				21		30				A9
A3					22	29				A8
A4				23		28				A7
A5					24	27				A6
VCC				25		26				VSS

									(400mil TSOP(II))
								*(N.C) : N.C for 4K Refresh Product
			Pin Name						Pin function
			A0 - A12						Address Inputs(8K Product)
			A0 - A11						Address Inputs(4K Product)
			DQ0 - 15						Data In/Out
			VSS						Ground
									Row Address Strobe
			RAS
									Upper Column Address Strobe
			UCAS
									Lower Column Address Strobe
			LCAS
									Read/Write Input
			W
									Data Output Enable
			OE
			VCC						Power(+5.0V)
			N.C						No Connection

KM416C4000B,KM416C4100B					CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter	Symbol	Rating				Units
Voltage on any pin relative to VSS	VIN,VOUT	-1.0	to	+7.0		V
Voltage on VCC supply relative to VSS	VCC	-1.0	to	+7.0		V
Storage Temperature	Tstg	-55 to +150				°C
Power Dissipation	PD		1			W
Short Circuit Output Current	IOS Address		50			mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70°C)

	Parameter	Symbol		Min	Typ	Max	Units
Supply Voltage		VCC		4.5	5.0	5.5	V
Ground		VSS		0	0	0	V
Input High Voltage		VIH		2.4	-	VCC+1.0*1	V
Input Low Voltage		VIL		-1.0*2	-	0.8	V
*1	: VCC+2.0V at pulse width≤20ns which is measured at VCC
*2	: -2.0 at pulse width≤20ns which is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

	Parameter		Symbol	Min	Max	Units
	Input Leakage Current (Any input 0≤VIN≤VCC+0.5V,		II(L)	-5	5	uA
	all other pins not under test=0 Volt)
	Output Leakage Current		IO(L)	-5	5	uA
	(Data out is disabled, 0V≤VOUT≤VCC)
	Output High Voltage Level(IOH=-5mA)		VOH	2.4	-	V
	Output Low Voltage Level(IOL=4.2mA)		VOL	-	0.4	V

KM416C4000B,KM416C4100B							CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol	Power	Speed			Max			Units
				KM416C4000B		KM416C4100B
		-45		100		130		mA
ICC1	Don′t care	-5		90		120		mA
		-6		80		110		mA
ICC2	Normal	Don′t care		2		2		mA
		-45		100		130		mA
ICC3	Don′t care	-5		90		120		mA
		-6		80		110		mA
		-45		70		80		mA
ICC4	Don′t care	-5		60		70		mA
		-6		50		60		mA
ICC5	Normal	Don′t care		1		1		mA
		-45		100		130		mA
ICC6	Don′t care	-5		90		120		mA
		-6		80		110		mA

ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)

ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)

ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)

ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.)

ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min)

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.

KM416C4000B,KM416C4100B

CMOS DRAM

CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A12]

CIN1

-

5

pF

Input capacitance

CIN2

-

7

pF

[RAS,

UCAS,

LCAS,

W,

OE]

Output capacitance [DQ0 - DQ15]

CDQ

-

7

pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V

						Parameter										Symbol	-45				-5			-6		Units	Note
																	Min		Max	Min		Max	Min		Max
		Random read or write cycle time														tRC	80			90			110			ns
		Read-modify-write cycle time														tRWC	115			133			153			ns
		Access time from														tRAC			45			50			60	ns	3,4,10
						RAS
		Access time from														tCAC			12			13			15	ns	3,4,5
						CAS
		Access time from column address														tAA			23			25			30	ns	3,10
			to output in Low-Z													tCLZ	0			0			0			ns	3
		CAS
		Output buffer turn-off delay														tOFF	0		13	0		13	0		13	ns	6
		Transition time (rise and fall)														tT	1		50	1		50	1		50	ns	2
			precharge time													tRP	25			30			40			ns
		RAS
			pulse width													tRAS	45		10K	50		10K	60		10K	ns
		RAS
			hold time													tRSH	12			13			15			ns
		RAS
			hold time													tCSH	45			50			60			ns
		CAS
			pulse width													tCAS	12		10K	13		10K	15		10K	ns
		CAS
			to		delay time											tRCD	18		33	20		37	20		45	ns	4
		RAS		CAS
			to column address delay time													tRAD	13		22	15		25	15		30	ns	10
		RAS
			to		precharge time											tCRP	5			5			5			ns
		CAS		RAS
		Row address set-up time														tASR	0			0			0			ns
		Row address hold time														tRAH	8			10			10			ns
		Column address set-up time														tASC	0			0			0			ns	13
		Column address hold time														tCAH	8			10			10			ns	13
		Column address to									lead time					tRAL	23			25			30			ns
								RAS
		Read command set-up time														tRCS	0			0			0			ns
		Read command hold time referenced to														tRCH	0			0			0			ns	8
													CAS
		Read command hold time referenced to														tRRH	0			0			0			ns	8
												RAS
		Write command hold time														tWCH	8			10			10			ns
		Write command pulse width														tWP	8			10			10			ns
		Write command to								lead time						tRWL	13			15			15			ns
							RAS
		Write command to								lead time						tCWL	12			13			15			ns	16
							CAS
		Data set-up time														tDS	0			0			0			ns	9,19
		Data hold time														tDH	10			10			10			ns	9,19

KM416C4000B,KM416C4100B

CMOS DRAM

AC CHARACTERISTICS (Continued)

Parameter

Symbol

-45

-5

-6

Units

Note

Min

Max

Min

Max

Min

Max

Refresh period (4K, Normal)

tREF

64

64

64

ms

Refresh period (8K, Normal)

tREF

64

64

64

ms

Write command set-up time

tWCS

0

0

0

ns

7

to

delay time

tCWD

32

36

38

ns

7,15

CAS

W

to

delay time

tRWD

67

73

83

ns

7

RAS

W

Column address to

delay time

tAWD

43

48

53

ns

7

W

precharge

delay time

tCPWD

48

53

60

ns

CAS

W

set-up time

-before-

refresh)

tCSR

5

5

5

ns

17

CAS

(CAS

RAS

hold time

-before-

refresh)

tCHR

10

10

10

ns

18

CAS

(CAS

RAS

to

precharge time

tRPC

5

5

5

ns

RAS

CAS

Access time from

precharge

tCPA

26

30

35

ns

3

CAS

Fast Page mode cycle time

tPC

31

35

40

ns

Fast Page mode read-modify-write cycle time

tPRWC

70

76

85

ns

precharge time (Fast Page cycle)

tCP

9

10

10

ns

14

CAS

pulse width (Fast Page cycle)

tRASP

45

200K

50

200K

60

200K

ns

RAS

hold time from

precharge

tRHCP

28

30

35

ns

RAS

CAS

access time

tOEA

12

13

15

ns

OE

to data delay

tOED

12

13

13

ns

OE

Output buffer turn off delay time from

tOEZ

0

13

0

13

0

13

ns

6

OE

command hold time

tOEH

12

13

15

ns

OE

Write command set-up time (Test mode in)

tWTS

10

10

10

ns

11

Write command hold time (Test mode in)

tWTH

15

15

15

ns

11

to

tWRP

W

RAS

precharge time (C

-B-R refresh)

10

10

10

ns

to

-B-

refresh)

tWRH

10

10

10

ns

W

RAS

hold time (C

R

-B-

self refresh)

tRASS

100

100

100

us

20,21,22

RAS

pulse width (C

R

-B-

self refresh)

tRPS

80

90

110

ns

20,21,22

RAS

precharge time (C

R

-B-

self refresh)

tCHS

-50

-50

-50

ns

20,21,22

CAS

hold time (C

R

	KM416C4000B,KM416C4100B																								CMOS DRAM
TEST MODE CYCLE																											( Note 11 )
								Parameter								Symbol		-45			-5			-6		Units	Note
																	Min		Max	Min		Max	Min		Max
		Random read or write cycle time														tRC	85			95			115			ns
		Read-modify-write cycle time														tRWC	120			138			160			ns
		Access time from														tRAC			50			55			65	ns	3,4,10,12
									RAS
		Access time from														tCAC			17			18			20	ns	3,4,5,12
									CAS
		Access time from column address														tAA			28			30			35	ns	3,10,12
						pulse width										tRAS	50		10K	55		10K	65		10K	ns
		RAS
						pulse width										tCAS	17		10K	18		10K	20		10K	ns
		CAS
						hold time										tRSH	17			18			20			ns
		RAS
						hold time										tCSH	50			55			65			ns
		CAS
		Column Address to													lead time	tRAL	28			30			35			ns
											RAS
					to			delay time								tCWD	37			41			43			ns	7
		CAS					W
						to		delay time								tRWD	72			78			88			ns	7
		RAS					W
		Column Address to											delay time			tAWD	48			53			58			ns	7
											W
		Fast Page mode cycle time														tPC	36			40			45			ns
		Fast Page mode read-modify-write cycle time														tPRWC	75			81			90			ns
					pulse width (Fast Page cycle)											tRASP	50		200K	55		200K	65		200K	ns
		RAS
		Access time from											precharge			tCPA			31			35			40	ns	3
										CAS
				access time												tOEA			17			18			20	ns
		OE
				to data delay												tOED	17			18			18			ns
		OE
				command hold time												tOEH	17			18			20			ns
		OE

KM416C4000B,KM416C4100B	CMOS DRAM

NOTES

1.An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved.

2.VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.

3.Measured with a load equivalent to 2 TTL load and 100pF.

4.Operation within the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.

5.Assumes that tRCD³tRCD(max).

6.tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh or Vol.

7.tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS³tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD³tCWD(min), tRWD³tRWD(min) and tAWD³tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate.

8.Either tRCH or tRRH must be satisfied for a read cycle.

9.These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.

10.If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. These specifications are applied in the test mode.

11.In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters

12.should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

KM416C40(1)00B Truth Table

	RAS	LCAS		UCAS	W	OE	DQ0 - DQ7	DQ8-DQ15	STATE
	H	X		X	X	X	Hi-Z	Hi-Z	Standby
	L	H		H	X	X	Hi-Z	Hi-Z	Refresh
	L	L		H	H	L	DQ-OUT	Hi-Z	Byte Read
	L	H		L	H	L	Hi-Z	DQ-OUT	Byte Read
	L	L		L	H	L	DQ-OUT	DQ-OUT	Word Read
	L	L		H	L	H	DQ-IN	-	Byte Write
	L	H		L	L	H	-	DQ-IN	Byte Write
	L	L		L	L	H	DQ-IN	DQ-IN	Word Write
	L	L		L	H	H	Hi-Z	Hi-Z	-

KM416C4000B,KM416C4100B	CMOS DRAM

13.tASC, tCAH are referenced to the earlier CAS falling edge.

14.tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.

15.tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.

16.tCWL is specified from W falling edge to the earlier CAS rising edge.

17.tCSR is referenced to the earlier CAS falling edge before RAS transition low.

18.tCHR is referenced to the later CAS rising edge after RAS transition low.

RAS

LCAS

UCAS

tCSR

tCHR

19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge.

LCAS

UCAS

tDS tDH

DQ0 ~ DQ15							Din

20.If tRASS³100us, then RAS precharge time must use tRPS instead of tRP.

21.For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification.

22.For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.

KM416C4000B,KM416C4100B	CMOS DRAM

WORD READ CYCLE

				tRC
VIH -				tRAS	tRP
RAS VIL -
	tCRP			tCSH	tCRP
			tRCD	tRSH
VIH -
				tCAS
UCAS VIL -
	tCRP			tCSH	tCRP
			tRCD	tRSH
VIH -
				tCAS
LCAS VIL -
			tRAD	tRAL
	tASR	tRAH	tASC
				tCAH
VIH -
	ROW			COLUMN
A VIL -
	ADDRESS			ADDRESS
			tRCS		tRCH
					tRRH
VIH -
W VIL -
				tAA
VIH -				tOEA
OE VIL -					tOFF
				tCAC
DQ0 ~ DQ7				tCLZ	tOEZ
				tRAC
VOH -
		OPEN			DATA-OUT
VOL -
					tOFF
				tCAC
DQ8 ~ DQ15				tCLZ	tOEZ
VOH -				tRAC
		OPEN			DATA-OUT
VOL -

Don′t care

Undefined

KM416C4000B,KM416C4100B	CMOS DRAM

LOWER BYTE READ CYCLE

NOTE : DIN = OPEN

				tRC
VIH -				tRAS	tRP
RAS VIL -
	tCRP				tRPC
VIH -
UCAS VIL -				tCSH
	tCRP
			tRCD	tRSH
VIH -
				tCAS
LCAS VIL -			tRAD
	tASR	tRAH	tASC	tRAL
				tCAH
VIH -
	ROW			COLUMN
A VIL -
	ADDRESS			ADDRESS
			tRCS		tRCH
					tRRH
VIH -
W VIL -					tOFF
				tAA	tOEZ
VIH -				tOEA
OE VIL -
				tCAC
DQ0 ~ DQ7			tRAC	tCLZ
VOH -
		OPEN			DATA-OUT
VOL -
DQ8 ~ DQ15
VOH -				OPEN
VOL -

Don′t care

Undefined