KM432S2030C |
CMOS SDRAM |
2M x 32 SDRAM
512K x 32bit x 4 Banks Synchronous DRAM LVTTL
Revision 1.1
March 1999
Samsung Electronics reserves the right to change products or specification without notice.
- 1 - |
REV. 1.1 Mar. '99 |
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KM432S2030C |
CMOS SDRAM |
Revision History
Revision 1.1 (March 12th, 1999)
• Corrected typo in ordering information on page 3
Revision 1.0 (March 8th, 1999) - Final Spec
•Removed KM432S2030C-Z@CL2 part (125MHz@CL2)
•Changed tRDL from 1CLK to 2CLK for every clock frequency. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
Revision 0.3 (March 5th, 1999) - Preliminary Spec
Revision 0.2 (February 13th, 1999)
•Removed KM432S2030C-7@CL2 part (115MHz@CL2)
•Changed VDD condition of KM432S2030C-8@CL2 from 3.135V to 3.0V~3.6V.
•Changed AC Characteristic table format
•Add KM432S2030C-Z part.
Revision 0.1 (December 2nd, 1998)
• Delete refresh information(4K/64ms)
Revision 0.0 (November 20th, 1998)
• Define target specification.
- 2 - |
REV. 1.1 Mar. '99 |
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KM432S2030C |
CMOS SDRAM |
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
•3.3V power supply
•LVTTL compatible with multiplexed address
•Four banks operation
•MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
•All inputs are sampled at the positive going edge of the system clock
•Burst read single-bit write operation
•DQM for masking
•Auto & self refresh
•15.6us refresh duty cycle
GENERAL DESCRIPTION
The KM432S2030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part NO. |
Max Freq. |
Interface |
Package |
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KM432S2030CT-G/F6 |
166MHz |
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KM432S2030CT-G/F7 |
143MHz |
LVTTL |
86 |
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TSOP(II) |
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KM432S2030CT-G/F8 |
125MHz |
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KM432S2030CT-G/F10 |
100MHz |
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FUNCTIONAL BLOCK DIAGRAM
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I/O |
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LWE |
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Control |
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Data Input Register |
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LDQM |
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Bank Select
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Address |
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CounterRefresh |
BufferRow |
DecoderRow |
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512K x 32 |
AMPSense |
BufferOutput |
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512K x 32 |
DQi |
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512K x 32 |
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CLK |
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512K x 32 |
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Register |
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LRAS |
LCBR |
Buffer.Col |
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ADD |
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Column Decoder |
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Latency & Burst Length |
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LCKE |
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Programming Register |
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LRAS |
LCBR |
LWE |
LCAS |
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LWCBR |
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LDQM |
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Timing Register |
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CLK |
CKE |
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CS |
RAS |
CAS |
WE |
DQM |
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* Samsung Electronics reserves the right to |
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change products or specification without |
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notice. |
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- 3 - |
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REV. 1.1 Mar. '99 |
KM432S2030C |
CMOS SDRAM |
PIN CONFIGURATION (Top view)
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VDD |
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1 |
86 |
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VSS |
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DQ0 |
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2 |
85 |
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DQ15 |
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VDDQ |
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3 |
84 |
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VSSQ |
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DQ1 |
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4 |
83 |
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DQ14 |
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DQ2 |
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5 |
82 |
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DQ13 |
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VSSQ |
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6 |
81 |
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VDDQ |
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DQ3 |
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7 |
80 |
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DQ12 |
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DQ4 |
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8 |
79 |
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DQ11 |
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VDDQ |
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9 |
78 |
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VSSQ |
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DQ5 |
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10 |
77 |
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DQ10 |
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DQ6 |
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11 |
76 |
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DQ9 |
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VSSQ |
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12 |
75 |
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VDDQ |
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DQ7 |
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13 |
74 |
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DQ8 |
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N.C |
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14 |
73 |
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N.C |
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VDD |
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15 |
72 |
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VSS |
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DQM0 |
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16 |
71 |
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DQM1 |
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WE |
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17 |
70 |
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N.C |
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CAS |
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18 |
69 |
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N.C |
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RAS |
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19 |
68 |
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CLK |
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CS |
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20 |
67 |
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CKE |
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N.C |
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21 |
66 |
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A9 |
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BA0 |
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22 |
65 |
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A8 |
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BA1 |
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23 |
64 |
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A7 |
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A10/AP |
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24 |
63 |
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A6 |
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A0 |
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25 |
62 |
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A5 |
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A1 |
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26 |
61 |
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A4 |
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A2 |
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27 |
60 |
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A3 |
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DQM2 |
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28 |
59 |
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DQM3 |
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VDD |
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29 |
58 |
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VSS |
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N.C |
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30 |
57 |
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N.C |
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DQ16 |
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31 |
56 |
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DQ31 |
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VSSQ |
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32 |
55 |
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VDDQ |
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DQ17 |
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33 |
54 |
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DQ30 |
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DQ18 |
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34 |
53 |
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DQ29 |
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VDDQ |
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35 |
52 |
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VSSQ |
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DQ19 |
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36 |
51 |
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DQ28 |
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DQ20 |
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37 |
50 |
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DQ27 |
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VSSQ |
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38 |
49 |
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VDDQ |
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DQ21 |
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39 |
48 |
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DQ26 |
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DQ22 |
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40 |
47 |
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DQ25 |
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VDDQ |
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41 |
46 |
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VSSQ |
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DQ23 |
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42 |
45 |
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DQ24 |
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VDD |
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43 |
44 |
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VSS |
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86Pin TSOP (II) (400mil x 875mil) (0.5 mm Pin pitch)
- 4 - |
REV. 1.1 Mar. '99 |
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KM432S2030C |
CMOS SDRAM |
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PIN FUNCTION DESCRIPTION |
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Pin |
Name |
Input Function |
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CLK |
System clock |
Active on the positive going edge to sample all inputs. |
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Disables or enables device operation by masking or enabling all inputs except |
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CS |
Chip select |
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CLK, CKE and DQM. |
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Masks system clock to freeze operation from the next clock cycle. |
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CKE |
Clock enable |
CKE should be enabled at least one cycle prior to new command. |
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Disables input buffers for power down mode. |
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A0 ~ A10 |
Address |
Row/column addresses are multiplexed on the same pins. |
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Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 |
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BA0,1 |
Bank select address |
Selects bank to be activated during row address latch time. |
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Selects bank for read/write during column address latch time. |
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Latches row addresses on the positive going edge of the CLK with RAS low. |
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RAS |
Row address strobe |
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Enables row access & precharge. |
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Latches column addresses on the positive going edge of the CLK with CAS low. |
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CAS |
Column address strobe |
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Enables column access. |
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Enables write operation and row precharge. |
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WE |
Write enable |
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Latches data in starting from CAS, WE active. |
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DQM0 ~ 3 |
Data input/output mask |
Makes data output Hi-Z, tSHZ after the clock and masks the output. |
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Blocks data input when DQM active. |
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DQ0 ~ 31 |
Data input/output |
Data inputs/outputs are multiplexed on the same pins. |
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VDD/VSS |
Power supply/ground |
Power and ground for the input buffers and the core logic. |
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VDDQ/VSSQ |
Data output power/ground |
Isolated power supply and ground for the output buffers to provide improved noise |
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immunity. |
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NC |
No Connection |
This pin is recommended to be left No connection on the device. |
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ABSOLUTE MAXIMUM RATINGS
Parameter |
Symbol |
Value |
Unit |
Voltage on any pin relative to Vss |
VIN, VOUT |
-1.0 ~ 4.6 |
V |
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Voltage on VDD supply relative to Vss |
VDD, VDDQ |
-1.0 ~ 4.6 |
V |
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Storage temperature |
TSTG |
-55 ~ +150 |
°C |
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Power dissipation |
PD |
1 |
W |
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Short circuit current |
IOS |
50 |
mA |
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Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) |
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Pin |
Symbol |
Min |
Max |
Unit |
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Clock |
CCLK |
2.5 |
4 |
pF |
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RAS, CAS, WE, CS, CKE, DQM |
CIN |
2.5 |
4.5 |
pF |
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Address |
CADD |
2.5 |
4.5 |
pF |
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DQ0 ~ DQ31 |
COUT |
4.0 |
6.5 |
pF |
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- 5 - REV. 1.1 Mar. '99
KM432S2030C |
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CMOS SDRAM |
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DC OPERATING CONDITIONS |
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Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) |
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Parameter |
Symbol |
Min |
Typ |
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Max |
Unit |
Note |
Supply voltage |
VDD, VDDQ |
3.0 |
3.3 |
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3.6 |
V |
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Input logic high voltage |
VIH |
2.0 |
3.0 |
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VDDQ+0.3 |
V |
1 |
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Input logic low voltage |
VIL |
-0.3 |
0 |
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0.8 |
V |
2 |
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Output logic high voltage |
VOH |
2.4 |
- |
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V |
IOH = -2mA |
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Output logic low voltage |
VOL |
- |
- |
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0.4 |
V |
IOL = 2mA |
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Input leakage current (Inputs) |
IIL |
-1 |
- |
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1 |
uA |
3 |
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Input leakage current (I/O pins) |
IIL |
-1.5 |
- |
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1.5 |
uA |
3,4 |
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Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is £ 3ns.
2.VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3.Any input 0V £ VIN £ VDDQ,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4.Dout is disabled, 0V £ VOUT £ VDDQ.
5.The VDD condition of KM432S2030C-6 is 3.135V~3.6V.
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter |
Symbol |
Test Condition |
CAS |
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Version |
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Unit |
Note |
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Latency |
-6 |
-7 |
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-8 |
-10 |
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Operating current |
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Burst length = 1 |
3 |
140 |
130 |
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130 |
115 |
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ICC1 |
tRC ³ tRC(min) |
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mA |
1 |
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(One bank active) |
2 |
- |
- |
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130 |
115 |
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IOL = 0 mA |
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Precharge standby current |
ICC2P |
CKE £ VIL(max), tCC = 15ns |
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2 |
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mA |
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in power-down mode |
ICC2PS |
CKE & CLK £ VIL(max), tCC = ¥ |
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2 |
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CKE ³ VIH(min), |
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³ VIH(min), tCC = 15ns |
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ICC2N |
CS |
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20 |
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mA |
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Precharge standby current |
Input signals are changed one time during 30ns |
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in non power-down mode |
ICC2NS |
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥ |
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10 |
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mA |
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Input signals are stable |
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Active standby current in |
ICC3P |
CKE £ VIL(max), tCC = 15ns |
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3 |
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mA |
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power-down mode |
ICC3PS |
CKE & CLK £ VIL(max), tCC = ¥ |
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3 |
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CKE ³ VIH(min), |
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³ VIH(min), tCC = 15ns |
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Active standby current in |
ICC3N |
CS |
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30 |
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mA |
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Input signals are changed one time during 30ns |
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non power-down mode |
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CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥ |
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(One bank active) |
ICC3NS |
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20 |
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mA |
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Input signals are stable |
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Operating current |
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IOL = 0 mA |
3 |
200 |
180 |
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150 |
130 |
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ICC4 |
Page burst |
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mA |
1 |
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(Burst mode) |
2 |
- |
- |
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130 |
110 |
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2 Banks activated |
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Refresh current |
ICC5 |
tRC ³ tRC(min) |
3 |
200 |
180 |
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160 |
150 |
mA |
2 |
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2 |
- |
- |
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160 |
150 |
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Self refresh current |
ICC6 |
CKE £ 0.2V |
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2 |
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mA |
3 |
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450 |
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uA |
4 |
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Notes : 1. Measured with outputs open.
2.Refresh period is 64ms.
3.KM432S2030CT-G**
4.KM432S2030CT-F**
- 6 - |
REV. 1.1 Mar. '99 |
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KM432S2030C |
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CMOS SDRAM |
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AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) |
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Parameter |
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Value |
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Unit |
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AC input levels (Vih/Vil) |
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2.4/0.4 |
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V |
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Input timing measurement reference level |
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1.4 |
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V |
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Input rise and fall time |
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tr/tf = 1/1 |
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ns |
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Output timing measurement reference level |
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1.4 |
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V |
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Output load condition |
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See Fig. 2 |
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3.3V |
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Vtt = 1.4V |
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1200Ω |
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50Ω |
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Output |
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VOH (DC) = 2.4V, IOH = -2mA |
Output |
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Z0 = 50Ω |
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50pF*1 |
VOL (DC) = 0.4V, IOL = 2mA |
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50pF*1 |
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870Ω |
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(Fig. 1) DC output load circuit |
(Fig. 2) AC output load circuit |
Note : 1. The DC/AC Test Output Load of KM432S2030C-6/7 is 30pF. 2. The VDD condition of KM432S2030C-6 is 3.135V~3.6V.
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
|
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Parameter |
Symbol |
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Version |
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Unit |
Note |
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-6 |
-7 |
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-8 |
-10 |
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CLK cycle time |
tCC(min) |
6 |
7 |
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8 |
10 |
ns |
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Row active to row active delay |
tRRD(min) |
12 |
14 |
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16 |
20 |
ns |
1 |
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RAS to CAS delay |
tRCD(min) |
18 |
18 |
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18 |
20 |
ns |
1 |
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Row precharge time |
tRP(min) |
18 |
18 |
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18 |
20 |
ns |
1 |
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Row active time |
tRAS(min) |
42 |
49 |
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48 |
50 |
ns |
1 |
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tRAS(max) |
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100 |
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us |
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Row cycle time |
tRC(min) |
66 |
67 |
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68 |
70 |
ns |
1 |
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Last data in to row precharge |
tRDL(min) |
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2 |
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CLK |
2,5 |
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Last data in to new col.address delay |
tCDL(min) |
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1 |
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CLK |
2 |
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Last data in to burst stop |
tBDL(min) |
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1 |
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CLK |
2 |
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Col. address to col. address delay |
tCCD(min) |
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1 |
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CLK |
3 |
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Mode Register Set cycle time |
tMRS(min) |
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2 |
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CLK |
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Number of valid output data |
CAS Latency=3 |
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2 |
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ea |
4 |
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CAS Latency=2 |
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1 |
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Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
- 7 - |
REV. 1.1 Mar. '99 |
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KM432S2030C |
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CMOS SDRAM |
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Symbol |
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Version |
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Unit |
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-6 |
-7 |
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-8 |
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-10 |
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CL |
3 |
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- |
3 |
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- |
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3 |
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2 |
3 |
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2 |
CLK |
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tCC(min) |
6 |
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- |
7 |
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- |
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8 |
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10 |
10 |
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12 |
ns |
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tRRD(min) |
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2 |
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CLK |
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tRCD(min) |
3 |
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- |
3 |
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- |
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3 |
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2 |
2 |
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2 |
CLK |
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tRP(min) |
3 |
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- |
3 |
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- |
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3 |
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2 |
2 |
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2 |
CLK |
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tRAS(min) |
7 |
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- |
7 |
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6 |
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5 |
5 |
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4 |
CLK |
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tRAS(max) |
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100 |
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us |
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tRC(min) |
11 |
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- |
10 |
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- |
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9 |
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7 |
7 |
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6 |
CLK |
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2.Minimum delay is required to complete write.
3.All parts allow every cycle column address change.
4.In case of row precharge interrupt, auto precharge and read burst stop.
5.For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter |
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Symbol |
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-6 |
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-7 |
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-8 |
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-10 |
Unit |
Note |
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Min |
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Max |
Min |
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Max |
Min |
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Max |
Min |
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Max |
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CLK cycle time |
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CAS Latency=3 |
tCC |
6 |
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1000 |
7 |
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1000 |
8 |
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1000 |
10 |
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1000 |
ns |
1 |
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CAS Latency=2 |
- |
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- |
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10 |
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12 |
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CLK to valid |
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CAS Latency=3 |
tSAC |
- |
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5.5 |
- |
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5.5 |
- |
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6 |
- |
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7 |
ns |
1, 2 |
output delay |
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CAS Latency=2 |
- |
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- |
- |
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- |
- |
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7 |
- |
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8 |
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Output data |
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tOH |
2.5 |
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- |
2.5 |
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- |
2.5 |
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- |
2.5 |
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- |
ns |
2 |
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CLK high pulse width |
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CAS Latency=3 |
tCH |
2.5 |
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- |
3 |
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- |
3 |
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- |
3.5 |
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- |
ns |
3 |
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CAS Latency=2 |
- |
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CLK low pulse width |
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CAS Latency=3 |
tCL |
2.5 |
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- |
3 |
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- |
3 |
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- |
3.5 |
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- |
ns |
3 |
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CAS Latency=2 |
- |
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Input setup time |
|
CAS Latency=3 |
tSS |
1.5 |
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- |
1.75 |
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- |
2 |
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- |
2.5 |
|
- |
ns |
3 |
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CAS Latency=2 |
- |
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- |
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Input hold time |
|
tSH |
1 |
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- |
1 |
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- |
1 |
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- |
1 |
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- |
ns |
3 |
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CLK to output in Low-Z |
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tSLZ |
1 |
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- |
1 |
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- |
1 |
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- |
1 |
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- |
ns |
2 |
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CLK to output |
|
CAS Latency=3 |
tSHZ |
- |
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5.5 |
- |
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5.5 |
- |
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6 |
- |
|
7 |
ns |
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in Hi-Z |
|
CAS Latency=2 |
- |
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- |
- |
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- |
- |
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7 |
- |
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8 |
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Note : 1. Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
- 8 - |
REV. 1.1 Mar. '99 |
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KM432S2030C |
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CMOS SDRAM |
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SIMPLIFIED TRUTH TABLE |
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Command |
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, |
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CKEn-1 |
CKEn |
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CS |
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RAS |
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CAS |
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WE |
DQM |
BA0,1 |
A10/AP |
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Note |
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A9 ~ A0 |
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Register |
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Mode register set |
H |
X |
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L |
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L |
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L |
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X |
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OP code |
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1,2 |
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Auto refresh |
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H |
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L |
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L |
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H |
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X |
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3 |
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Refresh |
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Entry |
L |
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3 |
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Self |
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H |
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H |
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3 |
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refresh |
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Exit |
L |
H |
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X |
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X |
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Bank active & row addr. |
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H |
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H |
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H |
X |
V |
Row address |
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Read & |
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Auto precharge disable |
H |
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H |
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X |
V |
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Column |
4 |
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column address |
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address |
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Auto precharge enable |
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H |
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(A0 ~ A7) |
4,5 |
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Write & |
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Auto precharge disable |
H |
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L |
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H |
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L |
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X |
V |
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Column |
4 |
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column address |
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address |
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Auto precharge enable |
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H |
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(A0 ~ A7) |
4,5 |
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Burst Stop |
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H |
X |
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L |
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H |
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H |
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L |
X |
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X |
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6 |
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Precharge |
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Bank selection |
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H |
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L |
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L |
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H |
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X |
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All banks |
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X |
H |
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Entry |
H |
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X |
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Clock suspend or |
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X |
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V |
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active power down |
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Exit |
L |
H |
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X |
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X |
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X |
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X |
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Entry |
H |
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Precharge power down mode |
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L |
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H |
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H |
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X |
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Exit |
L |
H |
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H |
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X |
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X |
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X |
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L |
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DQM |
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H |
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X |
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V |
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7 |
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No operation command |
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H |
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X |
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X |
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X |
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L |
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H |
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H |
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H |
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(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Notes :1. OP Code : Operand code
A0 ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.
4.BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5.During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
- 9 - |
REV. 1.1 Mar. '99 |
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KM432S2030C |
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CMOS SDRAM |
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MODE REGISTER FIELD TABLE TO PROGRAM MODES |
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Register Programmed with MRS |
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Address |
BA0 ~ BA1 |
A10/AP |
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A9 |
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A8 |
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A7 |
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A6 |
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A5 |
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A4 |
A3 |
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A2 |
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A1 |
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A0 |
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Function |
RFU |
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RFU |
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W.B.L |
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TM |
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CAS Latency |
BT |
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Burst Length |
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Test Mode |
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CAS Latency |
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Burst Type |
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Burst Length |
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A8 |
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A7 |
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Type |
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A6 |
A5 |
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A4 |
Latency |
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A3 |
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Type |
A2 |
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A1 |
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BT = 0 |
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BT = 1 |
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0 |
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0 |
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Mode Register Set |
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0 |
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0 |
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Reserved |
0 |
Sequential |
0 |
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0 |
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0 |
1 |
1 |
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0 |
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1 |
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Reserved |
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0 |
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1 |
Reserved |
1 |
Interleave |
0 |
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0 |
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1 |
2 |
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Reserved |
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0 |
4 |
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1 |
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Reserved |
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3 |
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8 |
8 |
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Write Burst Length |
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0 |
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Reserved |
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1 |
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Reserved |
Reserved |
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A9 |
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Length |
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1 |
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0 |
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Reserved |
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1 |
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Reserved |
Reserved |
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0 |
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Burst |
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Reserved |
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1 |
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0 |
Reserved |
Reserved |
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1 |
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Single Bit |
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Reserved |
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Full Page |
Reserved |
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Full Page Length : x32 (256) |
POWER UP SEQUENCE
1.Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle.
- 10 |
REV. 1.1 Mar. '99 |
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KM432S2030C |
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CMOS SDRAM |
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BURST SEQUENCE (BURST LENGTH = 4) |
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Initial Address |
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Sequential |
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Interleave |
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A1 |
A0 |
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0 |
0 |
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0 |
1 |
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2 |
3 |
0 |
1 |
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2 |
3 |
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0 |
1 |
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1 |
2 |
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3 |
0 |
1 |
0 |
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3 |
2 |
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1 |
0 |
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2 |
3 |
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0 |
1 |
2 |
3 |
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0 |
1 |
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1 |
1 |
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3 |
0 |
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1 |
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3 |
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0 |
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BURST SEQUENCE (BURST LENGTH = 8)
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Initial Address |
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Sequential |
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Interleave |
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A2 |
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A1 |
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A0 |
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0 |
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0 |
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0 |
0 |
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- 11 |
REV. 1.1 Mar. '99 |
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KM432S2030C |
CMOS SDRAM |
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are thesame as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.
BANK ADDRESSES (BA0 ~ BA1)
This SDRAM is organized as four independent banks of 524,288 words x 32 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A10)
The 19 address bits are required to decode the 524,288 word locations are multiplexed into 11 address input pins (A0 ~ A10). The 11 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS,
CAS, WE and all the address inputs are ignored.
POWER-UP
1.Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3.Issue precharge commands for both banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
- 12 |
REV. 1.1 Mar. '99 |
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KM432S2030C |
CMOS SDRAM |
DEVICE OPERATIONS (Continued)
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS,
RAS, CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ A10 and BA0 ~ BA1 in the same cycle as CS, RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on the fields of functions. The burst length field uses A0 ~ A2, burst type uses A3, CAS latency (read latency from column address) use A4 ~ A6, vendor specific options or test mode use A7 ~ A8, A10/AP and BA0 ~ BA1. The write burst length is programmed using A9. A7 ~ A8, A10/AP and BA0 ~ BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.
BANK ACTIVATE
The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be
active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS(max). The number of cycles for both tRAS(min) and tRAS(max) can be calculated similar to tRCD specification.
BURST READ
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be completed by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also.
- 13 |
REV. 1.1 Mar. '99 |
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