Samsung KM681002CLTI-15, KM681002CLTI-12, KM681002CLTI-10, KM681002CLT-20, KM681002CLT-15 Datasheet

KM681002C/CL, KM681002CI/CLI

CMOS SRAM

Document Title

128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.

Revision History

Rev.No. History

Rev. 0.0 Initial release with Preliminary.

Rev. 1.0 Release to Final Data Sheet. 1.1. Delete Preliminary.

2.2. Added Data Retention Characteristics.

Draft Data	Remark
Aug. 5. 1998	Preliminary
Mar. 3. 1999	Final

Rev. 2.0

Add 10ns part.

Mar. 3. 2000

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

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Revision 2.0

March 2000

KM681002C/CL, KM681002CI/CLI

CMOS SRAM

128K x 8 Bit High-Speed CMOS Static RAM(5.0V Operating)

FEATURES

•Fast Access Time 10,12,15,20ns(Max.)

•Low Power Dissipation

Standby (TTL) : 30mA(Max.) (CMOS) : 5mA(Max.)

0.5mA(Max.) L-ver. only Operating KM681002C/CL-10 : 80mA(Max.)

KM681002C/CL-12 : 75mA(Max.) KM681002C/CL-15 : 73mA(Max.) KM681002C/CL-20 : 70mA(Max.)

•Single 5.0V±10% Power Supply

•TTL Compatible Inputs and Outputs

•I/O Compatible with 3.3V Device

•Fully Static Operation

-No Clock or Refresh required

•Three State Outputs

•2V Minimum Data Retention; L-ver. only

•Center Power/Ground Pin Configuration

•Standard Pin Configuration

KM681002C/CLJ : 32-SOJ-400

KM681002C/CLT : 32-TSOP2-400CF

FUNCTIONAL BLOCK DIAGRAM

A0				Clk Gen.					Pre-Charge Circuit
A1
A2							Select
A4										512 Rows
A3							Row			Memory Array
A5									256x8 Columns
A6

	A7
	A8
	I/O1~I/O8	Data	I/O Circuit
		Cont.	Column Select
		CLK
		Gen.
		A9	A10 A11 A12 A13 A14 A15 A16
	CS
	WE
	OE

GENERAL DESCRIPTION

The KM681002C is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681002C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681002C is packaged in a 400mil 32-pin plastic SOJ or TSOP2 forward.

ORDERING INFORMATION

KM681002C/CL-10/12/15/20	Commercial Temp.
KM681002CI/CLI-10/12/15/20	Industrial Temp.

PIN CONFIGURATION(Top View)

		A0		1		32	A16
		A1		2		31	A15
		A2		3		30	A14
		A3		4		29	A13
	CS			5		28		OE
	I/O1			6		27	I/O8
	I/O2						I/O7
				7		26
	Vcc						Vss
				8	SOJ/	25
	Vss						Vcc
				9	TSOP2	24
	I/O3			10		23	I/O6
	I/O4						I/O5
				11		22
	WE			12		21	A12
		A4					A11
				13		20
		A5		14		19	A10
		A6		15		18		A9
		A7		16		17		A8

PIN FUNCTION

Pin Name				Pin Function
A0 - A16				Address Inputs
	WE			Write Enable
	CS			Chip Select
	OE			Output Enable
I/O1 ~ I/O8				Data Inputs/Outputs
VCC				Power(+5.0V)
VSS				Ground
N.C				No Connection

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Revision 2.0

March 2000

KM681002C/CL, KM681002CI/CLI				CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter		Symbol	Rating		Unit
Voltage on Any Pin Relative to VSS		VIN, VOUT	-0.5 to Vcc+0.5V		V
Voltage on VCC Supply Relative to VSS		VCC	-0.5 to 7.0		V
Power Dissipation		Pd	1		W
Storage Temperature		TSTG	-65 to 150		°C
Operating Temperature	Commercial	TA	0 to 70		°C
	Industrial	TA	-40 to 85		°C

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage	VCC	4.5	5.0	5.5	V
Ground	VSS	0	0	0	V
Input High Voltage	VIH	2.2	-	VCC + 0.5***	V
Input Low Voltage	VIL	-0.5**	-	0.8	V

*The above parameters are also guaranteed at industrial temperature range.

**VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.

***VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.

DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Max

Unit

Input Leakage Current

ILI

VIN = VSS to VCC

-2

2

mA

mA

Output Leakage Current

ILO

CS=VIH or OE=VIH or WE=VIL

-2

2

VOUT=VSS to VCC

Operating Current

ICC

Min. Cycle, 100% Duty

10ns

-

80

mA

CS=VIL, VIN=VIH or VIL,

12ns

-

75

IOUT=0mA

15ns

-

73

20ns

-

70

Standby Current

ISB

Min. Cycle, CS=VIH

-

30

mA

ISB1

f=0MHz,

CS

³VCC-0.2V,

Normal

-

5

mA

VIN³VCC-0.2V or VIN£0.2V

L-ver.

-

0.5

Output Low Voltage Level

VOL

IOL=8mA

-

0.4

V

Output High Voltage Level

VOH

IOH=-4mA

2.4

-

V

VOH1**

IOH1=-0.1mA

-

3.95

V

*The above parameters are also guaranteed at industrial temperature range.

**VCC=5.0V±5%, Temp.=25°C.

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item	Symbol	Test Conditions	MIN	Max	Unit
Input/Output Capacitance	CI/O	VI/O=0V	-	8	pF
Input Capacitance	CIN	VIN=0V	-	6	pF

* Capacitance is sampled and not 100% tested.

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Revision 2.0

March 2000