K9F2808Q0C-DCB0,DIB0 |
K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0 |
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K9F2808U0C-YCB0,YIB0 |
K9F2816U0C-YCB0,YIB0 |
FLASH MEMORY |
K9F2808U0C-DCB0,DIB0 |
K9F2816U0C-DCB0,DIB0 |
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Document Title
16M x 8 Bit , 8M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
0.0Initial issue.
1.0TBGA PKG Dimension Change
48-Ball, 6.0mm x 8.5mm --> 63-Ball, 9.0mm x 11.0mm
2.01.A3 Pin assignment of TBGA Package is changed.(Page 4) (before) NC --> (after) Vss
2.Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 32)
3.Add the data protection Vcc guidence for 1.8V device - below about 1.1V. (Page 33)
2.1The min. Vcc value 1.8V devices is changed. K9F28XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V
Pb-free Package is added.
2.2
K9F2808U0C-FCB0,FIB0
K9F2808Q0C-HCB0,HIB0
K9F2816U0C-HCB0,HIB0
K9F2816U0C-PCB0,PIB0
K9F2816Q0C-HCB0,HIB0
K9F2808U0C-HCB0,HIB0
K9F2808U0C-PCB0,PIB0
Some AC parameter is changed(K9F28XXQ0C).
2.3
tWC tWH tWP tRC tREH tRP tREA tCEA
Before |
45 |
15 |
25 |
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15 |
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45 |
After |
60 |
20 |
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55 |
Draft Date |
Remark |
Apr. 15th 2002 |
Advance |
Sep. 5th 2002 |
Advance |
Dec.10th 2002 |
Preliminary |
Mar. 6th 2003
Mar. 13rd 2003
Mar. 26th 2003
2.4 New definition of the number of invalid blocks is added. May. 24th 2003
(Minimum 502 valid blocks are guaranteed for each contiguous 64Mb memory space)
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.
1
K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0 |
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K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 |
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FLASH MEMORY |
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K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 |
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16M x 8 Bit / 8M x 16 Bit NAND Flash Memory |
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PRODUCT LIST |
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Part Number |
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Vcc Range |
Organization |
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PKG Type |
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K9F2808Q0C-D,H |
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1.7 ~ 1.95V |
X8 |
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TBGA |
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K9F2816Q0C-D,H |
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X16 |
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K9F2808U0C-Y,P |
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TSOP1 |
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K9F2808U0C-D,H |
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X8 |
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TBGA |
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K9F2808U0C-V,F |
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2.7 ~ 3.6V |
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WSOP1 |
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K9F2816U0C-Y,P |
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X16 |
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TSOP1 |
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K9F2816U0C-D,H |
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TBGA |
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FEATURES |
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∙ Voltage Supply |
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∙ Fast Write Cycle Time |
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- 1.8V device(K9F28XXQ0C) : 1.7~1.95V |
- Program time : 200μs(Typ.) |
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- 3.3V device(K9F28XXU0C) : 2.7 ~ 3.6 V |
- Block Erase Time : 2ms(Typ.) |
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∙ Organization |
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∙ Command/Address/Data Multiplexed I/O Port |
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- Memory Cell Array |
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∙ Hardware Data Protection |
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- X8 device(K9F2808X0C) : (16M + 512K)bit x 8bit |
- Program/Erase Lockout During Power Transitions |
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- X16 device(K9F2816X0C) : (8M + |
256K)bit x 16bit |
∙ Reliable CMOS Floating-Gate Technology |
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- Data Register |
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- Endurance |
: 100K Program/Erase Cycles |
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- X8 device(K9F2808X0C) : (512 + 16)bit x 8bit |
- Data Retention : 10 Years |
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- X16 device(K9F2816X0C) : (256 + |
8)bit x16bit |
∙ Command Register Operation |
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∙ Automatic Program and Erase |
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∙ Unique ID for Copyright Protection |
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- Page Program |
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∙ Package |
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- X8 device(K9F2808X0C) : (512 + 16)Byte |
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- K9F28XXU0C-YCB0/YIB0 |
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- X16 device(K9F2816X0C) : (256 + |
8)Word |
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48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) |
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- Block Erase : |
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- K9F28XXU0C-PCB0/PIB0 |
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- X8 device(K9F2808X0C) : (16K + 512)Byte |
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48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - Pb-free Package |
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- X16 device(K9F2816X0C) : ( 8K + 256)Word |
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- K9F28XXX0C-DCB0/DIB0 |
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∙ Page Read Operation |
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63 - Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm) |
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- Page Size |
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- X8 device(K9F2808X0C) : (512 + 16)Byte |
- K9F28XXX0C-HCB0/HIB0 |
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- X16 device(K9F2816X0C) : (256 + |
8)Word |
63 - Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm) |
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- Random Access : 10μs(Max.) |
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- Pb-free Package |
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- Serial Page Access : 50ns(Min.) |
- K9F2808U0C-VCB0/VIB0 |
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48 - Pin WSOP I (12X17X0.7mm) |
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- K9F2808U0C-FCB0/FIB0 |
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48 - Pin WSOP I (12X17X0.7mm) - Pb-free Package |
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* K9F2808U0C-V/F(WSOPI ) is the same device as |
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K9F2808U0C-Y/P(TSOP1) except package type. |
GENERAL DESCRIPTION
Offered in 16Mx8bit or 8Mx16bit, the K9F28XXX0C is 128M bit with spare 4M bit capacity. The device is offered in 1.8V or 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200μs on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns cycle time per word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the writeintensive systems can take advantage of the K9F28XXX0C’s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F28XXX0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
2
K9F2808Q0C-DCB0,DIB0 |
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K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0 |
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K9F2808U0C-YCB0,YIB0 |
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K9F2816U0C-YCB0,YIB0 |
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FLASH MEMORY |
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K9F2808U0C-DCB0,DIB0 |
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K9F2816U0C-DCB0,DIB0 |
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PIN CONFIGURATION (TSOP1) |
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K9F28XXU0C-YCB0,PCB0/YIB0,PIB0 |
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X16 |
X8 |
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X8 |
X16 |
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N.C |
N.C |
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N.C |
Vss |
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1 |
48 |
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N.C |
N.C |
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2 |
47 |
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N.C |
I/O15 |
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N.C |
N.C |
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3 |
46 |
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N.C |
I/O7 |
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N.C |
N.C |
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4 |
45 |
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N.C |
I/O14 |
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N.C |
N.C |
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5 |
44 |
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I/O7 |
I/O6 |
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GND |
GND |
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6 |
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I/O6 |
I/O13 |
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R/B |
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R/B |
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I/O5 |
I/O5 |
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RE |
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RE |
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I/O4 |
I/O12 |
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CE |
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CE |
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N.C |
I/O4 |
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N.C |
N.C |
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10 |
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N.C |
N.C |
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N.C |
N.C |
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11 |
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N.C |
N.C |
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Vcc |
Vcc |
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12 |
37 |
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Vcc |
Vcc |
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Vss |
Vss |
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13 |
36 |
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Vss |
N.C |
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N.C |
N.C |
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14 |
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N.C |
N.C |
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N.C |
N.C |
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N.C |
N.C |
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CLE |
CLE |
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16 |
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N.C |
I/O11 |
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ALE |
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ALE |
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I/O3 |
I/O3 |
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WE |
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WE |
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I/O2 |
I/O10 |
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WP |
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WP |
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I/O1 |
I/O2 |
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N.C |
N.C |
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20 |
29 |
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I/O0 |
I/O9 |
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N.C |
N.C |
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21 |
28 |
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N.C |
I/O1 |
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N.C |
N.C |
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22 |
27 |
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N.C |
I/O8 |
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N.C |
N.C |
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23 |
26 |
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N.C |
I/O0 |
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N.C |
N.C |
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24 |
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N.C |
Vss |
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PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
+0.07 0.03- |
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+0.003 0.001- |
#1 |
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0.20 |
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0.008 |
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0.50 |
0.0197 |
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#24
0~8°
TYP |
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0.25 |
0.010 |
20.00±0.20
0.787±0.008
18.40±0.10
0.724±0.004
Unit :mm/Inch
MAX |
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0.10 |
0.004 |
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#48
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0.25 |
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0.010 |
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MAX |
12.00 |
0.472 |
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12.40 |
0.488 |
#25 |
1.00±0.05 |
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0.05 |
MIN |
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0.039±0.002 |
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0.002 |
+0.075 0.035 |
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+0.003 0.001- |
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1.20 |
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0.047MAX |
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0.125 |
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0.005 |
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0.45~0.75 |
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0.50 |
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( |
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0.018~0.030 |
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0.020 |
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3
K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0 |
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K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 |
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FLASH MEMORY |
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K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 |
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PIN CONFIGURATION (TBGA) |
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X8 |
K9F28XXX0C-DCB0,HCB0/DIB0,HIB0 |
X16 |
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NC |
NC |
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NC |
NC |
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DNU DNU |
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NC |
NC |
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NC |
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NC |
NC |
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DNU |
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NC |
NC |
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/WP |
ALE |
Vss |
/CE |
/WE |
R/B |
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/WP |
ALE |
Vss |
/CE |
/WE |
R/B |
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NC |
/RE |
CLE |
NC |
NC |
NC |
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NC |
/RE |
CLE |
NC |
NC |
NC |
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NC |
NC |
NC |
NC |
NC |
NC |
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NC |
NC |
NC |
NC |
NC |
NC |
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NC |
NC |
NC |
NC |
NC |
NC |
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NC |
NC |
NC |
NC |
NC |
NC |
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NC |
NC |
NC |
NC |
NC |
NC |
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NC |
NC |
NC |
I/O5 |
I/O7 |
NC |
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NC |
I/O0 |
NC |
NC |
NC |
Vcc |
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I/O8 |
I/O1 |
I/O10 |
I/O12 |
IO14 |
Vcc |
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NC |
I/O1 |
NC |
VccQ |
I/O5 |
I/O7 |
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I/O0 |
I/O9 I/O3 VccQ I/O6 I/O15 |
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Vss |
I/O2 |
I/O3 |
I/O4 |
I/O6 |
Vss |
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Vss |
I/O2 |
I/O11 I/O4 |
I/O13 |
Vss |
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NC |
NC |
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NC |
NC |
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NC |
NC |
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NC |
NC |
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NC |
NC |
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NC |
NC |
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NC |
NC |
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NC |
NC |
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(Top View) |
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(Top View) |
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PACKAGE DIMENSIONS
63-Ball TBGA (measured in millimeters)
Top View |
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Bottom View |
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9.00±0.10 |
#A1
11.00±0.10
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9.00±0.10 |
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A |
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0.80 |
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x9= |
7.20 |
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x5= |
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0.80 |
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4.00 |
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0.80 |
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B |
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(Datum A) |
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6 5 |
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4 |
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3 2 |
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1 |
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A |
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0.80 |
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(Datum B) |
B |
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C |
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x7=0.805.60 |
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x11=0.808.80 |
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2.80 |
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D |
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11.000.10± |
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E |
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F |
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G |
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H |
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63- 0.45±0.05
0.20 M A B |
2.00 |
|
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Side View |
±0.05 |
|
±0.10 |
|
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||||||||
9.00±0.10 |
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0.32 |
|
0.90 |
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0.08MAX |
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0.45±0.05 |
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4
K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0
K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 |
|
|
FLASH MEMORY |
||||||
|
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|
|
PIN CONFIGURATION (WSOP1) |
|
|
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||||||
|
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|
K9F2808U0C-VCB0,FCB0/VIB0,FIB0 |
|
|
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N.C |
N.C |
|
1 |
48 |
|
|||||
|
|
||||||||
N.C |
|
2 |
47 |
|
N.C |
||||
|
|
||||||||
DNU |
|
3 |
46 |
|
DNU |
||||
|
|
||||||||
N.C |
|
4 |
45 |
|
N.C |
||||
|
|
||||||||
N.C |
|
5 |
44 |
|
I/O7 |
||||
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||||||||
N.C |
|
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6 |
43 |
|
I/O6 |
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R/B |
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7 |
42 |
|
I/O5 |
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|||||||
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RE |
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8 |
41 |
|
I/O4 |
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|||||||
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CE |
|
9 |
40 |
|
N.C |
||
|
|
||||||||
DNU |
|
10 |
39 |
|
DNU |
||||
|
|
||||||||
N.C |
|
11 |
38 |
|
N.C |
||||
|
|
||||||||
Vcc |
|
12 |
37 |
|
Vcc |
||||
|
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||||||||
Vss |
|
13 |
36 |
|
Vss |
||||
|
|
||||||||
N.C |
|
14 |
35 |
|
N.C |
||||
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|
||||||||
DNU |
|
15 |
34 |
|
DNU |
||||
|
|
||||||||
CLE |
|
16 |
33 |
|
N.C |
||||
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||||||||
|
ALE |
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|
17 |
32 |
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I/O3 |
||
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||||||||
|
WE |
|
|
18 |
31 |
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I/O2 |
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||||||||
|
WP |
|
19 |
30 |
|
I/O1 |
|||
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||||||||
N.C |
|
20 |
29 |
|
I/O0 |
||||
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||||||||
N.C |
|
21 |
28 |
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N.C |
||||
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|
||||||||
DNU |
|
22 |
27 |
|
DNU |
||||
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|
||||||||
N.C |
|
23 |
26 |
|
N.C |
||||
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|
||||||||
N.C |
|
24 |
25 |
|
N.C |
||||
|
|
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F |
|
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Unit :mm |
|||
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0.70 MAX |
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|||||||
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15.40±0.10 |
0.58±0.04 |
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#1 |
#48 |
+0.07 |
-0.03 |
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0.16 |
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||
+0.07 |
-0.03 |
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0.20 |
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0.50TYP |
(0.50±0.06) |
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#24 |
#25 |
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(0.1Min) |
10.0±00.12
+0.075 -0.035
0.10 |
0 |
° |
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~ |
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8 |
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° |
0.45~0.75
17.00±0.20
5
K9F2808Q0C-DCB0,DIB0 |
K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0 |
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K9F2808U0C-YCB0,YIB0 |
K9F2816U0C-YCB0,YIB0 |
FLASH MEMORY |
K9F2808U0C-DCB0,DIB0 |
K9F2816U0C-DCB0,DIB0 |
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PIN DESCRIPTION
Pin Name |
Pin Function |
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DATA INPUTS/OUTPUTS |
I/O0 ~ I/O7 |
The I/O pins are used to input command, address and data, and to output data during read operations. The |
(K9F2808X0C) |
I/O pins float to high-z when the chip is deselected or when the outputs are disabled. |
I/O0 ~ I/O15 |
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper- |
(K9F2816X0C) |
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and |
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output. |
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COMMAND LATCH ENABLE |
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CLE |
The CLE input controls the activating path for commands sent to the command register. When active high, |
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commands are latched into the command register through the I/O ports on the rising edge of the WE signal. |
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ADDRESS LATCH ENABLE |
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ALE |
The ALE input controls the activating path for address to the internal address registers. Addresses are |
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latched on the rising edge of WE with ALE high. |
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CHIP ENABLE |
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The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and |
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CE |
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the device does not return to standby mode in program or erase opertion. Regarding CE control during read |
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operation, refer to ’Page read’section of Device operation . |
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READ ENABLE |
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RE |
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid |
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tREA after the falling edge of RE which also increments the internal column address counter by one. |
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WRITE ENABLE |
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WE |
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of |
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the WE pulse. |
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WRITE PROTECT |
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WP |
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage |
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generator is reset when the WP pin is active low. |
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READY/BUSY OUTPUT |
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The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or |
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R/B |
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random read operation is in process and returns to high state upon completion. It is an open drain output and |
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does not float to high-z condition when the chip is deselected or when outputs are disabled. |
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OUTPUT BUFFER POWER |
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VccQ |
VCCQ is the power supply for Output Buffer. |
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VccQ is internally connected to Vcc, thus should be biased to Vcc. |
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Vcc |
POWER |
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VCC is the power supply for device. |
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Vss |
GROUND |
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N.C |
NO CONNECTION |
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Lead is not internally connected. |
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GND INPUT FOR ENABLING SPARE AREA |
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GND |
To do sequential read mode including spare area , connect this input pin to Vss or set to static low state |
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or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state. |
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DNU |
DO NOT USE |
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Leave it disconnected. |
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NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
6
K9F2808Q0C-DCB0,DIB0 |
K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0 |
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K9F2808U0C-YCB0,YIB0 |
K9F2816U0C-YCB0,YIB0 |
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FLASH MEMORY |
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K9F2808U0C-DCB0,DIB0 |
K9F2816U0C-DCB0,DIB0 |
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Figure 1-1. K9F2808X0C (X8) FUNCTIONAL BLOCK DIAGRAM |
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VCC |
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VSS |
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A9 - A23 |
X-Buffers |
128M + 4M Bit |
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Latches |
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& Decoders |
NAND Flash |
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ARRAY |
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A0 - A7 |
Y-Buffers |
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Latches |
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& Decoders |
(512 + 16)Byte x 32768 |
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Page Register & S/A |
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A8 |
Y-Gating |
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Command |
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Command |
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Register |
I/O Buffers & Latches |
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VCC/VCCQ |
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VSS |
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CE |
Control Logic |
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RE |
& High Voltage |
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Output |
I/0 0 |
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WE |
Generator |
Global Buffers |
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Driver |
I/0 7 |
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CLE ALE WP |
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Figure 2-1. K9F2808X0C (X8) ARRAY ORGANIZATION |
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32K Pages
(=1,024 Blocks)
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1 Block =32 Pages |
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= (16K + 512) Byte |
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1 |
Page = 528 Byte |
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1 |
Block = 528 Byte x 32 Pages |
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1st half Page Register |
2nd half Page Register |
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= (16K + 512) Byte |
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1 |
Device = 528Bytes x 32Pages x 1024 Blocks |
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(=256 Bytes) |
(=256 Bytes) |
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= 132 Mbits |
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8 bit |
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512Byte |
16 Byte |
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I/O 0 ~ I/O 7
Page Register
512 Byte |
16 Byte |
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I/O 0 |
I/O 1 |
I/O 2 |
I/O 3 |
I/O 4 |
I/O 5 |
I/O 6 |
I/O 7 |
1st Cycle |
A0 |
A1 |
A2 |
A3 |
A4 |
A5 |
A6 |
A7 |
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2nd Cycle |
A9 |
A10 |
A11 |
A12 |
A13 |
A14 |
A15 |
A16 |
3rd Cycle |
A17 |
A18 |
A19 |
A20 |
A21 |
A22 |
A23 |
L* |
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register.
*A8 is set to "Low" or "High" by the 00h or 01h Command.
*The device ignores any additional input of address cycles than reguired.
*L must be set to "Low".
Column Address
Row Address
(Page Address)
7
K9F2808Q0C-DCB0,DIB0 |
K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0 |
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K9F2808U0C-YCB0,YIB0 |
K9F2816U0C-YCB0,YIB0 |
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FLASH MEMORY |
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K9F2808U0C-DCB0,DIB0 |
K9F2816U0C-DCB0,DIB0 |
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Figure 1-2. K9F2816X0C (X16) FUNCTIONAL BLOCK DIAGRAM |
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VCC |
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VSS |
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A9 - A23 |
X-Buffers |
128M + 4M Bit |
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Latches |
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& Decoders |
NAND Flash |
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ARRAY |
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A0 - A7 |
Y-Buffers |
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Latches |
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& Decoders |
(256 + 8)Word x 32768 |
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Page Register & S/A |
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Command |
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Y-Gating |
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Command |
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Register |
I/O Buffers & Latches |
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VCC/VCCQ |
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VSS |
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CE |
Control Logic |
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RE |
& High Voltage |
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Output |
I/0 0 |
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WE |
Generator |
Global Buffers |
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Driver |
I/0 15 |
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CLE ALE WP |
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Figure 2-2. K9F2816X0C (X16) ARRAY ORGANIZATION |
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32K Pages
(=1,024 Blocks)
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1 Block =32 Pages |
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= (8K + 256) Word |
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1 Page = 264 Word |
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1 Block = 264 Word x 32 Pages |
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Page Register |
= (8K + 256) Word |
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1 Device = 264Words x 32Pages x 1024 Blocks |
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(=256 Words) |
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= 132 Mbits |
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16 bit |
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256Word |
8 Word |
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I/O 0 ~ I/O 15 |
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Page Register |
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256 Word |
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8 Word |
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I/O 0 |
I/O 1 |
I/O 2 |
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I/O 3 |
I/O 4 |
I/O 5 |
I/O 6 |
I/O 7 |
I/O8 to 15 |
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1st Cycle |
A0 |
A1 |
A2 |
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A3 |
A4 |
A5 |
A6 |
A7 |
L* |
Column Address |
2nd Cycle |
A9 |
A10 |
A11 |
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A12 |
A13 |
A14 |
A15 |
A16 |
L* |
Row Address |
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(Page Address) |
3rd Cycle |
A17 |
A18 |
A19 |
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A20 |
A21 |
A22 |
A23 |
L* |
L* |
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NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
8
K9F2808Q0C-DCB0,DIB0 |
K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0 |
|
K9F2808U0C-YCB0,YIB0 |
K9F2816U0C-YCB0,YIB0 |
FLASH MEMORY |
K9F2808U0C-DCB0,DIB0 |
K9F2816U0C-DCB0,DIB0 |
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PRODUCT INTRODUCTION
The K9F28XXX0C is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528(X8 device) or 264(X16 device) columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8 device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structures. A NAND structure consists of 16 cells. Total 16896 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1024 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase operation is prohibited on the K9F28XXX0C.
The K9F28XXX0C has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). K9F2816X0C allows sixteen bit wide data transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O’s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other commands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution. The 16K-byte(X8 device) or 32K-word(X16 device) physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F28XXX0C.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
Function |
|
1st. Cycle |
2nd. Cycle |
Acceptable Command during Busy |
Read 1 |
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00h/01h(1) |
- |
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Read 2 |
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50h |
- |
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Read ID |
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90h |
- |
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Reset |
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FFh |
- |
O |
Page Program |
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80h |
10h |
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Block Erase |
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60h |
D0h |
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Read Status |
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70h |
- |
O |
NOTE: 1. The 00h command defines starting address of the 1st half of registers. |
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The 01h command defines starting address of the 2nd half of registers. |
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After data access on |
2nd half of register by the 01h command, start pointer is automatically moved to |
1st half register(00h) on the next cycle.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
9
K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0 |
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K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 |
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FLASH MEMORY |
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K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 |
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ABSOLUTE MAXIMUM RATINGS |
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Parameter |
Symbol |
Rating |
Unit |
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K9F28XXQ0C(1.8V) |
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K9F28XXU0C(3.3V) |
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VIN/OUT |
-0.6 to + 2.45 |
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-0.6 to + 4.6 |
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Voltage on any pin relative to VSS |
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V |
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VCC |
-0.2 to + 2.45 |
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-0.6 to + 4.6 |
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VCCQ |
-0.2 to + 2.45 |
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-0.6 to + 4.6 |
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Temperature Under Bias |
K9F28XXX0C-XCB0 |
TBIAS |
-10 to +125 |
°C |
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K9F28XXX0C-XIB0 |
-40 to +125 |
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Storage Temperature |
K9F28XXX0C-XCB0 |
TSTG |
-65 to +150 |
°C |
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K9F28XXX0C-XIB0 |
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Short Circuit Current |
Ios |
5 |
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mA |
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NOTE :
1.Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F28XXX0C-XCB0 :TA=0 to 70°C, K9F28XXX0C-XIB0:TA=-40 to 85°C)
Parameter |
Symbol |
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K9F28XXQ0C(1.8V) |
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K9F28XXU0C(3.3V) |
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Unit |
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Min |
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Typ. |
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Max |
Min |
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Typ. |
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Max |
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Supply Voltage |
VCC |
1.7 |
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1.8 |
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1.95 |
2.7 |
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3.3 |
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3.6 |
V |
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Supply Voltage |
VCCQ |
1.7 |
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1.8 |
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1.95 |
2.7 |
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3.3 |
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3.6 |
V |
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Supply Voltage |
VSS |
0 |
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0 |
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0 |
0 |
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0 |
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0 |
V |
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DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
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Parameter |
Symbol |
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Test Conditions |
K9F28XXQ0C(1.8V) |
K9F28XXU0C(3.3V) |
Unit |
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Min |
Typ |
Max |
Min |
Typ |
Max |
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Operat- |
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Sequential Read |
ICC1 |
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tRC=50ns, CE=VIL |
- |
8 |
15 |
- |
10 |
20 |
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IOUT=0mA |
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Current |
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Program |
ICC2 |
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- |
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- |
8 |
15 |
- |
10 |
20 |
mA |
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Erase |
ICC3 |
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- |
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8 |
15 |
- |
10 |
20 |
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Stand-by Current(TTL) |
ISB1 |
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CE=VIH, WP=0V/VCC |
- |
- |
1 |
- |
- |
1 |
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Stand-by Current(CMOS) |
ISB2 |
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CE=VCC-0.2, WP=0V/VCC |
- |
10 |
50 |
- |
10 |
50 |
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Input Leakage Current |
ILI |
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VIN=0 to Vcc(max) |
- |
- |
±10 |
- |
- |
±10 |
μ |
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A |
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Output Leakage Current |
ILO |
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VOUT=0 to Vcc(max) |
- |
- |
±10 |
- |
- |
±10 |
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I/O pins |
VCCQ-0.4 |
- |
VCCQ |
2.0 |
- |
VCCQ+0.3 |
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+0.3 |
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Input High Voltage |
VIH |
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Except I/O pins |
VCC-0.4 |
- |
VCC |
2.0 |
- |
VCC+0.3 |
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+0.3 |
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V |
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Input Low Voltage, All inputs |
VIL |
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- |
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-0.3 |
- |
0.4 |
-0.3 |
- |
0.8 |
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Output High Voltage Level |
VOH |
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K9F28XXQ0C :IOH=-100μA |
VCCQ-0.1 |
- |
- |
2.4 |
- |
- |
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K9F28XXU0C :IOH=-400μA |
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Output Low Voltage Level |
VOL |
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K9F28XXQ0C :IOL=100uA |
- |
- |
0.1 |
- |
- |
0.4 |
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K9F28XXU0C :IOL=2.1mA |
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K9F28XXQ0C :VOL=0.1V |
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Output Low Current(R/B) |
IOL(R/B) |
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3 |
4 |
- |
8 |
10 |
- |
mA |
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K9F28XXU0C :VOL=0.4V |
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10