Samsung K9F5616U0B-PIB0, K9F5616U0B-PCB0, K9F5616U0B-HIB0, K9F5616U0B-HCB0, K9F5616U0B-DIB0 Datasheet

K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0	K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0	K9F5616U0B-YCB0,YIB0,PCB0,PIB0	FLASH MEMORY
K9F5608U0B-DCB0,DIB0,HCB0,HIB0	K9F5616U0B-DCB0,DIB0,HCB0,HIB0

Document Title

32M x 8 Bit , 16M x 16 Bit NAND Flash Memory

Revision History

Revision No. History

Draft Date

Remark

0.0Initial issue.

0.1At Read2 operation in X16 device

: A3 ~ A7 are Don’t care ==> A3 ~ A7 are "L"

0.21. IOL(R/B) of 1.8V device is changed. -min. Value: 7mA -->3mA

-typ. Value: 8mA -->4mA

2.AC parameter is changed. tRP(min.) : 30ns --> 25ns

3.WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum

1μs is required before internal circuit gets ready for any command

sequences as shown in Figure 15.

---> WP pin provides hardware protection and is recommended to be

kept at VIL during power-up and power-down and recovery time of

minimum 10μs is required before internal circuit gets ready for any

command sequences as shown in Figure 15.

0.3

1. X16 TSOP1 pin is changed.

: #36 pin is changed from VccQ to N.C .

0.4

1. In X16 device, bad block information location is changed from 256th byte to 256th and 261th byte.

2.tAR1, tAR2 are merged to tAR.(page 12)

(before revision) min. tAR1 = 20ns , min. tAR2 = 50ns

(after revision) min. tAR = 10ns

3.min. tCLR is changed from 50ns to 10ns.(page12)

4.min. tREA is changed from 35ns to 30ns.(page12)

5.min. tWC is changed from 50ns to 45ns.(page12)

6.Unique ID for Copyright Protection is available

-The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung.

7.tRHZ is divide into tRHZ and tOH.(page 12)

-tRHZ : RE High to Output Hi-Z

-tOH : RE High to Output Hold

8.tCHZ is divide into tCHZ and tOH.(page 12)

-tCHZ : CE High to Output Hi-Z

-tOH : CE High to Output Hold

May. 15th 2001

Advance

Sep. 20th 2001

Nov. 5th 2001

Feb. 15th 2002

Apr. 15th 2002

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

1

K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0		K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0		K9F5616U0B-YCB0,YIB0,PCB0,PIB0	FLASH MEMORY
K9F5608U0B-DCB0,DIB0,HCB0,HIB0		K9F5616U0B-DCB0,DIB0,HCB0,HIB0
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
Revision No. History			Draft Date	Remark
0.5	1. Add the Rp vs tr ,tf &	Rp vs ibusy graph for 1.8V device (Page 33)	Nov. 22.2002
	2. Add the data protection Vcc guidence for 1.8V device - below about
	1.1V. (Page 34)
0.6	The min. Vcc value 1.8V devices is changed.		Mar. 6.2003
	K9F56XXQ0B : Vcc 1.65V~1.95V --> 1.70V~1.95V
0.7	Pb-free Package is added.		Mar. 13rd 2003
	K9F5608U0B-FCB0,FIB0
	K9F5608Q0B-HCB0,HIB0

K9F5616U0B-HCB0,HIB0

K9F5616U0B-PCB0,PIB0

K9F5616Q0B-HCB0,HIB0

K9F5608U0B-HCB0,HIB0

K9F5608U0B-PCB0,PIB0

0.8New definition of the number of invalid blocks is added.

(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.)

0.9Pin assignment of TBGA A3 ball is changed.

(before) N.C --> (after) Vss

Apr. 4th 2003

May. 24th 2003

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

2

K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0	K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0	K9F5616U0B-YCB0,YIB0,PCB0,PIB0	FLASH MEMORY
K9F5608U0B-DCB0,DIB0,HCB0,HIB0	K9F5616U0B-DCB0,DIB0,HCB0,HIB0

32M x 8 Bit / 16M x 16 Bit NAND Flash Memory

PRODUCT LIST

	Part Number	Vcc Range	Organization	PKG Type
	K9F5608Q0B-D,H	1.70 ~ 1.95V	X8	TBGA
	K9F5616Q0B-D,H		X16
	K9F5608U0B-Y,P			TSOP1
	K9F5608U0B-D,H		X8	TBGA
	K9F5608U0B-V,F	2.7 ~ 3.6V		WSOP1
	K9F5616U0B-Y,P		X16	TSOP1
	K9F5616U0B-D,H			TBGA

FEATURES

∙ Voltage Supply		∙ Fast Write Cycle Time
- 1.8V device(K9F56XXQ0B) : 1.70~1.95V		- Program time : 200μs(Typ.)
- 3.3V device(K9F56XXU0B) : 2.7 ~ 3.6 V		- Block Erase Time : 2ms(Typ.)
∙ Organization		∙ Command/Address/Data Multiplexed I/O Port
- Memory Cell Array		∙ Hardware Data Protection
- X8 device(K9F5608X0B) :	(32M + 1024K)bit x 8 bit	- Program/Erase Lockout During Power Transitions
- X16 device(K9F5616X0B) :	(16M + 512K)bit x 16bit	∙ Reliable CMOS Floating-Gate Technology
- Data Register		- Endurance	: 100K Program/Erase Cycles
- X8 device(K9F5608X0B) :	(512 + 16)bit x 8bit	- Data Retention : 10 Years
- X16 device(K9F5616X0B) :	(256 + 8)bit x16bit	∙ Command Register Operation
∙ Automatic Program and Erase		∙ Intelligent Copy-Back
- Page Program		∙ Unique ID for Copyright Protection
- X8 device(K9F5608X0B) :	(512 + 16)Byte	∙ Package
- X16 device(K9F5616X0B) :	(256 + 8)Word	- K9F56XXU0B-YCB0/YIB0
- Block Erase :		48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- X8 device(K9F5608X0B) :	(16K + 512)Byte	- K9F56XXX0B-DCB0/DIB0
- X16 device(K9F5616X0B) : ( 8K + 256)Word		63Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
∙ Page Read Operation		- K9F5608U0B-VCB0/VIB0
- Page Size		48 - Pin WSOP I (12X17X0.7mm)
- X8 device(K9F5608X0B) :	(512 + 16)Byte	- K9F56XXU0B-PCB0/PIB0
- X16 device(K9F5616X0B) :	(256 + 8)Word	48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - Pb-free Package
- Random Access : 10μs(Max.)		- K9F56XXX0B-HCB0/HIB0
- Serial Page Access : 50ns(Min.)		63Ball TBGA	( 9 x 11 /0.8mm pitch , Width 1.0 mm)
		- Pb-free Package
		- K9F5608U0B-FCB0/FIB0

48 - Pin WSOP I (12X17X0.7mm) - Pb-free Package * K9F5608U0B-V,F(WSOPI ) is the same device as

K9F5608U0B-Y,P(TSOP1) except package type.

GENERAL DESCRIPTION

Offered in 32Mx8bit or 16Mx16bit, the K9F56XXX0B is 256M bit with spare 8M bit capacity. The device is offered in 1.8V or 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200μs on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns cycle time per word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F56XXX0B′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.

The K9F56XXX0B is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

3

K9F5608U0B-VCB0,VIB0,FCB0,FIB0

K9F5608Q0B-DCB0,DIB0,HCB0,HIB0

K9F5616Q0B-DCB0,DIB0,HCB0,HIB0

K9F5608U0B-YCB0,YIB0,PCB0,PIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-DCB0,DIB0,HCB0,HIB0

PIN CONFIGURATION (TSOP1)

K9F56XXU0B-YCB0,PCB0/YIB0,PIB0

X16

X8

X8

X16

N.C

N.C

N.C

Vss

1

48

N.C

N.C

2

47

N.C

I/O15

N.C

N.C

3

46

N.C

I/O7

N.C

N.C

4

45

N.C

I/O14

N.C

N.C

5

44

I/O7

I/O6

GND

GND

6

43

I/O6

I/O13

R/B

R/B

7

42

I/O5

I/O5

RE

RE

8

41

I/O4

I/O12

CE

CE

9

40

N.C

I/O4

N.C

N.C

10

39

N.C

N.C

N.C

N.C

11

38

N.C

N.C

Vcc

Vcc

12

37

Vcc

Vcc

Vss

Vss

13

36

Vss

N.C

N.C

N.C

14

35

N.C

N.C

N.C

N.C

15

34

N.C

N.C

CLE

CLE

16

33

N.C

I/O11

ALE

ALE

17

32

I/O3

I/O3

WE

WE

18

31

I/O2

I/O10

WP

WP

19

30

I/O1

I/O2

N.C

N.C

20

29

I/O0

I/O9

N.C

N.C

21

28

N.C

I/O1

N.C

N.C

22

27

N.C

I/O8

N.C

N.C

23

26

N.C

I/O0

N.C

N.C

24

25

N.C

Vss

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F

+0.07 0.03-		+0.003 0.001-		#1
0.20		0.008

0.50	0.0197

#24

TYP
0.25	0.010

0~8¡Æ

20.00±0.20

0.787±0.008

18.40±0.10

0.724±0.004

Unit :mm/Inch

MAX
0.10	0.004

#48

)
0.25	0.010
(

MAX		12.00	0.472
12.40	0.488

#25

1.00±0.05				0.05		MIN
0.039±0.002					0.002

+0.075 0.035		+0.003 0.001-				1.20
						0.047MAX
0.125		0.005

		0.45~0.75																					0.50
																				(				)
	0.018~0.030
																							0.020

4

K9F5608U0B-VCB0,VIB0,FCB0,FIB0

K9F5608Q0B-DCB0,DIB0,HCB0,HIB0

K9F5616Q0B-DCB0,DIB0,HCB0,HIB0

K9F5608U0B-YCB0,YIB0,PCB0,PIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-DCB0,DIB0,HCB0,HIB0

PIN CONFIGURATION (TBGA)

X8

K9F56XXX0B-DCB0,HCB0/DIB0,HIB0

X16

DNU DNU

DNU DNU

DNU DNU

DNU DNU

DNU

DNU DNU

DNU

DNU DNU

/WP

ALE

Vss

/CE

/WE

R/B

/WP

ALE

Vss

/CE

/WE

R/B

NC

/RE

CLE

NC

NC

NC

NC

/RE

CLE

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

I/O5

I/O7

NC

NC

I/O0

NC

NC

NC

Vcc

I/O8

I/O1

I/O10

I/O12

IO14

Vcc

NC

I/O1

NC

VccQ

I/O5

I/O7

I/O0

I/O9

I/O3

VccQ

I/O6

I/O15

Vss

I/O2

I/O3

I/O4

I/O6

Vss

Vss

I/O2

I/O11 I/O4

I/O13

Vss

DNU DNU

DNU DNU

DNU DNU

DNU DNU

DNU DNU

DNU DNU

DNU DNU

DNU DNU

(Top View)

(Top View)

PACKAGE DIMENSIONS

63-Ball TBGA (measured in millimeters)

Top View		Bottom View

9.00±0.10

#A1

11.00±0.10

9.00±0.10

A

0.80

x9=

7.20

x5=

0.80

4.00

0.80

B

(Datum A)

6 5

4

3 2

1

A

0.80

(Datum B)

B

C

x7=0.805.60

x11=0.808.80

2.80

D

11.000.10±

E

F

G

H

63- 0.45±0.05

0.20 M A B	2.00

Side View

9.00±0.10

0.08MAX 0.45±0.05

	0.32±0.05		0.90±0.10

5

K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0	K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0	K9F5616U0B-YCB0,YIB0,PCB0,PIB0	FLASH MEMORY
K9F5608U0B-DCB0,DIB0,HCB0,HIB0	K9F5616U0B-DCB0,DIB0,HCB0,HIB0

PIN CONFIGURATION (WSOP1)

K9F5608U0B-VCB0,FCB0/VIB0,FIB0

N.C						1	48		N.C
N.C						2	47		N.C
DNU						3	46		DNU
N.C						4	45		N.C
N.C						5	44		I/O7
N.C						6	43		I/O6
		R/B				7	42		I/O5
		RE				8	41		I/O4
		CE				9	40		N.C
DNU						10	39		DNU
N.C						11	38		N.C
Vcc						12	37		Vcc
Vss						13	36		Vss
N.C						14	35		N.C
DNU						15	34		DNU
CLE						16	33		N.C
	ALE					17	32		I/O3
	WE					18	31		I/O2
	WP					19	30		I/O1
N.C						20	29		I/O0
N.C						21	28		N.C
DNU						22	27		DNU
N.C						23	26		N.C
N.C						24	25		N.C

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48 - WSOP1 - 1217F

Unit :mm

0.70 MAX

15.40±0.10

0.58±0.04

#1

#48

+0.07	-0.03
0.16
+0.07	-0.03
0.20

0.50TYP	(0.50±0.06)
	#24	#25
		(0.1Min)

10.0±00.12

+0.075 -0.035

0.10	0
	°
	~
	8
	°

0.45~0.75

17.00±0.20

6

K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0	K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0	K9F5616U0B-YCB0,YIB0,PCB0,PIB0	FLASH MEMORY
K9F5608U0B-DCB0,DIB0,HCB0,HIB0	K9F5616U0B-DCB0,DIB0,HCB0,HIB0

PIN DESCRIPTION

Pin Name	Pin Function
	DATA INPUTS/OUTPUTS
I/O0 ~ I/O7	The I/O pins are used to input command, address and data, and to output data during read operations. The
(K9F5608X0B)	I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O0 ~ I/O15	I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
(K9F5616X0B)	ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
	output.

						COMMAND LATCH ENABLE
	CLE					The CLE input controls the activating path for commands sent to the command register. When active high,
						commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
						ADDRESS LATCH ENABLE
	ALE					The ALE input controls the activating path for address to the internal address registers. Addresses are
						latched on the rising edge of WE with ALE high.
						CHIP ENABLE
						The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
		CE
						the device does not return to standby mode in program or erase opertion. Regarding CE control during read
						operation, refer to ’Page read’section of Device operation.
						READ ENABLE
		RE				The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
						tREA after the falling edge of RE which also increments the internal column address counter by one.
						WRITE ENABLE
		WE				The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
						the WE pulse.
						WRITE PROTECT
		WP				The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
						generator is reset when the WP pin is active low.
						READY/BUSY OUTPUT
						The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
	R/B
						random read operation is in process and returns to high state upon completion. It is an open drain output and
						does not float to high-z condition when the chip is deselected or when outputs are disabled.
						OUTPUT BUFFER POWER
	VccQ					VCCQ is the power supply for Output Buffer.
						VccQ is internally connected to Vcc, thus should be biased to Vcc.
	Vcc					POWER
						VCC is the power supply for device.
	Vss					GROUND
	N.C					NO CONNECTION
						Lead is not internally connected.
						GND INPUT FOR ENABLING SPARE AREA
	GND					To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
						or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.
	DNU					DO NOT USE
						Leave it disconnected.

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

7

	K9F5608U0B-VCB0,VIB0,FCB0,FIB0
	K9F5608Q0B-DCB0,DIB0,HCB0,HIB0		K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
	K9F5608U0B-YCB0,YIB0,PCB0,PIB0		K9F5616U0B-YCB0,YIB0,PCB0,PIB0		FLASH MEMORY
	K9F5608U0B-DCB0,DIB0,HCB0,HIB0		K9F5616U0B-DCB0,DIB0,HCB0,HIB0
	Figure 1-1. K9F5608X0B (X8) FUNCTIONAL BLOCK DIAGRAM
	VCC
	VSS
	A9 - A24	X-Buffers		256M + 8M Bit
		Latches
		& Decoders		NAND Flash
				ARRAY
	A0 - A7	Y-Buffers
		Latches
		& Decoders		(512 + 16)Byte x 65536
				Page Register & S/A
	Command	A8		Y-Gating
		Command
		Register		I/O Buffers & Latches		VCC/VCCQ
						VSS
	CE	Control Logic
	RE	& High Voltage			Output	I/0 0
	WE	Generator		Global Buffers
					Driver	I/0 7
		CLE ALE	WP
	Figure 2-1. K9F5608X0B (X8) ARRAY ORGANIZATION

64K Pages

(=2,048 Blocks)

			1 Block =32 Pages
			= (16K + 512) Byte
			1	Page = 528 Byte
			1	Block = 528 Byte x 32 Pages
	1st half Page Register	2nd half Page Register		= (16K + 512) Byte
			1	Device = 528Bytes x 32Pages x 2048 Blocks
	(=256 Bytes)	(=256 Bytes)
				= 264 Mbits
			8 bit
	512Byte		16 Byte

I/O 0 ~ I/O 7

Page Register

512 Byte

16 Byte

	I/O 0	I/O 1	I/O 2	I/O 3	I/O 4	I/O 5	I/O 6	I/O 7
1st Cycle	A0	A1	A2	A3	A4	A5	A6	A7
2nd Cycle	A9	A10	A11	A12	A13	A14	A15	A16
3rd Cycle	A17	A18	A19	A20	A21	A22	A23	A24

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register.

*A8 is set to "Low" or "High" by the 00h or 01h Command.

*The device ignores any additional input of address cycles than reguired.

Column Address

Row Address

(Page Address)

8

	K9F5608U0B-VCB0,VIB0,FCB0,FIB0
	K9F5608Q0B-DCB0,DIB0,HCB0,HIB0		K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
	K9F5608U0B-YCB0,YIB0,PCB0,PIB0		K9F5616U0B-YCB0,YIB0,PCB0,PIB0		FLASH MEMORY
	K9F5608U0B-DCB0,DIB0,HCB0,HIB0		K9F5616U0B-DCB0,DIB0,HCB0,HIB0
	Figure 1-2. K9F5616X0B (X16) FUNCTIONAL BLOCK DIAGRAM
	VCC
	VSS
	A9 - A24	X-Buffers		256M + 8M Bit
		Latches
		& Decoders		NAND Flash
				ARRAY
	A0 - A7	Y-Buffers
		Latches
		& Decoders		(256 + 8)Word x 65536
				Page Register & S/A
	Command			Y-Gating
		Command
		Register		I/O Buffers & Latches		VCC/VCCQ
						VSS
	CE	Control Logic
	RE	& High Voltage			Output	I/0 0
	WE	Generator		Global Buffers
					Driver	I/0 15
		CLE ALE	WP
	Figure 2-2. K9F5616X0B (X16) ARRAY ORGANIZATION

64K Pages

(=2,048 Blocks)

		1 Block =32 Pages
		= (8K + 256) Word
		1 Page = 264 Word
		1 Block = 264 Word x 32 Pages
	Page Register	= (8K + 256) Word
		1 Device = 264Words x 32Pages x 2048 Blocks
	(=256 Words)
		= 264 Mbits
		16 bit
	256Word	8 Word

		I/O 0 ~ I/O 15
	Page Register

			256 Word			8 Word
	I/O 0	I/O 1	I/O 2		I/O 3	I/O 4	I/O 5	I/O 6	I/O 7	I/O8 to 15
1st Cycle	A0	A1	A2		A3	A4	A5	A6	A7	L*	Column Address
2nd Cycle	A9	A10	A11		A12	A13	A14	A15	A16	L*	Row Address
3rd Cycle	A17	A18	A19		A20	A21	A22	A23	A24	L*	(Page Address)

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

9

K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0	K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0	K9F5616U0B-YCB0,YIB0,PCB0,PIB0	FLASH MEMORY
K9F5608U0B-DCB0,DIB0,HCB0,HIB0	K9F5616U0B-DCB0,DIB0,HCB0,HIB0

PRODUCT INTRODUCTION

The K9F56XXX0B is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528(X8 device) or 264(X16 device) columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8 device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structures. A NAND structure consists of 16 cells. Total 16896 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase operation is prohibited on the K9F56XXX0B.

The K9F56XXX0B has addresses multiplexed into 8 I/Os(X16 device case: lower 8 I/Os). K9F5616X0B allows sixteen bit wide data transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other commands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution. The 32M-byte(X8 device) or 16M-word(X16 device) physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F56XXX0B.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung.

Table 1. COMMAND SETS

Function	1st. Cycle	2nd. Cycle	Acceptable Command during Busy
Read 1	00h/01h(1)	-
Read 2	50h	-
Read ID	90h	-
Reset	FFh	-	O
Page Program	80h	10h
Copy-Back Program	00h	8Ah
Block Erase	60h	D0h
Read Status	70h	-	O

NOTE : 1. The 01h command is available only on X8 device(K9F5608X0B).

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

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K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0		K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0		K9F5616U0B-YCB0,YIB0,PCB0,PIB0				FLASH MEMORY
K9F5608U0B-DCB0,DIB0,HCB0,HIB0		K9F5616U0B-DCB0,DIB0,HCB0,HIB0
ABSOLUTE MAXIMUM RATINGS
Parameter			Symbol	Rating			Unit
				K9F56XXQ0B(1.8V)		K9F56XXU0B(3.3V)
			VIN/OUT	-0.6 to + 2.45		-0.6 to + 4.6
Voltage on any pin relative to VSS							V
			VCC	-0.2 to + 2.45		-0.6 to + 4.6
			VCCQ	-0.2 to + 2.45		-0.6 to + 4.6
Temperature Under Bias	K9F56XXX0B-XCB0		TBIAS	-10 to +125			°C
	K9F56XXX0B-XIB0			-40 to +125
Storage Temperature	K9F56XXX0B-XCB0		TSTG	-65 to +150			°C
	K9F56XXX0B-XIB0
Short Circuit Current			Ios		5		mA

NOTE:

1.Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F56XXX0B-XCB0 :TA=0 to 70°C, K9F56XXX0B-XIB0 :TA=-40 to 85°C)

Parameter	Symbol		K9F56XXQ0B(1.8V)					K9F56XXU0B(3.3V)				Unit
		Min		Typ.		Max	Min		Typ.		Max
Supply Voltage	VCC	1.70		1.8		1.95	2.7		3.3		3.6	V
Supply Voltage	VCCQ	1.70		1.8		1.95	2.7		3.3		3.6	V
Supply Voltage	VSS	0		0		0	0		0		0	V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

	Parameter				Symbol					Test Conditions							K9F56XXQ0B(1.8V)			K9F56XXU0B(3.3V)			Unit
																	Min	Typ	Max	Min	Typ	Max
Operat-		Sequential Read			ICC1				tRC=50ns, CE=VIL								-	8	15	-	10	20
									IOUT=0mA
ing
Current		Program			ICC2				-								-	8	15	-	10	20	mA
		Erase			ICC3				-								-	8	15	-	10	20
Stand-by Current(TTL)					ISB1				CE=VIH, WP=0V/VCC								-	-	1	-	-	1
Stand-by Current(CMOS)					ISB2				CE=VCC-0.2, WP=0V/VCC								-	10	50	-	10	50
Input Leakage Current					ILI				VIN=0 to Vcc(max)								-	-	±10	-	-	±10	μA
Output Leakage Current					ILO				VOUT=0 to Vcc(max)								-	-	±10	-	-	±10
									I/O pins								VCCQ-0.4	-	VCCQ	2.0	-	VCCQ+0.3
																			+0.3
Input High Voltage					VIH
									Except I/O pins								VCC-0.4	-	VCC	2.0	-	VCC+0.3
																			+0.3
																							V
Input Low Voltage, All inputs					VIL				-								-0.3	-	0.4	-0.3	-	0.8
Output High Voltage Level					VOH				K9F56XXQ0B :IOH=-100μA								VCCQ-0.1	-	-	2.4	-	-
									K9F56XXU0B :IOH=-400μA
Output Low Voltage Level					VOL				K9F56XXQ0B :IOL=100uA								-	-	0.1	-	-	0.4
									K9F56XXU0B :IOL=2.1mA
									K9F56XXQ0B :VOL=0.1V
Output Low Current(R/B)					IOL(R/B)												3	4	-	8	10	-	mA
									K9F56XXU0B :VOL=0.4V

11