Samsung KS88C01632, KS88C01624, KS88C01532, KS88C01524, S3C80G9 Datasheet

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)	PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS

Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

—Efficient register-oriented architecture

—Selectable CPU clock sources

—Idle and Stop power-down mode release by interrupt

—Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.

S3C80F7/C80F9/C80G7/C80G9 Microcontroller

The S3C80F7/C80F9/C80G7/C80G9 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture.

The S3C80F9/C80G9 is the microcontroller which has 32-Kbyte mask-programmable ROM and S3C80F7/C80G7 is the microcontroller which has 24-Kbyte mask-programmable ROM.

The S3P80F9/P80G9 is the microcontroller which has 32-Kbyte one-time-programmable EPROM and S3P80F7/P80G7 is the microcontroller which has 24-Kbyte one-time-programmable EPROM.

Using a proven modular design approach, Samsung engineers developed S3C80F7/C80F9/C80G7/C80G9 by integrating the following peripheral modules with the powerful SAM87 RC core:

—Internal LVD circuit and 16 bit-programmable pins for external interrupts.

—One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).

—One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.

—One 8-bit counter with auto-reload function and one-shot or repeat control.

The S3C80F7/C80F9/C80G7/C80G9 is a versatile general-purpose microcontroller which is especially suitable for use as remote transmitter controller. It is currently available in a 32-pin SOP, 42-pin SDIP and 44-pin QFP package.

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PRODUCT OVERVIEW	S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

FEATURES

CPU

∙SAM87RC CPU core

Memory

∙32-Kbyte internal ROM (S3C80F9/C80G9)

:0000H–7FFFH

∙24-Kbyte internal ROM (S3C80F7/C80G7)

:0000H–5FFFH

∙Data memory: 272-byte RAM (318 register)

Instruction Set

∙78 instructions

∙IDLE and STOP instructions added for powerdown modes

Instruction Execution Time

∙500 ns at 8-MHz fOSC (minimum)

Interrupts

∙22 interrupt sources with 16 vector and 7 level.

I/O Ports

∙Three 8-bit I/O ports (P0–P2), one 8-bit output port(P4) and 6-bit port (P3) for a total of 38 bitprogrammable pins.(44-QFP)

∙Three 8-bit I/O ports (P0–P2), one 8-bit output port(P4) and 4-bit port (P3) for a total of 36 bitprogrammable pins.(42-SDIP)

∙Three 8-bit I/O ports (P0–P2) and one 2-bit I/O port (P3) for a total of 26-bit programmable pins. (32-SOP)

Timers and Timer/Counters

∙One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer (software reset) function

∙One 8-bit timer/counter (Timer 0) with three operating modes; Interval mode, Capture and PWM mode.

∙One 16-bit timer/counter (Timer1) with two operating modes; Interval mode and Capture.

Carrier Frequency Generator

∙One 8-bit counter with auto-reload function and one-shot or repeat control (Counter A)

Back-up mode

∙When VDD is lower than VLVD, the chip enters Back-up mode to block oscillation and reduce the current consumption.

In S3C80G7/C80G9, this function is disabled when operating state is “STOP mode”.

∙When RESET pin is lower than Input Low Voltage (VIL), the chip enters Back-up mode to block oscillation and reduce the current consumption.

Low Voltage Detect Circuit

∙Low voltage detect to get into Back-up mode.

∙Low level detect voltage

−S3C80F7/C80F9: 2.20 V (Typ) ± 200mV

−S3C80G7/C80G9: 1.90 V (Typ) ± 200mV

Operating Temperature Range

∙–40 °C to + 85 °C

Operating Voltage Range

∙ 1.7V to 5.0V at 4 MHz fOSC (S3C80G7/C80G9)

∙2.0V to 5.0V at 8 MHz fOSC (S3C80F7/C80F9)

Package Type

∙44-pin QFP-1010B

∙42-pin SDIP

∙32-pin SOP

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S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)	PRODUCT OVERVIEW

BLOCK DIAGRAM

P0.0-0.3 (INT0-INT3)

P1.0-P1.7

P0.4-P0.7 (INT4)

TEST

VDD

LVD

Port 0

Port 1

RESET

XIN

MAIN

P2.0-2.3 (INT5-INT8)

OSC

XOUT

Port 2

8-Bit	I/O Port and Interrupt	P2.4-2.7 (INT9)
	Control
Basic
Timer		P3.0-T0PWM/
		T0CAP/(T1CAP)
8-Bit		P3.1-REM/(T0CK)
Timer/	Port 3	P3.2/(T0CK)
Counter	SAM87RC	P3.3/(T1CAP)
	CPU	P3.4-3.5
16-Bit
Timer/
Counter

32K-Bytes	317-Bytes			Port 4			P4.0-4.7
	Register
ROM
	File

Carrier

Registor

(Counter A)

Figure 1-1. Block Diagram

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PRODUCT OVERVIEW	S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

PIN ASSIGNMENTS

								P4.3
P4.2		1				42
P4.1		2				41		P0.7/INT4
P4.0		3				40		P0.6/INT4
P2.0/INT5		4				39		P0.5/INT4
P2.1/INT6		5				38		P0.4/INT4
P2.2/INT7		6				37		P0.3/INT3
P2.3/INT8		7				36		P0.2/INT2
P2.4/INT9		8	S3C80F7/C80F9			35		P0.1/INT1
P3.0/T0PWM/T0CAP/SDAT		9	/C80G7/C80G9			34		P0.0/INT0
R3.1/REM/SCLK		10				33		P4.4
VDD		11	(Top View)			32		P4.5
VSS		12				31		P4.6
XOUT		13	42-SDIP			30		P1.7
XIN		14				29		P1.6
TEST		15				28		P1.5
P2.5/INT9		16				27		P1.4
P2.6/INT9		17				26		P1.3
RESET		18				25		P1.2
P2.7/INT9		19				24		P1.1
P1.0		20				23		P4.7
P3.2/T0CK		21				22		P3.3/T1CAP

Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)

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S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)	PRODUCT OVERVIEW

		P0.3/INT3			P0.2/INT2			P0.1/INT1			P0.0/INT0			P4.4			P4.5			P4.6			P1.7			P1.6			P1.5			P1.4
		33			32			31			30			29			28			27			26			25			24			23
P0.4/INT4		34																														22				P1.3
P0.5/INT4		35				S3C80F7/C80F9																										21				P1.2
P0.6/INT4		36																														20				P1.1
P0.7/INT4		37					/C80G7/C80G9																									19				P4.7
																																				P3.3/T1CAP
P4.3		38																														18
P4.2		39										(Top View)																				17				P3.2/T0CK
P4.1		40																														16				P1.0
P4.0		41									(44-QFP)																					15				P2.7/INT9
P2.0/INT5		42																														14				P3.5
P2.1/INT6		43																														13				P3.4
P2.2/INT7		44																														12				RESET
		1 2 3 4 5 6 7 8 9 10 11
		P2.3/INT8			P2.4/INT9			P3.0/T0PWM/T0CAP/SDAT			P3.1/REM/SCLK			VDD			VSS			XOUT			XIN			TEST			P2.5/INT9			P2.6/INT9

Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)

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PRODUCT OVERVIEW	S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

VSS		1		32		VDD
XIN		2		31		P3.1/REM/T0CK/SCLK
XOUT		3		30		P3.0/T0PWM/T0CAP/T1CAP/SDAT
TEST		4		29		P2.4/INT9
P2.5/INT9		5	S3C80F7/C80F9	28		P2.3/INT8
P2.6/INT9		6		27		P2.2/INT7
RESET		7	/C80G7/C80G9	26		P2.1/INT6
						P2.0/INT5
P2.7/INT9		8	(Top View)	25
P1.0		9		24		P0.7/INT4
P1.1		10		23		P0.6/INT4
P1.2		11	32-SOP	22		P0.5/INT4
P1.3		12		21		P0.4/INT4
P1.4		13		20		P0.3/INT3
P1.5		14		19		P0.2/INT2
P1.6		15		18		P0.1/INT1
P1.7		16		17		P0.0/INT0

Figure 1-4. Pin Assignment Diagram (32-Pin SOP Package)

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S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW

Table 1-1. Pin Descriptions of 44-QFP and 42-SDIP

Pin	Pin	Pin Description	Circuit	42 Pin	44 Pin	Shared
Names	Type		Type	No.	No.	Functions
P0.0–P0.7	I/O	I/O port with bit-programmable pins.	1	34–41	30–37	Ext. INT
		Configurable to input or push-pull output				(INT0 - 4)
		mode. Pull-up resistors can be assigned
		by software. Pins can be assigned
		individually as external interrupt inputs
		with noise filters, interrupt enable/
		disable, and interrupt pending control.
		SED & R circuit built in P0 for STOP
		releasing.
P1.0–P1.7	I/O	I/O port with bit-programmable pins.	2	20	16	–
		Configurable to input mode or output		24–30	20–26
		mode. Pin circuits are either push-pull or
		n-channel open-drain type.
P2.0–P2.3	I/O	I/O port with bit-programmable pins.	1	4–8,	42–44	Ext. INT
P2.4–P2.7		Configurable to input or push-pull output		16, 17	1,2,	(INT5–9)
		mode. Pull-up resistors can be assigned		19	10,11,
		by software. Pins can be assigned			15
		individually as external interrupt inputs
		with noise filters, interrupt enable/
		disable, and interrupt pending control.
		SED & R circuit built in P2 for STOP
		releasing.
P3.0	I/O	2-bit I/O port with bit-programmable pins.	3	9–10	3–4	T0PWM/ T0CAP
P3.1		Configurable to input mode, push-pull	4			REM
		output mode, or n-channel open-drain
		output mode. Input mode with pull-up
		resistors can be assigned by software.
		The two port 3 pins have high current
		drive capability
P3.2–P3.3	I	C-MOS Input port with pull-up resistors	5	21	17	(T0CK)
				22	18	(T1CAP)
P3.4–P3.5	O	Open drain output port for high current	6	None	13–14	–
		drive
P4.0–P4.7	O	8- bit-programmable output pins.	7	1–3	41–38	–
		Configurable to open drain output port or		42,23	27–29
		push-pull output port.		31-33	19
XIN, XOUT	–	System clock input and output pins	–	13,14	7,8	–
RESET	I	System reset signal input pin and back-	8	18	12	–
		up mode input.
TEST	I	Test signal input pin (for factory use only;	–	15	9	–
		must be connected to VSS.)
VDD	–	Power supply input pin	–	11	5	–
VSS	–	Ground pin	–	12	6	–

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PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

Table 1-2. Pin Descriptions of 32-SOP

Pin	Pin	Pin Description	Circuit	32 Pin	Shared
Names	Type		Type	No.	Functions
P0.0–P0.7	I/O	I/O port with bit-programmable pins.	1	17–24	Ext. INT
		Configurable to input or push-pull output
		mode. Pull-up resistors are assignable by
		software. Pins can be assigned individually as
		external interrupt inputs with noise filters,
		interrupt enable/ disable, and interrupt pending
		control. SED & R circuit built in P0 for STOP
		releasing.
P1.0–P1.7	I/O	I/O port with bit-programmable pins.	2	9–16	–
		Configurable to input mode or output mode.
		Pin circuits are either push-pull or n-channel
		open-drain type.
P2.0–P2.3	I/O	I/O port with bit-programmable pins.	1	25–28	Ext. INT
P2.4–P2.7		Configurable to input or push-pull output		29,5, 6,8
		mode. Pull-up resistors can be assigned by
		software. Pins can be assigned individually as
		external interrupt inputs with noise filters,
		interrupt enable/disable, and interrupt pending
		control. SED & R circuit built in P2 for STOP
		releasing.
P3.0	I/O	2-bit I/O port with bit-programmable pins.	3	30,31	T0PWM/
P3.1		Configurable to input mode, push-pull output	4		T0CAP/T1CAP
		mode, or n-channel open-drain output mode.			REM/T0CK
		Input mode with pull-up resistors can be
		assigned by software. The two port 3 pins
		have high current drive capability.
XIN, XOUT	–	System clock input and output pins	–	2,3	–
RESET	I	System reset signal input pin and back-up	8	7	–
		mode input.
TEST	I	Test signal input pin (for factory use only;	–	4	–
		must be connected to VSS).
VDD	–	Power supply input pin	–	32	–
VSS	–	Ground pin	–	1	–

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S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)	PRODUCT OVERVIEW

PIN CIRCUITS

Pull-up

Enable

Data

Output

Disable

External	Noise
Interrupt	Filter

VDD

Pull-up

Resistor

VDD

Input/

Output

VSS

Stop release

Stop

Figure 1-5. Pin Circuit Type 1 (Port 0 and Port2)

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PRODUCT OVERVIEW	S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

PIN CIRCUITS (Continued)

	VDD
	Pull-up
	Resistor
Pull-up
Enable
	VDD
Data
	Input/
	Output
Open-Drain
Output Disable
	VSS
Normal	Noise
Input	Filter

Figure 1-6. Pin Circuit Type 2 (Port 1)

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S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)	PRODUCT OVERVIEW

PIN CIRCUITS (Continued)

VDD

Pull-up

Resistor

Pull-up

Enable

P3CON.2

		VDD
Port 3.0 Data	M	Data
T0_PWM	U
	X

	Open-Drain	P3.0/T0PWM
		T0CAP/(T1CAP)
	Output Disable

VSS

P3.0 Input

P3CON.2,6,7

M

T0CAP/(T1CAP) U Noise filter

X

Figure 1-7. Pin Circuit Type 3 (P3.0)

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